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2019-11-22drm/amd/display: add default clocks if not able to fetch themAlex Deucher1-1/+2
dm_pp_get_clock_levels_by_type needs to add the default clocks to the powerplay case as well. This was accidently dropped. Fixes: b3ea88fef321de ("drm/amd/powerplay: add get_clock_by_type interface for display") Bug: https://gitlab.freedesktop.org/drm/amd/issues/906 Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdgpu: Use ARRAY_SIZE for sos_old_versionszhengbin1-1/+1
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/psp_v3_1.c:182:40-41: WARNING: Use ARRAY_SIZE Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: zhengbin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amd/powerplay: Use ARRAY_SIZE for smu7_profilingzhengbin1-1/+1
Fixes coccicheck warning: drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c:4946:28-29: WARNING: Use ARRAY_SIZE Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: zhengbin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdkfd: Remove duplicate functions update_mqd_hiq()Yong Zhao3-32/+4
The functions are the same as update_mqd(). Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Zhan Liu <zhan.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10changzhu3-2/+116
It may lose gpuvm invalidate acknowldege state across power-gating off cycle. To avoid this issue in gmc9/gmc10 invalidation, add semaphore acquire before invalidation and semaphore release after invalidation. After adding semaphore acquire before invalidation, the semaphore register become read-only if another process try to acquire semaphore. Then it will not be able to release this semaphore. Then it may cause deadlock problem. If this deadlock problem happens, it needs a semaphore firmware fix. Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdgpu: initialize vm_inv_eng0_sem for gfxhub and mmhubchangzhu6-0/+13
SW must acquire/release one of the vm_invalidate_eng*_sem around the invalidation req/ack. Through this way,it can avoid losing invalidate acknowledge state across power-gating off cycle. To use vm_invalidate_eng*_sem, it needs to initialize vm_invalidate_eng*_sem firstly. Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amd/amdgpu/sriov skip RLCG s/r list for arcturus VF.Jack Zhang1-1/+4
After rlcg fw 2.1, kmd driver starts to load extra fw for LIST_CNTL,GPM_MEM,SRM_MEM. We needs to skip the three fw because all rlcg related fw have been loaded by host driver. Guest driver would load the three fw fail without this change. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amd/amdgpu/sriov temporarily skip ras,dtm,hdcp for arcturus VFJack Zhang1-0/+36
Temporarily skip ras,dtm,hdcp initialize and terminate for arcturus VF Currently the three features haven't been enabled at SRIOV, it would trigger guest driver load fail with the bare-metal path of the three features. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdgpu/gfx10: re-init clear state buffer after gpu resetXiaojie Yuan1-6/+37
This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x. clear state buffer (resides in vram) is corrupted after 1st baco reset, upon gfxoff exit, CPF gets garbage header in CSIB and hangs. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22merge fix for "ftrace: Rework event_create_dir()"Stephen Rothwell1-1/+1
Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdgpu: remove redundant assignment to pointer write_frameColin Ian King1-1/+1
The pointer write_frame is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdgpu: simplify runtime suspendAlex Deucher1-13/+22
In the standard _PR3 case, the pci core handles the pci state. The driver only needs to handle it in the legacy ATPX case. This may fix issues with runtime suspend/resume on certain hybrid graphics laptops. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdkfd: DIQ should not use HIQ way to allocate memoryYong Zhao4-4/+4
In the mqd_diq_sdma buffer, there should be only one HIQ mqd. All DIQs should be allocated somewhere else using the regular way. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdkfd: Delete KFD_MQD_TYPE_COMPUTEYong Zhao6-9/+4
It is the same as KFD_MQD_TYPE_CP, so delete it. As a result, we will have one less mqd mananger per device. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdgpu: Update Arcturus golden registersJay Cornwall1-0/+1
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdgpu: implement querying ras error count for mmhub9.4Dennis Li3-1/+257
Get mmhub error counter by accessing EDC_CNT registers. v2: Add mmhub_v9_4_ prefix for local static variable and function Signed-off-by: Dennis Li <dennis.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdgpu: refine query function of mmhub EDC counter in vg20Dennis Li6-364/+320
Add codes to print the detail EDC info for the subblock of mmhub v2: Move the EDC_CNT registers' defintion from mmhub_9_4 header files to mmhub_1_0 ones. Add mmhub_v1_0_ prefix for the local static variable and function. v3: squash in DC fix Signed-off-by: Dennis Li <dennis.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdgpu: define soc15_ras_field_entry for reuseDennis Li2-23/+23
The struct soc15_ras_field_entry will be reused by other IPs, such as mmhub and gc v2: rename ras_subblock_regs to gc_ras_fields_vg20, because the future asic maybe have a different table. Signed-off-by: Dennis Li <dennis.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdgpu/gfx10: fix out-of-bound mqd_backup array accessXiaojie Yuan1-2/+0
Fixes: 0bb419c76b3150 ("drm/amdgpu/gfx10: fix mqd backup/restore for gfx rings (v2)") Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdgpu/gfx10: explicitly wait for cp idle after halt/unhaltXiaojie Yuan1-2/+12
50us is not enough to wait for cp ready after gpu reset on some navi asics. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Suggested-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22amd/amdgpu: force to trigger a no-retry-fault after a retry-faultAlex Sierra1-1/+10
Only for the debugger use case. [why] Avoid endless translation retries, after an invalid address access has been issued to the GPU. Instead, the trap handler is forced to enter by generating a no-retry-fault. A s_trap instruction is inserted in the debugger case to let the wave to enter trap handler to save context. [how] Intentionally using an invalid flag combination (F and P set at the same time) to trigger a no-retry-fault, after a retry-fault happens. This is only valid under compute context. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-22drm/amdgpu: add flag to indicate amdgpu vm contextAlex Sierra2-0/+5
Flag added to indicate if the amdgpu vm context is used for compute or graphics. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: enable runtime pm on BACO capable boards if runpm=1Alex Deucher1-4/+7
BACO - Bus Active, Chip Off Everything is in place now. Not enabled by default yet. You still have to specify runpm=1. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: disentangle runtime pm and vga_switcherooAlex Deucher1-8/+14
Originally we only supported runtime pm on PX/HG laptops so vga_switcheroo and runtime pm are sort of entangled. Attempt to logically separate them. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: start to disentangle boco from runtime pmAlex Deucher3-8/+16
BACO - Bus Active, Chip Off BOCO - Bus Off, Chip Off We originally only supported runtime pm on PX/HG laptops so most of the runtime pm code looks for this. Add a new flag to check for runtime pm enablement and use this rather than checking for PX/HG. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: add baco support to runtime suspend/resumeAlex Deucher1-1/+6
BACO - Bus Active, Chip Off This adds the necessary support to the runtime suspend and resume functions to handle boards that support baco. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: add helpers for baco entry and exitAlex Deucher2-0/+63
BACO - Bus Active, Chip Off Will be used for runtime pm. Entry will enter the BACO state (chip off). Exit will exit the BACO state (chip on). Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: split swSMU baco_reset into enter and exitAlex Deucher9-13/+51
BACO - Bus Active, Chip Off So we can use it for power savings rather than just reset. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: add additional boco checks to runtime suspend/resume (v2)Alex Deucher1-21/+26
BACO - Bus Active, Chip Off BOCO - Bus Off, Chip Off We will take slightly different paths for boco and baco. v2: fold together two consecutive if clauses Reviewed-by: Evan Quan <evan.quan@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: rename amdgpu_device_is_px to amdgpu_device_supports_boco (v2)Alex Deucher4-12/+12
BACO - Bus Active, Chip Off BOCO - Bus Off, Chip Off To better match what we are checking for and to align with amdgpu_device_supports_baco. BOCO is used on PowerXpress/Hybrid Graphics systems and BACO is used on desktop dGPU boards. v2: fix typo in documentation Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: add a amdgpu_device_supports_baco helperAlex Deucher2-0/+16
BACO - Bus Active, Chip Off To check if a device supports BACO or not. This will be used in determining when to enable runtime pm. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: add supports_baco callback for NV asics.Alex Deucher1-0/+11
BACO - Bus Active, Chip Off Check the BACO capabilities from the powerplay table. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: add supports_baco callback for VI asics.Alex Deucher1-0/+22
BACO - Bus Active, Chip Off Check the BACO capabilities from the powerplay table. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: add supports_baco callback for CIK asics.Alex Deucher1-0/+18
BACO - Bus Active, Chip Off Check the BACO capabilities from the powerplay table. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: add supports_baco callback for SI asics.Alex Deucher1-0/+6
BACO - Bus Active, Chip Off Not supported. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: add supports_baco callback for soc15 asics. (v2)Alex Deucher1-0/+24
BACO - Bus Active, Chip Off Check the BACO capabilities from the powerplay table. v2: drop unrelated struct cleanup Reviewed-by: Evan Quan <evan.quan@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: add asic callback for BACO supportAlex Deucher1-0/+4
BACO - Bus Active, Chip Off Used to check whether the device supports BACO. This will be used to enable runtime pm on devices which support BACO. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amd/powerplay: enable gpu_busy_percent sys interface for renoir (v2)changzhu3-0/+113
To get the value of gpu_busy_percent, it needs to realize get_current_activity_percent and get_metrics_table. The framework of renoir smu is different from old ones like raven. It needs to realize get_current_activity_percent and get_metrics_table in renoir_ppt.c like navi10. v2: remove unused variable (Alex) Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: pull ras controller int status only when ras enabledHawking Zhang1-7/+10
ras_controller_irq and athub_err_event_irq are only registered when PCIE_BIF ras is marked as supported. as the result, the driver also just need pull the int status in such case. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: switch to common helper func for psp cmd submissionHawking Zhang6-231/+1
Drop all the IP specific cmd_submit callback function and use the common helper instead Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: add helper func for psp ring cmd submissionHawking Zhang2-0/+54
Except for ring wptr update, the psp ring cmd submission function shouldn't be IP specific one. Create a common helper function to be shared for all the ASICs. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: add psp funcs for ring write pointer read/writeHawking Zhang5-0/+100
The ring write pointer regsiter update is the only part that is IP specific ones in psp_cmd_submit function. Add two callbacks for wptr read/write so that we unify the psp_cmd_submit function for all the ASICs. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amd/powerplay: add missing header file declarationEvan Quan1-0/+1
This can fix the compile errors below: drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c: In function ‘smu_v11_0_baco_set_state’: drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1674:27: error: implicit declaration of function ‘amdgpu_ras_get_context’ [-Werror=implicit-function-declaration] struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); ^ drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1674:27: warning: initialization makes pointer from integer without a cast [-Wint-conversion] drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1692:19: error: dereferencing pointer to incomplete type ‘struct amdgpu_ras’ if (!ras || !ras->supported) { Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amd/powerplay: add Arcturus baco reset supportEvan Quan3-4/+18
Enable baco reset support on Arcturus. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amd/powerplay: correct swSMU baco reset related settingsEvan Quan1-3/+27
Added bif doorbell interrupt setting and applied different settings for BACO reset for RAS recovery. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19Revert "drm/amd/display: enable S/G for RAVEN chip"Alex Deucher2-2/+2
This reverts commit 1c4259159132ae4ceaf7c6db37a6cf76417f73d9. S/G display is not stable with the IOMMU enabled on some platforms. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205523 Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: disable gfxoff on original ravenAlex Deucher1-2/+7
There are still combinations of sbios and firmware that are not stable. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204689 Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: remove experimental flag for Navi14Alex Deucher1-4/+4
5.4 and newer works fine with navi14. Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu: disable gfxoff when using register read interfaceAlex Deucher1-1/+5
When gfxoff is enabled, accessing gfx registers via MMIO can lead to a hang. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497 Acked-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-19drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK (v2)Alex Deucher2-0/+11
So that the setting reflects what the hw supports. This will be used in a subsequent patch so needs to be correct. v2: squash in fix from Colin Ian King Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497 Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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