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2010-06-01drm/vmwgfx: Don't use SVGA_REG_ENABLE in modesetting code.Jakob Bornecrantz2-9/+0
We should not use SVGA_REG_ENABLE anywhere but in the fifo setup code, since it controls whether the device is active. Signed-off-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2010-06-01drm/vmwgfx: Remove duplicate member from struct vmw_legacy_display_unit.Jakob Bornecrantz1-4/+2
Signed-off-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2010-06-01drm/vmwgfx: Reserve first part of VRAM for framebuffer.Thomas Hellstrom1-2/+39
The host may be touching this part of VRAM at modesetting, even if we never use it ourselves, since we blit screen updates from 3D surfaces. Make sure no DMA buffers are placed in this part of VRAM. V2: Fix an error check in vmw_surface_dmabuf_pin(). Signed-off-by: Thomas Hellstrom <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2010-06-01drm/vmwgfx: Support older hardware.Jakob Bornecrantz6-107/+148
V2: Fix a couple of typos. Signed-off-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2010-06-01drm/vmwgfx: Get connector status from detection function.Jakob Bornecrantz1-7/+3
Also make sure the ldu::active member is properly initialized. Part of fix by Michel Daenzer <[email protected]>. Signed-off-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Michel Daenzer <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2010-06-01drm/vmwgfx: Add kernel throttling support. Bump minor.Thomas Hellstrom6-6/+227
The throttle_us member in the execbuf argument is now honored. If the member is 0, no waiting for lag will occur, which guarantees backwards compatibility with well-behaved clients. Signed-off-by: Thomas Hellstrom <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2010-06-01drm/vmwgfx: Make sure to unpin old and pin new framebuffer.Jakob Bornecrantz1-6/+11
Signed-off-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2010-06-01drm/vmwgfx: Fix single framebuffer detection.Jakob Bornecrantz1-0/+3
V2: Fix a typo. Signed-off-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2010-06-01drm/vmwgfx: Assume larger framebuffer max size.Jakob Bornecrantz1-2/+3
Signed-off-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2010-05-28Merge branch 'drm-linus' of ↵Linus Torvalds1-2/+3
git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 * 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/radeon: fix the r100/r200 ums block 0 page fix
2010-05-29drm/radeon: fix the r100/r200 ums block 0 page fixDave Airlie1-2/+3
airlied -> brown paper bag. I blame Hi-5 or the Wiggles for lowering my IQ, move the fix inside some brackets instead of breaking everything in site. Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]>
2010-05-28drm/i915: Unmask interrupt for render engine on SandybridgeZhenyu Wang1-0/+19
With splitted engines on Sandybridge, each engine has its own interrupt control as well. This unmasks the interrupt to properly enable pipe control notify event for render engine. Signed-off-by: Zhenyu Wang <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-28drm/i915: Fix PIPE_CONTROL command on SandybridgeZhenyu Wang1-2/+14
Sandybridge(Gen6) has new format for PIPE_CONTROL command, the flush and post-op control are in dword 1 now. This changes command length field for difference between Ironlake and Sandybridge. I tried to test this with noop request and issue PIPE_CONTROL command for each sequence and track notify interrupts, which seems work fine. Hopefully we don't need workaround like on Ironlake for Sandybridge. Signed-off-by: Zhenyu Wang <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-28drm/i915: Fix up address spaces in slow_kernel_write()Chris Wilson1-25/+17
Since we now get_user_pages() outside of the mutex prior to performing the copy, we kmap() the page inside the copy routine and so need to perform an ordinary memcpy() and not copy_from_user(). Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-28drm/i915: Use non-atomic kmap for slow copy pathsChris Wilson1-52/+30
As we do not have a requirement to be atomic and avoid sleeping whilst performing the slow copy for shmem based pread and pwrite, we can use kmap instead, thus simplifying the code. Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-28drm/i915: Avoid moving from CPU domain during pwriteChris Wilson1-1/+2
We can avoid an early clflush when pwriting if we use the current CPU write domain rather than moving the object to the GTT domain for the purposes of the pwrite. This has the advantage of not flushing the presumably hot data that we want to upload into the bo, and of ascribing the clflush to the execution when profiling. Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-28drm/i915: Cleanup after failed initialization of ringbuffersChris Wilson1-1/+18
The callers expect us to cleanup any partially initialised structures before reporting the error. Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-28drm/i915: Reject bind_to_gtt() early if object > apertureChris Wilson1-0/+8
If the object is bigger than the entire aperture, reject it early before evicting everything in a vain attempt to find space. v2: Use E2BIG as suggested by Owain G. Ainsworth. Signed-off-by: Chris Wilson <[email protected]> Cc: [email protected] Signed-off-by: Eric Anholt <[email protected]>
2010-05-28drm/i915: Check error code whilst moving buffer to GTT domain.Chris Wilson1-1/+5
Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-28drm/i915: Remove spurious warning "Failure to install fence"Chris Wilson1-6/+11
This particular warning is harmless as we emit during the normal pinning process where the batch buffer requires more fences than is available without eviction. Only if we fail to evict enough fences does this become a problem, so include the requested number of fences in the ultimate *error* message. v2: Remember to compile test even trial patches to remove warnings. Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-28drm/i915: Rebind bo if currently bound with incorrect alignment.Chris Wilson1-0/+11
Whilst pinning the buffer, check that that its current alignment matches the requested alignment. If it does not, rebind. This should clear up any final render errors whilst resuming, for reference: Bug 27070 - [i915] Page table errors with empty ringbuffer https://bugs.freedesktop.org/show_bug.cgi?id=27070 Bug 15502 - render error detected, EIR: 0x00000010 https://bugzilla.kernel.org/show_bug.cgi?id=15502 Bug 13844 - i915 error: "render error detected" https://bugzilla.kernel.org/show_bug.cgi?id=13844 Signed-off-by: Chris Wilson <[email protected]> Cc: [email protected] Signed-off-by: Eric Anholt <[email protected]>
2010-05-28drm/i915: Include pitch in set_base debug statement.Chris Wilson1-1/+2
Add the pitch that we about to write into the control register along with the base, offset and coordinates that go into the other control registers. Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-28drm/i915: Only print "nothing to do" debug message as required.Chris Wilson1-2/+3
If the FBC is already disabled, then we do not even attempt to disable FBC and so there is no point emitting a debug statement at that point, having already emitted one saying why we are disabling FBC. Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-28drm/i915: Propagate error from unbinding an unfenceable object.Chris Wilson1-3/+7
Signed-off-by: Chris Wilson <[email protected]> Cc: Jesse Barnes <[email protected]> Reviewed-by: Jesse Barnes <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-28drm/i915: Avoid nesting of domain changes when setting display planeChris Wilson1-5/+3
Nesting domain changes will cause confusion when trying to interpret the tracepoints describing the sequence of changes for the object, as well as obscuring the order of operations for the reader of the code. Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-28drm/i915: Hold the spinlock whilst resetting unpin_work along error pathChris Wilson1-8/+12
Delay taking the mutex until we need to and ensure that we hold the spinlock when resetting unpin_work on the error path. Also defer the debugging print messages until after we have released the spinlock. Signed-off-by: Chris Wilson <[email protected]> Cc: Jesse Barnes <[email protected]> Cc: Kristian Høgsberg <[email protected]> Reviewed-by: Jesse Barnes <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-28drm/i915: Only print an message if there was an errorChris Wilson1-14/+24
Only report an error if the GPU has actually detected one, otherwise we are just hung. Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-28drm/nv50: use alternate source of SOR_MODE_CTRL for DP hackBen Skeggs1-6/+1
Fixes module unload+reload on Dell M4500, where the "normal" registers get reset to 0. Signed-off-by: Ben Skeggs <[email protected]>
2010-05-28drm/nouveau: fix dual-link displays when plugged into single-link outputsBen Skeggs1-14/+17
When selecting the native mode for a display we weren't taking into account whether or not it was actually supported on that particular output. This patch modifies our native mode selection to run all modes through mode_valid() first. Signed-off-by: Ben Skeggs <[email protected]>
2010-05-28drm/nv50: obey dcb->duallink_possibleBen Skeggs1-2/+1
It was once assumed that all G8x had dual-link TMDS everywhere, this isn't actually the case - especially considering passive DP->DVI converters and some HDMI connectors only support single-link. Signed-off-by: Ben Skeggs <[email protected]>
2010-05-28drm/nv50: fix duallink_possible calculation for DCB 4.0 cardsBen Skeggs1-6/+10
Signed-off-by: Ben Skeggs <[email protected]>
2010-05-28drm/nouveau: don't execute INIT_GPIO unless we're really running the tableBen Skeggs1-1/+4
This resulted in accidently switching off the eDP panel on certain laptops since the default state in the GPIO table was off. Fixes rh#582621 Signed-off-by: Ben Skeggs <[email protected]>
2010-05-28drm/nv40: allow cold-booting of nv4x chipsetsBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <[email protected]>
2010-05-28drm/nouveau: fix POST detection for certain chipsetsBen Skeggs1-3/+25
We totally fail at detecting un-POSTed chipsets prior to G80. This commit changes the pre-G80 POST detection to read the programmed horizontal total from CRTC 0, and assume the card isn't POSTed if it's 0. NVIDIA use some other heuristics more similar to what we do on G80, but I wasted quite a long time trying to figure out the exact specifics of what they do so we can try this for a bit instead. Signed-off-by: Ben Skeggs <[email protected]>
2010-05-28drm/nouveau: Add getparam for current PTIMER time.Marcin Kościelnicki1-0/+3
This will be useful for computing GPU-CPU latency, including GL_ARB_timer_query extension. Signed-off-by: Marcin Kościelnicki <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2010-05-28drm/nouveau: allow cursor image and position to survive suspendMaarten Maathuis4-0/+33
- This isn't triggered yet on a normal kernel, because it still does a VT switch, but it seemed like a good idea to fix this now. Tested-by: Maxim Levitsky <[email protected]> Signed-off-by: Maarten Maathuis <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2010-05-26drm/i915: Clean up leftover bits from hws move to ring structure.Eric Anholt3-10/+6
Fixes /debug/dri/0/i915_gem_interrupt output for status page. Signed-off-by: Eric Anholt <[email protected]>
2010-05-26drm/i915: Add CxSR support on Pineview DDR3Li Peng4-29/+53
Pineview with DDR3 memory has different latencies to enable CxSR. This patch updates CxSR latency table to add Pineview DDR3 latency configuration. It also adds one flag "is_ddr3" for checking DDR3 setting in MCHBAR. Cc: Shaohua Li <[email protected]> Cc: Zhao Yakui <[email protected]> Signed-off-by: Li Peng <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-26i915: remove unneeded null checksDan Carpenter1-2/+2
The "encoder" variable can never be null because it is used as loop cursor in a list_for_each_entry() loop. Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-26i915/intel_sdvo: remove unneeded null checkDan Carpenter1-1/+1
The "connector" variable is used as the cursor in a list_for_each_entry() and it's always non-null so we don't need to check it. Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-26drm/i915: Fix HDMI mode select for Cougarpoint PCHZhenyu Wang2-1/+7
For real HDMI sink, CPT HDMI port has to set 'HDMI' mode flag in order to make HDMI audio work correctly. This is required patch for drm/i915 to enable HDMI audio on CPT PCH, ALSA patch is at http://mailman.alsa-project.org/pipermail/alsa-devel/2010-May/027601.html Tested-by: Fengguang Wu <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-26drm/i915: combine all small integers into one single bitfieldDaniel Vetter2-26/+54
This saves a whooping 7 dwords. Zero functional changes. Because some of the refcounts are rather tightly calculated, I've put BUG_ONs in the code to check for overflows. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-26drm/i915/dp: Add DPCD data to debug outputAdam Jackson1-0/+2
Signed-off-by: Adam Jackson <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-26drm/i915/dp: Only enable enhanced framing if the sink supports itAdam Jackson1-3/+2
DisplayPort spec v1.1a, Table 2-52. Signed-off-by: Adam Jackson <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-26drm/i915: Kill dangerous pending-flip debuggingChris Wilson1-6/+0
We can, by virtue of a vblank interrupt firing in the middle of setting up the unpin work (i.e. after we set the unpin_work field and before we write to the ringbuffer) enter intel_finish_page_flip() prior to receiving the pending flip notification. Therefore we can expect to hit intel_finish_page_flip() under normal circumstances without a pending flip and even without installing the pending_flip_obj. This is exacerbated by aperture thrashing whilst binding the framebuffer References: Bug 28079 - "glresize" causes kernel panic in intel_finish_page_flip. https://bugs.freedesktop.org/show_bug.cgi?id=28079 Reported-by: Nick Bowler <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: Jesse Barnes <[email protected]> Cc: [email protected] Reviewed-by: Jesse Barnes <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-26drm/i915: Storage class should be before const qualifierTobias Klauser1-19/+19
The C99 specification states in section 6.11.5: The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature. Signed-off-by: Tobias Klauser <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-26drm/i915: add power monitoring supportJesse Barnes6-53/+772
Add power monitoring support to the i915 driver for use by the IPS driver. Export the available power info to the IPS driver through a few new inter-driver hooks. When used together, the IPS driver and this patch can significantly increase graphics performance on Ironlake class chips. Signed-off-by: Jesse Barnes <[email protected]> [anholt: Fixed 32-bit compile. stupid obfuscating div_u64()] Signed-off-by: Eric Anholt <[email protected]>
2010-05-26drm/i915/gen4: Extra CRT hotplug paranoiaAdam Jackson2-8/+14
Disable the CRT plug interrupt while doing the force cycle, explicitly clear any CRT interrupt we may have generated, and restore when done. Should mitigate interrupt storms from hotplug detection. Signed-off-by: Adam Jackson <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-26drm/i915: Add support for interlaced display.Krzysztof Halasa2-1/+15
This doesn't change the clock limits (minimums), i.e. it won't make it output 720x576 PAL nor 720x480 NTSC, but it will work with modes like 1080i etc. (including GLX and textured Xvideo, not sure about the overlay). Tested on i915 + analog VGA, it would be worth checking if newer chips (and which ones) still support interlaced mode. Signed-off-by: Krzysztof Halasa <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
2010-05-26i915: fix lock imbalance on error path...Daniel J Blueman1-0/+1
While investigating Intel i5 Arrandale GPU lockups with -rc4, I noticed a lock imbalance. Signed-off-by: Daniel J Blueman <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
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