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2017-10-21drm/amd/display: fix bug in force_single_disp_pipe_splitTony Cheng1-1/+4
should only lower dpp clock. Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: option to maximize lb usageTony Cheng2-2/+9
experimental change for testing if max line buffer result in better stutter efficiency for 1080p, LB can hold up to 9 line at 10bpcc, potentially add 10 line time of latency hiding. Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: add option to disable DCC for DCC 128b requestTony Cheng2-13/+16
1. reverts commit e67f51012740 ("dc: temp disable DCC on high res.") - default still DCC enabled 2. add debug options to decide how DCC is disabled - disable DCC - disable DCC if DCC requires 128b (aka. half) request -- observed compressed data corruption result in screen corruption in full (256b) request while half (128b) would cause DCN to hang, result in DF hang Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: enable optional pipe split for single displayTony Cheng3-10/+51
also refactor debug option. now pipe_split_policy are dynamic = no hack around dcn_calcs. will split based on HW recommendation avoid = avoid split if we can support the config with higher voltage avoid_multi_display = allow split with single display output. force_single_disp_pipe_split force single display to pipe split to improve stutter efficiency by using DET buffers using 2 HUBP. Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: temp disable DCC on high res.Charlene Liu1-2/+9
Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: Fix MST daisy chain SST not light upJerry Zuo1-61/+49
In SST daisy chain scenario, edid is getting read in mst hotplug routine. It is getting conflict with drm send_enum_path_resources kernel thread in terms of i2c bus which is getting locked up in such case. Have edid being read in get_mode hook, instead of in hotplug routine. Signed-off-by: Jerry Zuo <[email protected]> Reviewed-by: Roman Li <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: Only reset top pipe back end.Yongqiang Sun1-0/+3
Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: Early return when turn off a plane.Yongqiang Sun1-1/+7
In case of two monitor connected and turn off one of the monitors, OTG0 is locked after graphic plane off due to redundant programming front end regs. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: Program stream's csc matrix instead of using defaultSivapiriyanKumarasamy1-4/+3
Signed-off-by: SivapiriyanKumarasamy <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: update link type to mst before topology discoveryWenjing Liu1-3/+3
[Description] link type is not updated before mst topology discovery. This causes issue when branch device response to link address after before the start topology discovery event finishes. [Solution] update link type to mst before topology discovery Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: Use active + border for bw validationEric Yang1-3/+5
When doing SLS, KMD gives us clipped v_addressable with border. This results in bw validation failure. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: Fixed incorrect return value for validatonYongqiang Sun1-4/+5
Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: screen flickers when connected to ext monitor in cloneHersen Wu3-0/+12
Signed-off-by: Hersen Wu <[email protected]> Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: version 3.1.02Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: Fixed validation return wrong result.Yongqiang Sun3-3/+3
Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: add hubp/dpp pg debug keyCharlene Liu1-0/+2
Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: make sure BL off to mainlink off has enough timeCharlene Liu1-7/+0
Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: fix ASSERT() caused by missing registers.Ken Chalmers1-19/+23
Signed-off-by: Ken Chalmers <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: edp backlight regression fixYue Hin Lau2-0/+6
Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: moving backlight registers to hwsequencerYue Hin Lau9-127/+158
Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: update blending mode and set output denormEric Bernstein2-1/+30
Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: add back removed hack for mpcc addEric Yang1-0/+12
A previous changed removed the hack to match mpcc_idd with mi instance. This causes pstate hang on resume from hibernate for yet unknown reason. Add the hack back for now to work around the issue. More debugging required in init_hw to root cause the hang. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: set cp25201 to use TPS4Wenjing Liu1-2/+14
[Description] hbr2 compliance eye output is unstable (toggling on and off) with debugger break. This caueses intermittent PHY automation failure. Need to look into the root cause later Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: removing remaining register definitions work aroundYue Hin Lau3-25/+23
Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: power_down_Hw need signal type to turnoff backlightAndrew Jiang1-1/+4
Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: make tile changing run at ISRShihChen Chen1-3/+18
Signed-off-by: ShihChen Chen <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: Refactor dc_update_planes_and_stream.Bhawanpreet Lakha3-226/+87
Split update_planes_and_stream_state (split Software and Hardware programming) as the state is already build, so we only need to program the hardware Signed-off-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: Fix NULL pointer on MST chained modeJerry Zuo1-0/+7
Prevent NULL pointer on new_stream being added to ctx when added MST connectors cannot be found in existing crtc_state in the chained mode Signed-off-by: Jerry Zuo <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: Exclude MST from fake sinkJerry Zuo1-2/+11
Needs effort to take care of the fake sink scenario in downstream daisy chain device. Exclude MST from fake sink feature for now. Signed-off-by: Jerry Zuo <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: fixing register includesYue Hin Lau2-45/+46
Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: Match actual state during S3 resume.Leo (Sunpeng) Li1-0/+36
During system suspend, we: 1. Cache a duplicate of the current DRM atomic state, which calls hooks to duplicate our internal states. 2. Call hooks to disable all functionalities. 3. System suspended. During resume, we attempt to restore the cached state. However, our interal states are now stale, since step 1 was done before step 2. i.e. our cached state does not reflect the disabled nature of things. This change resolves that by destroying all relevant states to reflect the actual state during resume. Signed-off-by: Leo (Sunpeng) Li <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: update mpc add/remove functionsEric Bernstein3-70/+130
Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: fix multi-display on CZRoman Li1-8/+21
- fixed wrong index in dce110_validate_surface_sets() - formatted for better readability Signed-off-by: Roman Li <[email protected]> Reviewed-by: Harry Wentland <[email protected]> igned-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: Refactor dcn10_dpp_cm_helper to dcn10_cm_commonYue Hin Lau4-5/+5
Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: Don't report fake sink as connectedHarry Wentland1-1/+2
This was missed in the previous fake sink change. The fake sink allows us to enable a pipe with a disconnected display. We shouldn't report it as connected. Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: To prevent detecting new sink from spurious HPDMartin Tsai2-13/+21
Signed-off-by: Martin Tsai <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: Add FBC on/off to front-end programmingRoman Li1-0/+9
- Fixing text mode for cases when VT-switch doesn't result in timing change Signed-off-by: Roman Li <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: fix usb-c dongle regressionEric Yang1-2/+0
A previous change moved link_disconnect_sink after dpcd read, this causes the sink count to be overwritten which in turn causes another detection to be triggered in the short pulse handler, which brings down the display. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: Force always scale chroma, set always_scaled to falseAndrew Jiang2-8/+5
This allows us to not always have scaling on, which causes issues with validation and causes the text to blur slightly. Signed-off-by: Andrew Jiang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-21drm/amd/display: Driver message to SMU to indicate display offHersen Wu4-17/+28
Signed-off-by: Hersen Wu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-20drm/i915/cnl: Map VBT DDC Pin to BSpec DDC Pin.Rodrigo Vivi2-10/+25
Starting on CNL we now need to map VBT DDC Pin to BSPec DDC Pin values. Not a direct translation anymore. According to VBT Block 2 (General Bytes Definition) DDC Bus +----------+-----------+--------------------+ | DDI Type | VBT Value | Bspec Mapped Value | +----------+-----------+--------------------+ | DDI-B | 0x1 | 0x1 | | DDI-C | 0x2 | 0x2 | | DDI-D | 0x3 | 0x4 | | DDI-F | 0x4 | 0x3 | +----------+-----------+--------------------+ v2: Move defines to a better place. This is actually CNL_PCH not CNL only. v3: Accepting Ville's suggestions: enums and array to to make this future proof. v4: Protect the array access as Ville suggested. Also accepting all Jani's suggestions: - use already defined gmbus pin definitions. - use map_ddc_pin for disambiguation. - Add /* sic */ comment on inverted values so people can easily see it it nos a mistake we have the map 3 -> 4 and 4 -> 3 :/ Cc: Jani Nikula <[email protected]> Cc: Paulo Zanoni <[email protected]> Cc: Anusha Srivatsa <[email protected]> Cc: Clinton Taylor <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-10-20drm/i915: Let's use more enum intel_dpll_id pll_id.Rodrigo Vivi1-16/+18
No functional change expected. Just let's use this enum when possible and also same standard pll_id name so we can rework gen9+ port clock later. Cc: Mika Kahola <[email protected]> Cc: Paulo Zanoni <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Mika Kahola <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-10-21drm: Reorganize drm_pending_event to support future event types [v2]Keith Packard5-25/+33
Place drm_event_vblank in a new union that includes that and a bare drm_event structure. This will allow new members of that union to be added in the future without changing code related to the existing vbl event type. Assignments to the crtc_id field are now done when the event is allocated, rather than when delievered. This way, delivery doesn't need to have the crtc ID available. v2: * Remove 'dev' argument from create_vblank_event It wasn't being used anyways, and if we need it in the future, we can always get it from crtc->dev. * Check for MODESETTING before looking for crtc in queue_vblank_event UMS drivers will oops if we try to get a crtc, so make sure we're modesetting before we try to find a crtc_id to fill into the event. Signed-off-by: Keith Packard <[email protected]> Reviewed-by: Sean Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit dc695b85fde88eca3ef3b03fcd82f15b6bc6e462)
2017-10-21drm: Widen vblank count to 64-bits [v3]Keith Packard1-33/+71
This modifies the datatypes used by the vblank code to provide 64 bits of vblank count. The driver interfaces have been left using 32 bits of vblank count; all of the code necessary to widen that value for the user API was already included to handle devices returning fewer than 32-bits. This will provide the necessary datatypes for the Vulkan API. v2: * Re-write wait_vblank ioctl to ABSOLUTE sequence When an application uses the WAIT_VBLANK ioctl with RELATIVE or NEXTONMISS bits set, the target vblank interval is updated within the kernel. We need to write that target back to the ioctl buffer and update the flags bits so that if the wait is interrupted by a signal, when it is re-started, it will target precisely the same vblank count as before. * Leave driver API with 32-bit vblank count v3: * Rebase on top of Arnd Bergmann's patch which had the switch to ktime_t parts. [airlied: fix conflict with Ville vblank change]. Suggested-by: Michel Dänzer <[email protected]> Suggested-by: Daniel Vetter <[email protected]> Signed-off-by: Keith Packard <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 2affbc16983e4fc90960bc7f70e7615f4228199b)
2017-10-20drm/amdgpu:fix wb_clearMonk Liu1-2/+2
Properly shift the index when clearing so we clear the right bit Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-20drm/amdgpu:fix vf_error_putMonk Liu2-11/+17
1,it should not work on non-SR-IOV case 2,the NO_VBIOS error is incorrect, should handle it under detect_sriov_bios. 3,wrap the whole detect_sriov_bios with sriov check Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-20drm/amdgpu/sriov:now must reinit pspMonk Liu1-0/+1
otherwise after VF FLR the KIQ cannot work Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-20drm/amdgpu: merge bios post checking functionspding1-23/+18
Merge the post checking functions to avoid confusion and take virtualization into account in all cases. Signed-off-by: pding <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-10-20drm/tegra: hdmi: Add cec-notifier supportHans Verkuil4-0/+19
In order to support CEC the HDMI driver has to inform the CEC driver whenever the physical address changes. So when the EDID is read the CEC driver has to be informed and whenever the hotplug detect goes away. This is done through the cec-notifier framework. The link between the HDMI driver and the CEC driver is done through the hdmi-phandle property in the tegra-cec node in the device tree. Signed-off-by: Hans Verkuil <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2017-10-20drm/tegra: dc: Perform a complete reset sequenceThierry Reding1-2/+16
In order for the reset to be applied properly, the module clock must be enabled during the assertion. Signed-off-by: Thierry Reding <[email protected]>
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