aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu
AgeCommit message (Collapse)AuthorFilesLines
2017-04-08drm/msm/mdp5: Add structs for hw Layer MixersArchit Taneja5-0/+119
Create a struct to represent MDP5 Layer Mixer instances. This will eventually allow us to detach CRTCs from the Layer Mixers, and generally clean things up a bit. This is very similar to how hwpipes were previously abstracted away from drm planes. Signed-off-by: Archit Taneja <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm/mdp5: describe LM instances in mdp5_cfgArchit Taneja3-0/+84
The number of Layer Mixers and the downstream blocks (DSPPs and PPs) connected to each LM can vary with different MDP5 revisions. These parameters are also static. Keep the per instance LM data in mdp5_cfg. This will avoid the need to have macros which identify PP id or DSPP id the LM is connected to. We don't configure DSPPs at the moment, but keeping the DSPP instance # here might come handy later. Also add a 'caps' field that identifies features supported by a LM instance. Introduce the caps MDP_LM_CAP_DISPLAY and MDP_LM_CAP_WB that identify whether a LM instance can be used for display or writeback. Signed-off-by: Archit Taneja <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm/mdp5: Bring back pipe_lock to mdp5_plane structArchit Taneja3-5/+7
We'd previously moved the pipe_lock spinlock to the hwpipe struct. Bring it back to mdp5_plane. We will need this because an mdp5_plane in the future could comprise of 2 hw pipes. It makes more sense to have a single lock to protect the registers for the hw pipes used by a plane, rather than trying to take individual locks per hwpipe when committing a configuration. Signed-off-by: Archit Taneja <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm/hdmi: redefinitions of macros not requiredVinay Simha BN1-7/+0
4 macros already defined in hdmi.h, which is not required to redefine in hdmi_audio.c Signed-off-by: Vinay Simha BN <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm/mdp5: Update SSPP_MAX valueArchit Taneja1-1/+2
'SSPP_MAX + 1' is the max number of hwpipes that can be present on a MDP5 platform. Recently, 2 new cursor hwpipes were added, which caused overflows in arrays that used SSPP_MAX to represent the number of elements. Update the SSPP_MAX value to incorporate the extra hwpipes. Signed-off-by: Archit Taneja <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm/dsi: Fix bug in dsi_mgr_phy_enableArchit Taneja1-1/+1
A recent commit introduces a bug in dsi_mgr_phy_enable. In the non dual DSI mode, we reset the mdsi (master DSI) PHY. This isn't right since master and slave DSI exist only in dual DSI mode. For the normal mode of operation, we should simply reset the PHY of the DSI device (i.e. msm_dsi) corresponding to the current bridge. Usage of the wrong DSI pointer also resulted in a static checker warning. That too is resolved with this fix. Fixes: b62aa70a98c5 (drm/msm/dsi: Move PHY operations out of host) Reported-by: Dan Carpenter <[email protected]> Signed-off-by: Archit Taneja <[email protected]> Reviewed-by: Rob Clark <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm: Don't allow zero sized buffer objectsJordan Crouse1-0/+6
Zero sized buffer objects tend to make various bits of the GEM infrastructure complain: WARNING: CPU: 1 PID: 2323 at drivers/gpu/drm/drm_mm.c:389 drm_mm_insert_node_generic+0x258/0x2f0 Modules linked in: CPU: 1 PID: 2323 Comm: drm-api-test Tainted: G W 4.9.0-rc4-00906-g693af44 #213 Hardware name: Qualcomm Technologies, Inc. DB820c (DT) task: ffff8000d7353400 task.stack: ffff8000d7720000 PC is at drm_mm_insert_node_generic+0x258/0x2f0 LR is at drm_vma_offset_add+0x4c/0x70 Zero sized buffers serve no appreciable value to the user so disallow them at create time. Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm: Support 64 bit iova in RD_CMDSTREAM_ADDRJordan Crouse1-2/+2
Output the upper 32 bits of a 64 bit iova in the RD_CMDSTREAM_ADDR section while maintaining backwards compatibility for tools that only understand 32 bit iovas. Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm: Pass interrupt status to a5xx_rbbm_err_irq()Jordan Crouse1-5/+13
The interrupt status was being cleared before processing the handlers. a5xx_rbbm_err_irq() was checking the interrupt status again, which would likely turn out bad because the interrupt status would be 0 (or at least different). Pass the original status to the function instead. Also, skip clearing RBBM_AHB_ERROR from the interrupt status. The interrupt will keep firing until the error source is cleared. Skip the clear to avoid a storm until the error is cleared in a5xx_rbbm_err_irq(). Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm: Don't increase priv->num_aspaces until we know that it fitsJordan Crouse1-4/+3
priv->num_aspaces is increased and then checked to see if it still fits in the priv->aspace array. If it doesn't, we warn and exit but priv->num_aspaces remains incremented. Don't incremement the count until we know that it fits in the array. Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm: Fix wrong pointer check in a5xx_destroyJordan Crouse1-2/+2
Instead of checking for a5xx_gpu->gpmu_iova during destroy we accidently check a5xx_gpu->gpmu_bo. Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm: Simplify vblank event deliveryDaniel Vetter2-18/+6
The core takes care of handling the send_event vs. close() issues, we can remove that driver code. Cc: Rob Clark <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm: switch to postcloseDaniel Vetter1-2/+2
I didn't spot anything that would require ordering here (well not anywhere else either), and I'm trying to unify at least modern drivers on one close hook. Cc: Rob Clark <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm: adreno: fix build error without debugfsArnd Bergmann1-0/+2
The newly added a5xx support fails to build when debugfs is diabled: drivers/gpu/drm/msm/adreno/a5xx_gpu.c:849:4: error: 'struct msm_gpu_funcs' has no member named 'show' drivers/gpu/drm/msm/adreno/a5xx_gpu.c:849:11: error: 'a5xx_show' undeclared here (not in a function); did you mean 'a5xx_irq'? This adds a missing #ifdef. Fixes: b5f103ab98c7 ("drm/msm: gpu: Add A5XX target support") Cc: [email protected] Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm: move submit fence wait out of struct_mutexRob Clark1-21/+18
Probably a symptom of needing finer grained locking, but if we wait on the incoming fence-fd (which could come from a different context) while holding struct_mutex, that blocks retire_worker so gpu fences cannot get signalled. This causes a problem if userspace manages to get more than a frame ahead, leaving the atomic-commit worker blocked waiting on fences that cannot be signaled because submit is blocked waiting for a fence signalled from vblank (after the atomic commit which is blocked). If we start having multiple fence ctxs for the gpu, submit_fence_sync() would probably need to move outside of struct_mutex as well. Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm: pm runtime support for iommuRob Clark1-1/+14
In particular, attach() and unmap() need pm-runtime get/put to ensure iommu clks are enabled. Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm: convert to iommu_map_sgRob Clark1-49/+5
Significantly simplifies things. Also iommu_unmap() can unmap an entire iova range. (If backporting to downstream kernel you might need to revert this. Or at least double check older iommu implementation.) Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm/adreno: reset ringbuffer in hw_initRob Clark1-10/+8
We need to do this also in resume path when we need to re-hw_init(). Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm/gpu: use pm-runtimeRob Clark6-93/+71
We need to use pm-runtime properly when IOMMU is using device_link() to control it's own clocks. Signed-off-by: Rob Clark <[email protected]>
2017-04-08drm/msm/gpu: move suspend/resume into debugfs->showRob Clark5-14/+2
Each of the per-generation callbacks was doing this. Lets just simplify and move it into toplevel show() fxn. Signed-off-by: Rob Clark <[email protected]>
2017-04-07Revert "drm: Don't allow interruptions when opening debugfs/crc"Sean Paul1-1/+5
This reverts commit b8dfa821c27046ede9bf8eb14cc8109d379428e9 Author: Chris Wilson <[email protected]> Date: Fri Apr 7 12:17:12 2017 +0100 drm: Don't allow interruptions when opening debugfs/crc It reportedly breaks things, so let's revert now and try again later. Fixes: b8dfa821c270 ("drm: Don't allow interruptions when opening debugfs/crc") Cc: Chris Wilson <[email protected]> Cc: Tomeu Vizoso <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Sean Paul <[email protected]> Cc: David Airlie <[email protected]> Cc: [email protected] Reported-by: Chris Wilson <[email protected]> Acked-by: Chris Wilson <[email protected]> Acked-by: Daniel Vetter <[email protected]> Signed-off-by: Sean Paul <[email protected]>
2017-04-07drm/amdgpu: fix fence memory leak in wait_all_fence V2Chunming Zhou1-0/+1
V2: remove **array method, directly fence_put after fence wait. Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-07drm/amdgpu: fix "fix 64bit division"Christian König1-0/+1
The offset must be 64bit and add back the accidential dropped line. Signed-off-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-07drm/amd/powerplay: add fan controller table v11 support.Rex Zhu2-45/+120
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-07drm/amd/powerplay: port newest process pptable code for vega10.Rex Zhu3-50/+187
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-07drm/amdgpu: set vm size and block size by individual gmc by default (v3)Junwei Zhang8-40/+66
By default, the value is set by individual gmc. if a specific value is input, it overrides the global value for all v2: create helper funcs v3: update gmc9 APU's num_level athough it may be updated in the future. Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-07drm: Only take cursor locks when the cursor plane existsDaniel Vetter1-4/+4
I thought I've fixed this, but maybe not. Anyway, clearly broken, and easy fix. Cc: Tony Lindgren <[email protected]> Reported-by: Tony Lindgren <[email protected]> Fixes: b95ff0319a82 ("drm: Remove drm_modeset_(un)lock_crtc") Cc: Harry Wentland <[email protected]> Cc: Maarten Lankhorst <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Sean Paul <[email protected]> Cc: David Airlie <[email protected]> Cc: [email protected] Signed-off-by: Daniel Vetter <[email protected]> Tested-by: Tony Lindgren <[email protected]> Reviewed-by: Daniel Stone <[email protected]> Signed-off-by: Sean Paul <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-04-07drm/vmwgfx: Fix fbdev emulation using legacy functionsDaniel Vetter1-2/+56
I've broken this by removing the backoff handling from the set_config2atomic helper in commit 38b6441e4e75c0b319cfe4d9364c1059fc1e3c2b Author: Daniel Vetter <[email protected]> Date: Wed Mar 22 22:50:58 2017 +0100 drm/atomic-helper: Remove the backoff hack from set_config Fixing this properly would mean we get to wire the acquire_ctx all the way through vmwgfx fbdev code, and doing the same was tricky for the shared fbdev layer. Probably much better to look into refactoring the entire code to use the helpers, but since that's not a viable long-term solution fix the issue by open-coding a vmwgfx version of set_config, that does the legacy backoff dance internally. Note: Just compile-tested. The idea is to take drm_mode_set_config_internal(), remove the "is this a legacy driver" check, and whack the drm_atomic_legacy_backoff trickery at the end. Since drm_atomic_legacy_backoff is for atomic commits only we need to open-code it. Cc: Thomas Hellstrom <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Thomas Hellstrom <[email protected]> Signed-off-by: Sean Paul <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-04-07drm/rockchip: Shutdown all crtcs when unbinding drmJeffy Chen1-0/+1
Signed-off-by: Jeffy Chen <[email protected]> Signed-off-by: Sean Paul <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-04-07drm/rockchip: Reorder drm bind/unbind sequenceJeffy Chen1-23/+26
Current drm bind/unbind sequence would cause some memory issues. For example we should not cleanup iommu before cleanup mode config. Reorder bind/unbind sequence, follow exynos drm. Signed-off-by: Jeffy Chen <[email protected]> [seanpaul fixed spelling typo in commit subject] Signed-off-by: Sean Paul <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-04-07drm/rockchip: analogix_dp: Disable clock when unbindingJeffy Chen1-1/+2
The clock is enabled when binding cdn dp. Signed-off-by: Jeffy Chen <[email protected]> Signed-off-by: Sean Paul <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-04-07drm/rockchip: vop: Unprepare clocks when unbindingJeffy Chen1-0/+4
The clocks are prepared when binding vop. Signed-off-by: Jeffy Chen <[email protected]> Signed-off-by: Sean Paul <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-04-07drm/rockchip: vop: Enable pm domain before vop_initialJeffy Chen1-8/+21
We're trying to access vop registers here, so need to make sure the pm domain is on. Normally it should be enabled by the bootloader, but there's no guarantee of it. And if we wanna do unbind/bind, it would also cause the device to hang. And this patch also does these: 1/ move vop_initial to the end of vop_bind for eaiser error handling. 2/ correct the err_put_pm_runtime of vop_enable. Signed-off-by: Jeffy Chen <[email protected]> Signed-off-by: Sean Paul <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-04-07drm/rockchip: cdn-dp: Don't unregister audio dev when unbindingJeffy Chen1-3/+3
After snd_soc_unregister_codec, the dai link would remain bound to the invalid codec. That would cause crashes after unbind dp driver. Let's unregister audio codec when removing dp driver to prevent that. Signed-off-by: Jeffy Chen <[email protected]> Signed-off-by: Sean Paul <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-04-07drm/rockchip: cdn-dp: Don't try to release firmware when not loadedJeffy Chen1-1/+3
Signed-off-by: Jeffy Chen <[email protected]> Signed-off-by: Sean Paul <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-04-07drm: bridge: analogix: Destroy connector & encoder when unbindingJeffy Chen1-0/+2
Normally we do this in drm_mode_config_cleanup. But: 1/ analogix dp's connector is allocated in bind, and freed after unbind. So we need to destroy it in unbind to avoid further access. 2/ the drm bridge is attached in bind, and detached in encoder cleanup. So we need to destroy encoder in unbind. Signed-off-by: Jeffy Chen <[email protected]> Reviewed-by: Andrzej Hajda <[email protected]> Signed-off-by: Sean Paul <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-04-07drm: bridge: analogix: Disable clock when unbindingJeffy Chen1-0/+1
The clock is enabled when binding analogix dp. Signed-off-by: Jeffy Chen <[email protected]> Reviewed-by: Andrzej Hajda <[email protected]> Signed-off-by: Sean Paul <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-04-07drm: bridge: analogix: Unregister dp aux when unbindingJeffy Chen1-0/+1
The dp aux is registered when binding analogix dp. Signed-off-by: Jeffy Chen <[email protected]> Reviewed-by: Andrzej Hajda <[email protected]> Signed-off-by: Sean Paul <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-04-07drm: bridge: analogix: Detach panel when unbinding analogix dpJeffy Chen1-0/+2
The panel is attached when binding analogix dp. Signed-off-by: Jeffy Chen <[email protected]> Reviewed-by: Andrzej Hajda <[email protected]> Signed-off-by: Sean Paul <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-04-07drm: Don't allow interruptions when opening debugfs/crcChris Wilson1-5/+1
The code does not like to be interrupted when waiting for the first vblank after opening a debugfs/crc channel, so don't. [66285.716870] WARNING: CPU: 1 PID: 16615 at drivers/gpu/drm/drm_debugfs_crc.c:185 crtc_crc_open+0x1d0/0x1f0 [drm] [66285.716877] Modules linked in: i915 intel_powerclamp crct10dif_pclmul crc32_pclmul crc32c_intel ghash_clmulni_intel cryptd intel_gtt i2c_algo_bit lpc_ich mfd_core drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops prime_numbers drm video button autofs4 sd_mod ahci libahci libata i2c_i801 scsi_mod i2c_designware_platform i2c_designware_core i2c_core [66285.716929] CPU: 1 PID: 16615 Comm: kms_frontbuffer Not tainted 4.11.0-rc5+ #7 [66285.716935] Hardware name: GIGABYTE GB-BXBT-1900/MZBAYAB-00, BIOS F8 03/02/2016 [66285.716941] Call Trace: [66285.716955] dump_stack+0x4d/0x6f [66285.716966] __warn+0xc1/0xe0 [66285.716975] warn_slowpath_null+0x18/0x20 [66285.717004] crtc_crc_open+0x1d0/0x1f0 [drm] [66285.717014] ? wake_atomic_t_function+0x50/0x50 [66285.717024] full_proxy_open+0xf0/0x1b0 [66285.717032] ? full_proxy_release+0x80/0x80 [66285.717042] do_dentry_open.isra.17+0x14b/0x2d0 [66285.717051] vfs_open+0x42/0x60 [66285.717064] path_openat+0x5e7/0x13d0 [66285.717074] ? refcount_dec_and_test+0x11/0x20 [66285.717081] ? down_read+0xd/0x30 [66285.717087] do_filp_open+0x85/0xf0 [66285.717093] ? __vfs_write+0x23/0x120 [66285.717100] ? __alloc_fd+0x3a/0x170 [66285.717107] do_sys_open+0x11e/0x1f0 [66285.717113] ? do_sys_open+0x11e/0x1f0 [66285.717119] SyS_openat+0xf/0x20 [66285.717125] entry_SYSCALL_64_fastpath+0x17/0x98 [66285.717131] RIP: 0033:0x7f5f2235146a [66285.717135] RSP: 002b:00007ffd892e6bc0 EFLAGS: 00000246 ORIG_RAX: 0000000000000101 [66285.717142] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f5f2235146a [66285.717147] RDX: 0000000000000000 RSI: 00007ffd892e6c40 RDI: 0000000000000006 [66285.717151] RBP: 00007ffd892e6b20 R08: 0000000000000000 R09: 000000000000000f [66285.717156] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000001 [66285.717161] R13: 00007ffd892e6b10 R14: 0000000000000004 R15: 00000000007e61f4 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100610 Fixes: e8fa5671183c ("drm: crc: Wait for a frame before returning from open()") Signed-off-by: Chris Wilson <[email protected]> Cc: Tomeu Vizoso <[email protected]> Cc: Daniel Vetter <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-04-07drm/amdgpu: Avoid overflows/divide-by-zero in latency_watermark calculations.Mario Kleiner4-64/+12
At dot clocks > approx. 250 Mhz, some of these calcs will overflow and cause miscalculation of latency watermarks, and for some overflows also divide-by-zero driver crash ("divide error: 0000 [#1] PREEMPT SMP" in "dce_v10_0_latency_watermark+0x12d/0x190"). This zero-divide happened, e.g., on AMD Tonga Pro under DCE-10, on a Displayport panel when trying to set a video mode of 2560x1440 at 165 Hz vrefresh with a dot clock of 635.540 Mhz. Refine calculations to avoid the overflows. Tested for DCE-10 with R9 380 Tonga + ASUS ROG PG279 panel. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mario Kleiner <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2017-04-07drm/amdgpu: Make display watermark calculations more accurateMario Kleiner4-20/+20
Avoid big roundoff errors in scanline/hactive durations for high pixel clocks, especially for >= 500 Mhz, and thereby program more accurate display fifo watermarks. Implemented here for DCE 6,8,10,11. Successfully tested on DCE 10 with AMD R9 380 Tonga. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mario Kleiner <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2017-04-07drm/radeon: fix typo in bandwidth calculationAlex Deucher1-1/+1
The RV3xx settings were getting applied to all older asics rather than just RV3xx. Reported-by: David Binderman <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-07drm/radeon: Refuse to migrate a prime BO to VRAM. (v2)Christopher James Halse Rogers3-0/+19
BOs shared via dma-buf, either imported or exported, cannot sensibly be migrated to VRAM without breaking the dma-buf sharing. Refuse userspace requests to migrate to VRAM, ensure such BOs are not migrated during command submission, and refuse to pin them to VRAM. v2: Don't pin BOs in GTT. Instead, refuse to migrate BOs to VRAM. Reviewed-by: Christian König <[email protected]> Signed-off-by: Christopher James Halse Rogers <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-07drm/radeon: Maintain prime import/export refcount for BOsChristopher James Halse Rogers2-0/+7
Reviewed-by: Christian König <[email protected]> Signed-off-by: Christopher James Halse Rogers <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-07drm/amdgpu: Refuse to pin or change acceptable domains of prime BOs to VRAM. ↵Christopher James Halse Rogers2-0/+9
(v2) Migration to VRAM will break the sharing, resulting in rendering on the exporting GPU never becoming visible on the importing GPU. v2: Don't pin BOs to GTT. Instead, refuse to migrate them out of GTT. Reviewed-by: Christian König <[email protected]> Signed-off-by: Christopher James Halse Rogers <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-07drm/amdgpu: Fail fb creation from imported dma-bufs. (v2)Christopher James Halse Rogers1-0/+6
Any use of the framebuffer will migrate it to VRAM, which is not sensible for an imported dma-buf. v2: Use DRM_DEBUG_KMS to prevent userspace accidentally spamming dmesg. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Christopher James Halse Rogers <[email protected]> CC: [email protected] Signed-off-by: Alex Deucher <[email protected]>
2017-04-07drm/radeon: Fail fb creation from imported dma-bufs.Christopher James Halse Rogers1-0/+6
Any use of the framebuffer will migrate it to VRAM, which is not sensible for an imported dma-buf. v2: Use DRM_DEBUG_KMS to prevent userspace accidentally spamming dmesg. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Christopher James Halse Rogers <[email protected]> CC: [email protected] Signed-off-by: Alex Deucher <[email protected]>
2017-04-08drm/mediatek: add support for Mediatek SoC MT2701[email protected]7-0/+74
This patch add support for the Mediatek MT2701 DISP subsystem. There is only one OVL engine in MT2701. Signed-off-by: YT Shen <[email protected]> Acked-by: CK Hu <[email protected]>
2017-04-08drm/mediatek: update DSI sub driver flow for sending commands to panel[email protected]1-101/+158
This patch update enable/disable flow of DSI module. Original flow works on there is a bridge chip: DSI -> bridge -> panel. In this case: DSI -> panel, the DSI sub driver flow should be updated. We need to initialize DSI first so that we can send commands to panel. Signed-off-by: shaoming chen <[email protected]> Signed-off-by: YT Shen <[email protected]> Acked-by: CK Hu <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.