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2021-04-15drm/amd/pm: fix error code in smu_set_power_limit()Dan Carpenter1-0/+1
We should return -EINVAL instead of success if the "limit" is too high. Fixes: e098bc9612c2 ("drm/amd/pm: optimize the power related source code layout") Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu: fix an error code in init_pmu_entry_by_type_and_add()Dan Carpenter1-1/+3
If the kmemdup() fails then this should return a negative error code but it currently returns success Fixes: b4a7db71ea06 ("drm/amdgpu: add per device user friendly xgmi events for vega20") Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/radeon/cik: remove set but not used variablesTian Tao1-4/+0
The value of pipe_id and queue_id are not used under certain circumstances, so just delete. Signed-off-by: Tian Tao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15amd/display: allow non-linear multi-planar formatsSimon Ser1-7/+4
Accept non-linear buffers which use a multi-planar format, as long as they don't use DCC. Tested on GFX9 with NV12. Signed-off-by: Simon Ser <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Nicholas Kazlauskas <[email protected]> Cc: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu/dm: Fix NULL pointer crash during DP MST hotplugShashank Sharma1-0/+5
This patch checks the return value of the function dc_link_add_remote_sink before using it. This was causing a crash during consecutive hotplugs of DP MST displays. Cc: Harry Wentland <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Shashank Sharma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15Revert "Revert "drm/amdgpu: Ensure that the modifier requested is supported ↵Qingqing Zhuo2-3/+28
by plane."" This reverts commit 55fa622fe635bfc3f2587d784f6facc30f8fdf12. The regression caused by the original patch has been cleared, thus introduce back the change. Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: Update modifier list for gfx10_3Qingqing Zhuo1-2/+2
[Why] Current list supports modifiers that have DCC_MAX_COMPRESSED_BLOCK set to AMD_FMT_MOD_DCC_BLOCK_128B, while AMD_FMT_MOD_DCC_BLOCK_64B is used instead by userspace. [How] Replace AMD_FMT_MOD_DCC_BLOCK_128B with AMD_FMT_MOD_DCC_BLOCK_64B for modifiers with DCC supported. Fixes: faa37f54ce0462 ("drm/amd/display: Expose modifiers") Signed-off-by: Qingqing Zhuo <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/pm: revise two names of sensor values for vangoghXiaojian Du1-6/+6
This patch is to revise two names of sensor values for vangogh. New smu metrics table is supported by new pmfw (from version 4.63.36.00 ), it includes two parts, one part is the current smu metrics table data and the other part is the average smu metrics table data. The hwmon will read the current gfxclk and mclk from the current smu metrics table data. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/pm: remove the "set" function of pp_dpm_mclk for vangoghXiaojian Du1-6/+0
This patch is to remove the "set" function of pp_dpm_mclk for vangogh. For vangogh, mclk bonds with fclk, they will lock each other on the same perfomance level. But according to the smu message from pmfw, only fclk is allowed to set value manually, so remove the unnecessary code of "set" function for mclk. Signed-off-by: Xiaojian Du <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu: Copy MEC FW version to MEC2 if we skipped loading MEC2Joseph Greathouse1-0/+3
If we skipped loading MEC2 firmware separately from MEC, then MEC2 will be running the same firmware image. Copy the MEC version and feature numbers into MEC2 version and feature numbers. This is needed for things like GWS support, where we rely on knowing what version of firmware is running on MEC2. Leaving these MEC2 entries blank breaks our ability to version-check enables and workarounds. Signed-off-by: Joseph Greathouse <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/pm: add the callback to get the bootup values for renoirXiaojian Du3-0/+126
This patch is to add the callback to get the bootup values for renoir. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd: update the atomfirmware header for smu12Xiaojian Du1-0/+41
This patch is to update the atomfirmware header for smu12. v2: remove some unnecessary members Signed-off-by: Xiaojian Du <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdkfd: Remove legacy code not acquiring VMsFelix Kuehling3-71/+10
ROCm user mode has acquired VMs from DRM file descriptors for as long as it supported the upstream KFD. Legacy code to support older versions of ROCm is not needed any more. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Philip Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu: Use iterator methods exposed by amdgpu_res_cursor.h in building ↵Ramesh Errabolu3-12/+27
SG_TABLE's for a VRAM BO Extend current implementation of SG_TABLE construction method to allow exportation of sub-buffers of a VRAM BO. This capability will enable logical partitioning of a VRAM BO into multiple non-overlapping sub-buffers. One example of this use case is to partition a VRAM BO into two sub-buffers, one for SRC and another for DST. Reviewed-by: Christian König <[email protected]> Signed-off-by: Ramesh Errabolu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu: Add double-sscanf but invertLuben Tuikov1-2/+5
Add back the double-sscanf so that both decimal and hexadecimal values could be read in, but this time invert the scan so that hexadecimal format with a leading 0x is tried first, and if that fails, then try decimal format. Also use a logical-AND instead of nesting double if-conditional. See commit "drm/amdgpu: Fix a bug for input with double sscanf" Cc: Alexander Deucher <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/amdgpu: add ASPM support on polarisKenneth Feng1-2/+191
add ASPM support on polaris Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/amdgpu: enable ASPM on vegaKenneth Feng3-3/+257
enable ASPM on vega to save the power without the performance hurt. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/amdgpu: enable ASPM on navi1xKenneth Feng1-8/+2
enable ASPM on navi1x for the benifit of system power consumption without performance hurt. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/sriov no need to config GECC for sriovJack Zhang1-1/+1
No need to config GECC feature here for sriov Leave the host drvier to do the configuration job. Signed-off-by: Jack Zhang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/pm: Show updated clocks on aldebaranLijo Lazar1-11/+41
When GFXCLK range is updated in manual/determinism mode, show the updated min/max clock range. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu: Fix kernel-doc for the RAS sysfs interfaceLuben Tuikov1-23/+24
Imporve the kernel-doc for the RAS sysfs interface. Fix the grammar, fix the context. Cc: Alexander Deucher <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu: Add bad_page_cnt_threshold to debugfsLuben Tuikov1-0/+2
Add bad_page_cnt_threshold to debugfs, an optional file system used for debugging, for reporting purposes only--it usually matches the size of EEPROM but may be different depending on the "bad_page_threshold" kernel module option. The "bad_page_cnt_threshold" is a dynamically computed value. It depends on three things: the VRAM size; the size of the EEPROM (or the size allocated to the RAS table therein); and the "bad_page_threshold" module parameter. It is a dynamically computed value, when the amdgpu module is run, on which further parameters and logic depend, and as such it is helpful to see the dynamically computed value in debugfs. Cc: Alexander Deucher <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu: Fix a bug in checking the result of reserve pageLuben Tuikov1-6/+3
Fix if (ret) --> if (!ret), a bug, for "retire_page", which caused the kernel to recall the method with *pos == end of file, and that bounced back with error. On the first run, we advanced *pos, but returned 0 back to fs layer, also a bug. Fix the logic of the check of the result of amdgpu_reserve_page_direct()--it is 0 on success, and non-zero on error, not the other way around. This patch fixes this bug. Cc: Alexander Deucher <[email protected]> Cc: John Clements <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu: Fix a bug for input with double sscanfLuben Tuikov1-8/+5
Remove double-sscanf to scan for %llu and 0x%llx, as that is not going to work! The %llu will consume the "0" in "0x" of your input, and the hex value you think you're entering will always be 0. That is, a valid hex value can never be consumed. On the other hand, just entering a hex number without leading 0x will either be scanned as a string and not match, for instance FAB123, or the leading decimal portion is scanned as the %llu, for instance 123FAB will be scanned as 123, which is not correct. Thus remove the first %llu scan and leave only the %llx scan, removing the leading 0x since %llx can scan either. Addresses are usually always hex values, so this suffices. Cc: Alexander Deucher <[email protected]> Cc: Xinhui Pan <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu: Add graphics cache rinse packet for sdmaJinzhou Su1-0/+28
Add emit mem sync callback for sdma_v5_2 In amdgpu sync object test, three threads created jobs to send GFX IB and SDMA IB in sequence. After the first GFX thread joined, sometimes the third thread will reuse the same physical page to store the SDMA IB. There will be a risk that SDMA will read GFX IB in the previous physical page. So it's better to flush the cache before commit sdma IB. Signed-off-by: Jinzhou Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu: Ensure dcefclk isn't created on AldebaranKent Russell1-1/+3
Like Arcturus, this isn't available on Aldebaran, so remove it accordingly Signed-off-by: Kent Russell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: [FW Promotion] Release 0.0.61Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: 3.2.131Aric Cyr1-1/+1
DC version 3.2.131 brings improvements in multiple areas. In summary, we highlight: -Enhancement for multiple eDP BL control. -Add debug flag to enable eDP ILR by default and debugfs to repress HPD/HPR_RX IRQ. -Fixes for DSC enable sequence,Force vsync flip,hang when psr is enabled etc. -Firmware releases: 0.0.60 0.0.61 Signed-off-by: Aric Cyr <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: Fix hangs with psr enabled on dcn3.xxRoman Li1-4/+1
[Why] SKIP_CRTC_DISABLE bit should be applicable to all dcn asics not only Raven. [How] Replace check for Raven only with check for all DCNs. Signed-off-by: Roman Li <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: Added support for multiple eDP BL controlJake Wang2-0/+29
[WHY & HOW] Driver currently assumes only 1 eDP is connected. Added support for multiple eDP BL control. Signed-off-by: Jake Wang <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/pm: add support for new smu metrics table for vangoghXiaojian Du1-26/+338
This patch is to add support for new smu metrics table for vangogh. It will support new and legacy smu metrics table in the meanwhile. New pmfw version is 4.63.36.00, and new smu interface version is #3. v1: check smu pmfw version to determine to use new or legacy smu metrics table v2: check smu interface version to determine to use new or legacy smu metrics table v3: revise wrong symbol Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/pm: update the driver interface header for vangoghXiaojian Du2-2/+40
This patch is to update the driver interface header for vangogh. New version driver interface header will support new version pmfw (from version 4.63.36.00) which uses new smu metrics table. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: [FW Promotion] Release 0.0.60Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: wait vblank when stream enabled and update dpp clockLewis Huang3-1/+23
[Why] When boot into OS, seamless boot device won't blank stream. Driver update dpp clock when scanline position in vactive will show garbage on screen. [How] Wait for vblank for seamless boot edp display when driver update dpp clock. The apply seamless boot flag will be clear when OS call SetVisibility on. Therefore we only wait for vblank once after boot into OS. Signed-off-by: Lewis Huang <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: Add debugfs to repress HPD and HPR_RX IRQsHarry Wentland3-2/+45
[Why] For debugging reasons it can be beneficial to disable any hotplug and DP shortpulse interrupt handling. [How] Expose a debugfs to set a flag to bypass HPD IRQ handling and skip IRQ handling if flag is set. Signed-off-by: Harry Wentland <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: Connect clock optimization function to dcn301Mikita Lipski1-0/+2
[why/how] Connecting clock optimization functions to dcn301 HWSS to enable power state enter/exit optimization Signed-off-by: Mikita Lipski <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: Remove unused flag from stream stateMikita Lipski1-1/+0
[why & how] Removing unused DSC flag which is incorrect and is not used. We are only using stream->timing.flags.DSC for DSC's current state. Stream state as an input parameter and should not contain any past status flags. Signed-off-by: Mikita Lipski <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: Force vsync flip when reconfiguring MPCCAnthony Wang1-0/+4
[Why] Underflow observed when disabling PIP overlay in-game when vsync is disabled, due to OTC master lock not working with game pipe which is immediate flip. [How] When performing a full update, override flip_immediate value to false for all planes, so that flip occurs on vsync. Signed-off-by: Anthony Wang <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: Set LTTPR mode to non-LTTPR if no repeaters foundWesley Chalmers1-0/+2
[WHY] If no repeaters are found, we do not need or want to attempt to link-train repeaters, as this could cause bugs. Signed-off-by: Wesley Chalmers <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: Fix DML validation of simple vs native 422 modesNicholas Kazlauskas1-3/+4
[Why] We're always validating DML with simple 422 DSC even if native 422 DSC is in use. [How] Use the mode configuration from the timing. Signed-off-by: Nicholas Kazlauskas <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: Remove static property from decide_edp_link_settingsMichael Strauss2-1/+5
[Why & How] Static cleanup for eDP ILR Support. Signed-off-by: Michael Strauss <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: Fix DSC enable sequenceMike Hsieh5-5/+17
[Why] DSC is enabled before reset link and potentially cause DSC enable fail problem. [How] Enable DSC after link is reseted Signed-off-by: Mike Hsieh <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: Disable boot optimizations if ILR optimzation is requiredMichael Strauss4-2/+54
[Why] VBIOS currently sets the max link rate found in eDP 1.4 SUPPORTED_LINK_RATES table If eDP fastboot optimizations are enabled, the link rate remains at max after init [How] Determine optimal link rate during boot, disable seamless boot and eDP fastboot optimizations if link rate optimization is required Signed-off-by: Michael Strauss <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd/display: Add debug flag to enable eDP ILR by defaultMichael Strauss2-2/+2
[Why & How] Allow per-asic enablement of ILR feature with debug flag Signed-off-by: Michael Strauss <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdkfd: change MTYPEs for Aldebaran's HW requirementEric Huang1-8/+5
Due to changes of HW memory model, we need to change Aldebaran MTYPEs to meet HW changes. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu: Introduce new SETUP_TMR interfaceOak Zeng2-4/+19
This new interface passes both virtual and physical address to PSP. It is backward compatible with old interface. v2: use a function to simplify tmr physical address calc (Lijo) Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu: Calling address translation functions to simplify codesOak Zeng12-25/+12
Use amdgpu_gmc_vram_pa and amdgpu_gmc_vram_cpu_pa to simplify codes. No logic change. Signed-off-by: Oak Zeng <[email protected]> Signed-off-by: Harish Kasiviswanathan <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu: Introduce functions for vram physical addr calculationOak Zeng2-0/+39
Add one function to calculate BO's GPU physical address. And another function to calculate BO's CPU physical address. v2: Use functions vs macros (Christian) Use more proper function names (Christian) Signed-off-by: Oak Zeng <[email protected]> Suggested-by: Lijo Lazar <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu: update gfx 9.4.2 ras error reportingJohn Clements1-6/+7
only output ras error status if an error bit is set or error counter is set Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amdgpu: update mmhub 1.7 ras error reportingJohn Clements1-1/+1
only output ras error status if an error bit is set Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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