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2024-06-19drm/i915/psr: Disable PSR/Panel Replay on sink side for PSR onlyJouni Högander1-6/+6
Enabling/disabling Panel Replay on sink side has to be done before link training. We can't disable it in sink side on PSR disable. Fixes: 88ae6c65ecdb ("drm/i915/psr: Unify panel replay enable/disable sink") Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-19drm/i915/psr: Disable PSR2 SU Region ET if enable_psr module parameter is setJouni Högander1-1/+12
Currently PSR2 SU Region Early Transport is enabled by default on Lunarlake if panel supports it despite enable_psr module parameter value. This patch makes it possible for user to limit used PSR mode and prevent SU Region Early Transport by setting enable_psr as 2. With default (-1) PSR2 SU Region Early Transport is allowed. v2: fix/improve commit desciption Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-19drm/i915/psr: Disable Panel Replay if PSR mode is set via module parameterJouni Högander2-4/+26
If user is specifically limiting PSR mode to PSR1 or PSR2: disable Panel Replay. With default value -1 all modes are allowed including Panel Replay. Disabling PSR using value 0 disables Panel Replay as well. Also own compute config helper is added for Panel Replay. This makes sense because number of Panel Replay specific checks are increasing. v2: Squash adding Panel Replay compute config helper Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-19drm/i915/alpm: Fix port clock usage in AUX Less wake time calculationJouni Högander1-1/+2
Port clock is link rate in 10 kbit/s units. Take this into account when calculating AUX Less wake time. Fixes: da6a9836ac09 ("drm/i915/psr: Calculate aux less wake time") Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-19drm/i915/display: Wa 16021440873 is writing wrong registerJouni Högander2-11/+5
Wa 16021440873 is writing wrong register. Instead of PIPE_SRCSZ_ERLY_TPT write CURPOS_ERLY_TPT. v2: use right offset as well Fixes: 29cdef8539c3 ("drm/i915/display: Implement Wa_16021440873") Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Mika Kahola <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-19drm/i915/psr: Set SU area width as pipe src widthJouni Högander1-1/+1
Currently SU area width is set as MAX_INT. This is causing problems. Instead set it as pipe src width. Fixes: 86b26b6aeac7 ("drm/i915/psr: Carry su area in crtc_state") Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Mika Kahola <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-18drm/panic: depends on !VT_CONSOLEJocelyn Falempe1-1/+1
The race condition between fbcon and drm_panic can only occurs if VT_CONSOLE is set. So update drm_panic dependency accordingly. This will make it easier for Linux distributions to enable drm_panic by disabling VT_CONSOLE, and keeping fbcon terminal. The only drawback is that fbcon won't display the boot kmsg, so it should rely on userspace to do that. At least plymouth already handle this case with https://gitlab.freedesktop.org/plymouth/plymouth/-/merge_requests/224 Suggested-by: Daniel Vetter <[email protected]> Signed-off-by: Jocelyn Falempe <[email protected]> Reviewed-by: Javier Martinez Canillas <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-18drm: Add DRM_MODE_TV_MODE_MONOCHROMENick Hollinghurst3-3/+14
Add this as a value for enum_drm_connector_tv_mode, represented by the string "Mono", to generate video with no colour encoding or bursts. Define it to have no pedestal (since only NTSC-M calls for a pedestal). Change default mode creation to acommodate the new tv_mode value which comprises both 525-line and 625-line formats. Acked-by: Daniel Vetter <[email protected]> Signed-off-by: Nick Hollinghurst <[email protected]> Signed-off-by: Dave Stevenson <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-18drm/tidss: Add drm_panic supportJavier Martinez Canillas1-1/+13
Add support for the drm_panic infrastructure, which allows to display a user friendly message on the screen when a Linux kernel panic occurs. Signed-off-by: Javier Martinez Canillas <[email protected]> Reviewed-by: Jocelyn Falempe <[email protected]> Reviewed-by: Aradhya Bhatia <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-17drm/i915/display: Update calculation to avoid overflowMitul Golani1-4/+5
Update calculation to avoid overflow. -v2: Remove extra line between cc and signed-off. Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal") Cc: Mitul Golani <[email protected]> Cc: Ankit Nautiyal <[email protected]> Cc: Suraj Kandpal <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Stephen Rothwell <[email protected]> Signed-off-by: Mitul Golani <[email protected]> Reviewed-by: Ankit Nautiyal <[email protected]> Acked-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2024-06-17drm/nouveau: Constify struct nouveau_job_opsChristophe JAILLET3-4/+4
"struct nouveau_job_ops" is not modified in these drivers. Constifying this structure moves some data to a read-only section, so increase overall security. In order to do it, "struct nouveau_job" and "struct nouveau_job_args" also need to be adjusted to this new const qualifier. On a x86_64, with allmodconfig: Before: ====== text data bss dec hex filename 5570 152 0 5722 165a drivers/gpu/drm/nouveau/nouveau_exec.o After: ===== text data bss dec hex filename 5630 112 0 5742 166e drivers/gpu/drm/nouveau/nouveau_exec.o Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Danilo Krummrich <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/860e9753d7867aa46b003bb3d0497f1b04065b24.1718381285.git.christophe.jaillet@wanadoo.fr
2024-06-17nouveau: rip out busy fence waitsDave Airlie6-34/+6
I'm pretty sure this optimisation is actually not a great idea, and is racy with other things waiting for fences. Just nuke it, there should be no need to do fence waits in a busy CPU loop. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Signed-off-by: Danilo Krummrich <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-17drm/ci: add tests on vkmsVignesh Raman9-6/+274
Add job that runs igt on top of vkms. Acked-by: Maíra Canal <[email protected]> Acked-by: Helen Koike <[email protected]> Signed-off-by: Vignesh Raman <[email protected]> Acked-by: Jessica Zhang <[email protected]> Tested-by: Jessica Zhang <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Helen Koike <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-17drm/i915/display: update handling of FBC when VT-d active workaroundVinod Govindapillai1-16/+6
Move the handling of the disabling FBC when VT-d is active wa as part of the intel_fbc_check_plane(). As the hw is still there, intel_fbc_sanitize should be able to handle the state properly. v2: update the patch description (Jani Nikula) v3: fix the return value in wa handling (Jani Nikula) Bspec: 21664 Suggested-by: Ville Syrjälä <[email protected]> Signed-off-by: Vinod Govindapillai <[email protected]> Reviewed-by: Jouni Högander <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-17drm/i915: move comments about FSB straps to proper placeJani Nikula2-10/+9
Move the comment about FSB straps to where the relevant register is read. Suggested-by: Ville Syrjälä <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/8a5b6cd3db80259c30263861f1a9ff04fea2e7f0.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915/cdclk: use i9xx_fsb_freq() for rawclk_freq initializationJani Nikula1-43/+3
Instead of duplicating the CLKCFG parsing, reuse i9xx_fsb_freq() to figure out rawclk_freq where applicable. Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/21511f155f1f446e066117bc6ed3165618d7afd6.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915: use i9xx_fsb_freq() for GT clock frequencyJani Nikula3-2/+4
Reuse i9xx_fsb_freq() for GT clock frequency initialization instead of depending on rawclk_freq. Note: If the init order was changed, we could use i915->fsb_freq directly. However, GT clock initialization is done in i915_driver_mmio_probe(), but intel_dram_detect() later in i915_driver_hw_probe(), with a dependency on intel_pcode_init(). Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/0678d8ec9772725b47d4fa5b14e3b3a34256d5cf.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915: extend the fsb_freq initialization to more platformsJani Nikula1-14/+41
Initialize fsb frequency for more platforms to be able to use it for GT clock and rawclk frequency initialization. Note: There's a discrepancy between existing pnv_fsb_freq() and i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is mobile. Default to 1333 MHz for unknown values, similar to i9xx_hrawclk(). v2: - Add MISSING_CASE() (Ville) - Default to the same frequency for both branches (Ville) Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/7cd6dbd4dafb900ac1dd12be0ec096ff1d5fc6cf.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915: convert fsb_freq and mem_freq to kHzJani Nikula3-33/+34
We'll want to use fsb frequency for deriving GT clock and rawclk frequencies in the future. Increase the accuracy by converting to kHz. Do the same for mem freq to be aligned. Round the frequencies ending in 666 to 667. v2: Also handle mem_freq in gen5_rps_init() (Ville) Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/17fe2544b876549f63fac0f956273f5f282081b3.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915/gt: remove mem freq from gt debugfsJani Nikula1-1/+0
It's a bit out of place, and only printed for VLV/CHV. Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/bbfec4c67a81d1d3de1f40484a80b7164e69df21.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915/dram: rearrange mem freq initJani Nikula1-34/+25
Follow the same style in mem freq init as in fsb freq init, returning the value instead of assigning in multiple places. Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/f098ccdbb0c42016d5dad81e0b089bb4babe29f0.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915/dram: split out pnv DDR3 detectionJani Nikula1-4/+8
Split out the PNV DDR3 detection to a distinct step instead of conflating it with mem freq detection. Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/c4bf9d32479ab5024e9daa37a996508f543f05e9.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915/dram: separate fsb freq detection from mem freqJani Nikula1-46/+60
To simplify further changes, add separate functions for reading the fsb frequency. This ends up reading CLKCFG register twice, but it's not a big deal. Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/7582651aa21ac2c1472111c4e81ba8fee182f80e.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915/wm: clarify logging on not finding CxSR latency configJani Nikula1-12/+5
Clarify and unify the logging on not finding PNV CxSR latency config. Just let the i915->fsb_freq == 0 || i915->mem_freq == 0 case go through the table instead of checking for it separately. v2: Do not check for fsb == 0 || mem == 0 separately (Matt) Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/6333cb0675c531e971e829105f1ecfc4d71bdc6b.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915/wm: rename intel_get_cxsr_latency -> pnv_get_cxsr_latencyJani Nikula1-3/+3
Clarify that the function is specific to PNV, making subsequent changes slightly easier to grasp. Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/7d4e3c9a4220ff84af2741e5cd7bb62d1b4f2a44.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm/i915/mso: using joiner is not possible with eDP MSOJani Nikula1-0/+4
It's not possible to use the joiner at the same time with eDP MSO. When a panel needs MSO, it's not optional, so MSO trumps joiner. v3: Only change intel_dp_has_joiner(), leave debugfs alone (Ville) Fixes: bc71194e8897 ("drm/i915/edp: enable eDP MSO during link training") Cc: <[email protected]> # v5.13+ Cc: Ville Syrjala <[email protected]> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1668 Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Jani Nikula <[email protected]>
2024-06-17drm: zynqmp_dp: Don't delay workSean Anderson1-7/+6
We always call scheduled_delayed_work with no delay, so just use a non-delayed work_struct instead. Signed-off-by: Sean Anderson <[email protected]> Reviewed-by: Tomi Valkeinen <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-17drm: zynqmp_dp: Rearrange zynqmp_dp for better paddingSean Anderson1-13/+13
Sort the members of struct zynqmp_dp to reduce padding necessary for alignment. Signed-off-by: Sean Anderson <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-17drm: zynqmp_kms: Fix AUX bus not getting unregisteredSean Anderson1-3/+9
drm_encoder_cleanup is responsible for calling drm_bridge_detach for each bridge attached to the encoder. zynqmp_dp_bridge_detach is in turn responsible for unregistering the AUX bus. However, we never ended up calling drm_encoder_cleanup in the remove or error paths, so the AUX bus would stick around after the rest of the driver had been removed. I don't really understand why drm_mode_config_cleanup doesn't call drm_encoder_cleanup for us. It will call destroy (which for simple_encoder is drm_encoder_cleanup) on encoders in the mode_config's encoder_list. Should drm_encoder_cleanup get called before or after drm_atomic_helper_shutdown? Fixes: 2dfd045c8435 ("drm: xlnx: zynqmp_dpsub: Register AUX bus at bridge attach time") Signed-off-by: Sean Anderson <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-17drm: xlnx: zynqmp_dpsub: Enable plane in atomic updateAnatoliy Klymenko1-3/+7
Unconditionally enable the DPSUB layer in the corresponding atomic plane update callback. Setting the new display mode may require disabling and re-enabling the CRTC. This effectively resets DPSUB to the default state with all layers disabled. The original implementation of the plane atomic update enables the corresponding DPSUB layer only if the framebuffer format has changed. This would leave the layer disabled after switching to a different display mode with the same framebuffer format. Signed-off-by: Anatoliy Klymenko <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-17drm: zynqmp_dpsub: Fix an error handling path in zynqmp_dpsub_probe()Christophe JAILLET1-0/+1
If zynqmp_dpsub_drm_init() fails, we must undo the previous drm_bridge_add() call. Fixes: be3f3042391d ("drm: zynqmp_dpsub: Always register bridge") Signed-off-by: Christophe JAILLET <[email protected]> Reviewed-by: Sean Anderson <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/974d1b062d7c61ee6db00d16fa7c69aa1218ee02.1716198025.git.christophe.jaillet@wanadoo.fr
2024-06-14drm/amd/display: Skip wbscl_set_scaler_filter if filter is nullAlex Hung1-0/+3
Callers can pass null in filter (i.e. from returned from the function wbscl_get_filter_coeffs_16p) and a null check is added to ensure that is not the case. This fixes 4 NULL_RETURNS issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Check BIOS images before it is usedAlex Hung1-0/+14
BIOS images may fail to load and null checks are added before they are used. This fixes 6 NULL_RETURNS issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Add null checker before passing variablesAlex Hung1-3/+6
Checks null pointer before passing variables to functions. This fixes 3 NULL_RETURNS issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Explicitly extend unsigned 16 bit to 64 bitAlex Hung1-2/+2
Coverity reports sign extention defects as below: Suspicious implicit sign extension: mode->htotal with type u16 ... to int (32 bits, signed), then sign-extended to type unsigned long (64 bits, unsigned). If mode->htotal * mode->vtotal is greater than 0x7FFFFFFF, the upper bits of the result will all be 1. Cast it to unsigned long to avoid possible overflow. This fixes 4 SIGN_EXTENSION issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Send message to notify the DPIA host router bandwidthSung Joon Kim5-1/+81
[why] Tell the system about the current host router bandwidth to be used to measure and calculate the right voltage to be used. [how] Send SMU message of each DPIA host router bandwidth. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Add null check to dml21_find_dc_pipes_for_planeDillon Varone1-3/+8
When a phantom stream is in the process of being deconstructed, there could be pipes with no associated planes. In that case, ignore the phantom stream entirely when searching for associated pipes. Cc: [email protected] Reviewed-by: Alvin Lee <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Attempt to avoid empty TUs when endpoint is DPIAMichael Strauss3-1/+75
[WHY] Empty SST TUs are illegal to transmit over a USB4 DP tunnel. Current policy is to configure stream encoder to pack 2 pixels per pclk even when ODM combine is not in use, allowing seamless dynamic ODM reconfiguration. However, in extreme edge cases where average pixel count per TU is less than 2, this can lead to unexpected empty TU generation during compliance testing. For example, VIC 1 with a 1xHBR3 link configuration will average 1.98 pix/TU. [HOW] Calculate average pixel count per TU, and block 2 pixels per clock if endpoint is a DPIA tunnel and pixel clock is low enough that we will never require 2:1 ODM combine. Cc: [email protected] # 6.6+ Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Refactor DCN3X into component folderMounika Adhuri44-61/+304
[why] Move DCN3X files to unique component folder. [how] Create respective component folder in dc, move the DCN3X files into corresponding new folders and made appropriate changes for compilation in Makefiles. Reviewed-by: Martin Leung <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Mounika Adhuri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: On clock init, maintain DISPCLK freqChris Park2-1/+27
[Why] On init if a display is connected, we need to maintain the DISPCLK frequency Even though DPG_EN=1, the display still requires the correct timing or it could cause audio corruption (if DISPCLK freq is reduced). [How] Read the current DISPCLK freq and request the same value to ensure the timing is valid and unchanged. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Chris Park <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: fix minor coding errors where dml21 phase 5 uses wrong ↵Wenjing Liu1-2/+2
variables There is a coding error which causes incorrect variables to be assigned in DML21 phase 5. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove redundant condition in VBA 314 funcIvan Lipski1-9/+0
[WHY] Coverity analysis this conditional code as DEADCODE. The conditional statement is never true since 'MacroTileSizeBytes' is either 256 or 65536. Thus, the code inside is the conditional statement is never reached. [HOW] Removed the conditional statement. Reviewed-by: Aurabindo Pillai <[email protected]> Reviewed-by: Alex Hung <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove redundant condition with DEADCODEIvan Lipski1-3/+0
[WHY] Coverity analysis flagged this condition as DEADCODE since the variable 'req128_c' is always false, thus the condition is never true. [HOW] Remove the condition. Reviewed-by: Aurabindo Pillai <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14Revert "drm/amd/display: workaround for oled eDP not lighting up on DCN401"Joshua Aberback3-5/+0
This reverts commit e902dd7f3e3b93a401e1d3c0322cce933e75e809. A proper fix for this issue has been implemented in DMUB FW. So, no need to keep the workaround. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Add dcn401 DIG fifo enable/disableRelja Vojvodic3-3/+11
[Why] Found while hotplugging MST daisy chain displays. Changing dispclk during this sequence caused SMU hang due to DIG fifo not being disabled correctly (caused by missing functions). [How] Adding disable/enable DIG fifo functions for dcn401 Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Relja Vojvodic <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Enable DCN401 idle optimizations by defaultDillon Varone1-1/+0
[WHY&HOW] Re-enable idle optimizations by default. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: DCN401 full power down in HW init if any link enabledJoshua Aberback2-1/+1
[Why] During HW init, certain operations the driver performs are invalid on enabled hardware in an unknown state (for example, setting all clock values to minimum when the GPU is actively driving a display). There is already code present to call HWSS->power_down during init when any link is enabled in HW, but that function pointer is unpopulated for most asics. We want to enable this codepath for DCN401, as it resolves the issue with being unable to drive certain display configs on adapter re-enable, and we can restore boot optimizations. [How] - add power_down HWSS function for DCN401 - remove debug bit to disable boot optimizations for DCN401 Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdgpu: refine gfx8 firmware loadingYang Wang1-36/+33
refine gfx8 firmware loading Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdkfd: add ASIC version check for the reset selection of RAS poisonTao Zhou1-2/+8
GFX v9.4.3 uses mode1 reset, other ASICs choose mode2. Signed-off-by: Tao Zhou <[email protected]> Acked-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amdkfd: use mode1 reset for RAS poison consumptionTao Zhou1-2/+2
Per firmware's requirement, replace mode2 with mode1. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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