aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu
AgeCommit message (Collapse)AuthorFilesLines
2020-09-15drm/amd/display: Multi display cause system lag on mode changeAric Cyr1-6/+12
[Why] DCValidator is created/destroyed repeatedly for cofunctional validation which causes a lot of memory thrashing, particularly when Driver Verifer is enabled. [How] Implement a basic caching algorithm that will cache DCValidator with a matching topology. When a match is found, the DCValidator can be reused. If there is no match, a new one will be created and inserted into the cache if there is space or an unreference entry can be evicted. Signed-off-by: Aric Cyr <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Disable idle optimization when PSR is enabledZhan Liu1-14/+11
[Why] Idle optimization and PSR conflict each other. If both enabled at the same time, display flickering will be observed. [How] Disable idle optimization when PSR is enabled. Signed-off-by: Zhan Liu <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Don't use DRM_ERROR() for DTM add topologyBhawanpreet Lakha1-1/+1
[Why] Previously we were only calling add_topology when hdcp was being enabled. Now we call add_topology by default so the ERROR messages are printed if the firmware is not loaded. This error message is not relevant for normal display functionality so no need to print a ERROR message. [How] Change DRM_ERROR to DRM_INFO Signed-off-by: Bhawanpreet Lakha <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Compare plane when looking for pipe split being lostAlvin Lee1-6/+8
[Why] There are situations where we go from 2 pipe to 1 pipe in MPO, but this isn't a pipe split being lost -- it's a plane disappearing in (i.e. video overlay goes away) so we lose one pipe. In these situations we don't want to disable the pipe in a separate operation from the rest of the pipe programming sequence. We only want to disable a pipe in a separate operation when we're actually disabling pipe split. [How] Make sure the pipe being lost has the same stream AND plane as the old top pipe to ensure. Signed-off-by: Alvin Lee <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Enabling PSR on DCN30 on driver sideZhan Liu1-2/+16
[Why] PSR needs to be enabled on DCN30. This is the driver part of PSR enablement. Also disabled retired DMCU on driver side, since DMCU is not supported on DCN30 anymore. [How] Add necessary changes to enable PSR on DCN30. Signed-off-by: Zhan Liu <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: remove early return from dm_late_initRoman Li1-3/+0
[Why] ABM feature initialization was not executed due to early return. dm_late_init() had an early return in case if DMCU is not used. With the implementation of ABM on DMUB, DMCU can be disabled but ABM still needs to be initialized. [How] Remove verification for DMCU from the top of the function. The existing logic will handle the case when DMCU is not used. Signed-off-by: Roman Li <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Rename set_mst_bandwidth to align with DP specGeorge Shen8-18/+19
[Why] The function set_mst_bandwidth is poorly name since it isn't clear what it does, and it also does not reflect any part of the allocation sequence described in the DP spec. [How] Rename the function set_mst_bandwidth to set_throttled_vcp_size. Signed-off-by: George Shen <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Flip pending check timeout due to disabled hubpAric Cyr2-0/+6
[Why] When pipe locks are being taken we wait for flip pending to clear first. In some cases the pipe mapping is changed and the pending we're checking for will never clear. [How] Don't check disabled pipes for flip pending. Signed-off-by: Aric Cyr <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Increase Max EDID Size ConstantAidan Gratton1-1/+1
[HOW & WHY] Change max EDID size constant to 1280 to support 10-block EDIDs. Signed-off-by: Aidan Gratton <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Power eDP panel back ON before link training retryAshley Thomas3-22/+74
[why] When link training failures occur for eDP, dp_disable_link_phy is called which powers OFF eDP panel. After link training retry delay, the next retry begins by calling dp_enable_link_phy which does not issue a correspnding eDP panel power ON, leaving panel powered OFF which leads to display OFF/dark. [how] Power ON eDP before next link training retry. Signed-off-by: Ashley Thomas <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Fix CP_IRQ clear bit and logicHarmanprit Tatla2-11/+8
[Why] Currently clearing the wrong bit for CP_IRQ, and logic on when to clear needs to be fixed. [How] Corrected bit to clear and improved logic for decision to clear. Signed-off-by: Harmanprit Tatla <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Only use offset for first ODM pipeWesley Chalmers1-10/+19
[WHY] Only the first pipe in ODM combine group should have nonzero recout offset. All other pipes should have recout offset 0; otherwise there will be gaps in the image. [HOW] Set recout.x to 0 if the pipe is not the leftmost ODM pipe. When computing viewports, calculate the horizontal offset of a pipe's src based on the current pipe's position in the ODM group, plus whatever offset the leftmost ODM pipe has; otherwise there will be discontinuity in the image. Since ODM combine can only combine pipes horizontally, nothing needs to be done for recout.y. Signed-off-by: Wesley Chalmers <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: always use 100us for cr aux rd intervalWenjing Liu1-7/+7
[why] The cr training aux rd interval is modified without following specs requirements. According to the commit message the change was not intended to modify the value. Therefore it looks like it is caused by a typo in the change. Signed-off-by: Wenjing Liu <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: 3.2.101Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: [FW Promotion] Release 0.0.31Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Check clock table returnRodrigo Siqueira1-2/+5
During the load processes for Renoir, our display code needs to retrieve the SMU clock and voltage table, however, this operation can fail which means that we have to check this scenario. Currently, we are not handling this case properly and as a result, we have seen the following dmesg log during the boot: RIP: 0010:rn_clk_mgr_construct+0x129/0x3d0 [amdgpu] ... Call Trace: dc_clk_mgr_create+0x16a/0x1b0 [amdgpu] dc_create+0x231/0x760 [amdgpu] This commit fixes this issue by checking the return status retrieved from the clock table before try to populate any bandwidth. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Triplebuffering should not be used by defaultAric Cyr7-18/+14
Disable triplebuffering by default. Signed-off-by: Aric Cyr <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: add option to override cr training patternWenjing Liu3-12/+23
Signed-off-by: Wenjing Liu <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Compare mpcc_inst to mpcc_count instead of a constantJoshua Aberback1-3/+1
[Why] This assert triggers a false negative because there are more than 4 MPCCs on many asics. [How] - change assert comparisson - remove unused variable Signed-off-by: Joshua Aberback <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Add CP_IRQ clear capabilityHarmanprit Tatla3-0/+29
[Why] Currently we do not clear the CP_IRQ bit upon receiving it. [How] Added a function to clear CP_IRQ bit. Signed-off-by: Harmanprit Tatla <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Detect plane change when detect pipe change.JinZe.Xu2-1/+12
[Why] If plane has changed, dcn20_detect_pipe_changes doesn't update dc_plane_state->update_flags, and the following dcn20_program_pipe can't reprogram hubp correctly. [How] Add a new flags bit "plane_changed" in pipe_ctx->update_flags.If old plane isn’t identical to new plane, this bit will be set and guide “dcn20_program_pipe” to programing HUBP correctly. Signed-off-by: JinZe.Xu <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Fixed Intermittent blue screen on OLED panelNaveed Ashfaq1-6/+5
[why] Changing to smaller modes on OLED panel caused a blue screen crash as driver reported dram change during vactive when it shouldn't [how] Added an extra condition to prevent incorrect dram change timing Signed-off-by: Naveed Ashfaq <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: 3.2.100Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: [FW Promotion] Release 0.0.30Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/pm: support runtime pptable update for sienna_cichlid etc.Jiansong Chen1-3/+9
This avoids smu issue when enabling runtime pptable update for sienna_cichlid and so on. Runtime pptable udpate is needed for test and debug purpose. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amdgpu: drop BOOLEAN define in display partFlora Cui2-4/+2
use bool directly Signed-off-by: Flora Cui <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amdgpu: Enable SDMA utilization for ArcturusMukul Joshi1-0/+9
SDMA utilization calculations are enabled/disabled by writing to SDMAx_PUB_DUMMY_REG2 register. Currently, enable this only for Arcturus. Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Move disable interrupt into commit tailAurabindo Pillai1-33/+14
[Why&How] Since there is no need for accessing crtc state in the interrupt handler, interrupts need not be disabled well in advance, and can be moved to commit_tail where it should be. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/display: Refactor to prevent crtc state access in DM IRQ handlerAurabindo Pillai3-53/+69
[Why&How] Currently commit_tail holds global locks and wait for dependencies which is against the DRM API contracts. Inorder to fix this, IRQ handler should be able to run without having to access crtc state. Required parameters are copied over so that they can be directly accessed from the interrupt handler Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amdgpu: Move existing pflip fields into separate structAurabindo Pillai3-3/+38
[Why&How] To refactor DM IRQ management, all fields used by IRQ is best moved to a separate struct so that main amdgpu_crtc struct need not be changed Location of the new struct shall be in DM Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amdgpu: Update RAS init handlingJohn Clements1-1/+11
Output RAS init status If RAS init fails, teardown RAS context Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amdkfd: Fix -Wunused-const-variable warningYueHaibing1-1/+1
If KFD_SUPPORT_IOMMU_V2 is not set, gcc warns: drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device.c:121:37: warning: ‘raven_device_info’ defined but not used [-Wunused-const-variable=] static const struct kfd_device_info raven_device_info = { ^~~~~~~~~~~~~~~~~ As Huang Rui suggested, Raven already has the fallback path, so it should be out of IOMMU v2 flag. Suggested-by: Huang Rui <[email protected]> Signed-off-by: YueHaibing <[email protected]> Acked-by: Huang Rui <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amdgpu: add ta DTM/HDCP print in amdgpu_firmware_info for apuChangfeng1-7/+36
It needs to add ta DTM/HDCP print to get HDCP/DTM version info when cat amdgpu_firmware_info Signed-off-by: Changfeng <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/pm: update driver if version for navy_flounderJiansong Chen1-1/+1
It's in accordance with pmfw 65.8.0 for navy_flounder. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/pm: update driver if file for sienna cichlidLikun Gao3-11/+16
Update drive if file for sienna_cichlid. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amdgpu: Minor checkpatch fixAndrey Grodzovsky1-2/+4
Signed-off-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amdgpu: Disable DPC for XGMI for now.Andrey Grodzovsky1-0/+5
XGMI support is more complicated than single device support as questions of synchronization between the device recovering from PCI error and other members of the hive are required. Leaving this for next round. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amdgpu: Trim amdgpu_pci_slot_reset by reusing code.Andrey Grodzovsky1-61/+12
Reuse exsisting functions from GPU recovery to avoid code duplications. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amdgpu: Fix consecutive DPC recovery failures.Andrey Grodzovsky5-9/+70
Cache the PCI state on boot and before each case where we might loose it. v2: Add pci_restore_state while caching the PCI state to avoid breaking PCI core logic for stuff like suspend/resume. v3: Extract pci_restore_state from amdgpu_device_cache_pci_state to avoid superflous restores during GPU resets and suspend/resumes. v4: Style fixes. Signed-off-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amdgpu: Fix SMU error failureAndrey Grodzovsky1-2/+20
Wait for HW/PSP initiated ASIC reset to complete before starting the recovery operations. v2: Remove typo Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amdgpu: Block all job scheduling activity during DPC recoveryAndrey Grodzovsky1-4/+53
DPC recovery involves ASIC reset just as normal GPU recovery so block SW GPU schedulers and wait on all concurrent GPU resets. Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amdgpu: Avoid accessing HW when suspending SW stateAndrey Grodzovsky6-7/+65
At this point the ASIC is already post reset by the HW/PSP so the HW not in proper state to be configured for suspension, some blocks might be even gated and so best is to avoid touching it. v2: Rename in_dpc to more meaningful name Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amdgpu: Implement DPC recoveryAndrey Grodzovsky3-1/+177
Add PCI Downstream Port Containment (DPC) with basic recovery functionality v2: remove pci_save_state to avoid breaking suspend/resume v3: Fix style comments v4: Improve description. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amdgpu: Do gpu recovery when no job is runningLiu ChengZhe2-2/+3
In function flr_work, we should do gpu recovery when no job is running. Fix the logic by inverting it. v2: modify the description Reviewed-by: Christian König <[email protected]> Signed-off-by: Liu ChengZhe <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amdkfd: fix a memory leak issueDennis Li1-0/+2
In the resume stage of GPU recovery, start_cpsch will call pm_init which set pm->allocated as false, cause the next pm_release_ib has no chance to release ib memory. Add pm_release_ib in stop_cpsch which will be called in the suspend stage of GPU recovery. Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Dennis Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/kfd: fix a system crash issue during GPU recoveryDennis Li1-1/+1
The crash log as the below: [Thu Aug 20 23:18:14 2020] general protection fault: 0000 [#1] SMP NOPTI [Thu Aug 20 23:18:14 2020] CPU: 152 PID: 1837 Comm: kworker/152:1 Tainted: G OE 5.4.0-42-generic #46~18.04.1-Ubuntu [Thu Aug 20 23:18:14 2020] Hardware name: GIGABYTE G482-Z53-YF/MZ52-G40-00, BIOS R12 05/13/2020 [Thu Aug 20 23:18:14 2020] Workqueue: events amdgpu_ras_do_recovery [amdgpu] [Thu Aug 20 23:18:14 2020] RIP: 0010:evict_process_queues_cpsch+0xc9/0x130 [amdgpu] [Thu Aug 20 23:18:14 2020] Code: 49 8d 4d 10 48 39 c8 75 21 eb 44 83 fa 03 74 36 80 78 72 00 74 0c 83 ab 68 01 00 00 01 41 c6 45 41 00 48 8b 00 48 39 c8 74 25 <80> 78 70 00 c6 40 6d 01 74 ee 8b 50 28 c6 40 70 00 83 ab 60 01 00 [Thu Aug 20 23:18:14 2020] RSP: 0018:ffffb29b52f6fc90 EFLAGS: 00010213 [Thu Aug 20 23:18:14 2020] RAX: 1c884edb0a118914 RBX: ffff8a0d45ff3c00 RCX: ffff8a2d83e41038 [Thu Aug 20 23:18:14 2020] RDX: 0000000000000000 RSI: 0000000000000082 RDI: ffff8a0e2e4178c0 [Thu Aug 20 23:18:14 2020] RBP: ffffb29b52f6fcb0 R08: 0000000000001b64 R09: 0000000000000004 [Thu Aug 20 23:18:14 2020] R10: ffffb29b52f6fb78 R11: 0000000000000001 R12: ffff8a0d45ff3d28 [Thu Aug 20 23:18:14 2020] R13: ffff8a2d83e41028 R14: 0000000000000000 R15: 0000000000000000 [Thu Aug 20 23:18:14 2020] FS: 0000000000000000(0000) GS:ffff8a0e2e400000(0000) knlGS:0000000000000000 [Thu Aug 20 23:18:14 2020] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [Thu Aug 20 23:18:14 2020] CR2: 000055c783c0e6a8 CR3: 00000034a1284000 CR4: 0000000000340ee0 [Thu Aug 20 23:18:14 2020] Call Trace: [Thu Aug 20 23:18:14 2020] kfd_process_evict_queues+0x43/0xd0 [amdgpu] [Thu Aug 20 23:18:14 2020] kfd_suspend_all_processes+0x60/0xf0 [amdgpu] [Thu Aug 20 23:18:14 2020] kgd2kfd_suspend.part.7+0x43/0x50 [amdgpu] [Thu Aug 20 23:18:14 2020] kgd2kfd_pre_reset+0x46/0x60 [amdgpu] [Thu Aug 20 23:18:14 2020] amdgpu_amdkfd_pre_reset+0x1a/0x20 [amdgpu] [Thu Aug 20 23:18:14 2020] amdgpu_device_gpu_recover+0x377/0xf90 [amdgpu] [Thu Aug 20 23:18:14 2020] ? amdgpu_ras_error_query+0x1b8/0x2a0 [amdgpu] [Thu Aug 20 23:18:14 2020] amdgpu_ras_do_recovery+0x159/0x190 [amdgpu] [Thu Aug 20 23:18:14 2020] process_one_work+0x20f/0x400 [Thu Aug 20 23:18:14 2020] worker_thread+0x34/0x410 When GPU hang, user process will fail to create a compute queue whose struct object will be freed later, but driver wrongly add this queue to queue list of the proccess. And then kfd_process_evict_queues will access a freed memory, which cause a system crash. v2: The failure to execute_queues should probably not be reported to the caller of create_queue, because the queue was already created. Therefore change to ignore the return value from execute_queues. Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Dennis Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm: rcar-du: lvds: Add r8a7742 supportLad Prabhakar1-0/+1
The LVDS encoders on RZ/G1H SoC is identical to the R-Car Gen2 family. Add support for RZ/G1H (R8A7742) SoC to the LVDS encoder driver. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Marian-Cristian Rotariu <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]>
2020-09-15drm: rcar-du: Add r8a7742 supportLad Prabhakar1-2/+4
Add direct support for the r8a7742 (RZ/G1H). The RZ/G1H shares a common, compatible configuration with the r8a7790 (R-Car H2) so that device info structure is reused, the only difference being TCON is unsupported on RZ/G1H (Currently unsupported by the driver). Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Marian-Cristian Rotariu <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]>
2020-09-15drm: rcar-du: Make DRM_RCAR_WRITEBACK depends on DRM_RCAR_DUQian Cai1-0/+1
There is no need to select DRM_RCAR_WRITEBACK if DRM_RCAR_DU=n which just make the generated .config a bit ugly. # ARM devices # # end of ARM devices CONFIG_DRM_RCAR_WRITEBACK=y # # Frame buffer Devices Let DRM_RCAR_WRITEBACK depend on DRM_RCAR_DU instead. Signed-off-by: Qian Cai <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Reviewed-by: Kieran Bingham <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]>
2020-09-15drm/msm/dp: Use qmp phy for DP PLL and PHYStephen Boyd18-1762/+78
Make the necessary changes to the DP driver to use the qmp phy from the common phy framework instead of rolling our own in the drm subsystem. This also removes the PLL code and adds proper includes so things build. Cc: Jeykumar Sankaran <[email protected]> Cc: Chandan Uddaraju <[email protected]> Cc: Vara Reddy <[email protected]> Cc: Tanmay Shah <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Manu Gautam <[email protected]> Cc: Sandeep Maheswaram <[email protected]> Cc: Douglas Anderson <[email protected]> Cc: Sean Paul <[email protected]> Cc: Jonathan Marek <[email protected]> Cc: Dmitry Baryshkov <[email protected]> Cc: Rob Clark <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Signed-off-by: Rob Clark <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.