aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu
AgeCommit message (Collapse)AuthorFilesLines
2022-02-17Merge tag 'mediatek-drm-fixes-5.17' of ↵Dave Airlie1-83/+84
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-fixes Mediatek DRM Fixes for Linux 5.17 1. Avoid EPROBE_DEFER loop with external bridge Signed-off-by: Dave Airlie <[email protected]> From: Chun-Kuang Hu <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-02-16drm/amdgpu/gfx10: Add GC 10.3.7 SupportPrike Liang2-1/+57
Needed to properly initialize GC 10.3.7. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu/sdma5.2: add support for SDMA 5.2.7Prike Liang2-0/+6
Initialize SDMA engine firmware loading. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/pm: Add support for MP1 13.0.8Prike Liang4-0/+4
Set smu sw function and enable swSMU support for MP1. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu/psp: Add support for MP0 13.0.8Prike Liang3-0/+9
Set psp sw funcs callback and firmware loading for MP0. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu/gmc10: add support for GC 10.3.7Prike Liang2-0/+3
Set gfxhub function and configure VM for GC block. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu: update vcn/jpeg PG flags for VCN 3.1.1Sathishkumar S1-1/+3
update vcn and jpeg power gating flags for VCN 3.1.1 Signed-off-by: Sathishkumar S <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu: set new revision id for 10.3.7 GCPrike Liang1-0/+5
Add new revision ID for GC 10.3.7 and set cg/pg flags. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu/discovery: set sw common init for GC 10.3.7Prike Liang1-0/+1
Set nv_common_ip_block for GC 10.3.7. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu/discovery: Add 13.0.9 SMUIO blockPrike Liang1-0/+1
Add SMUIO sw function for the new SMUIO block. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd: smu7: downgrade voltage error to infoMario Limonciello1-2/+2
The message `Voltage value looks like a Leakage ID but it's not patched` shows up as an error on Dell Precision 3540. This doesn't cause functional problems and should be downgraded to info. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1162 Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu/discovery: add nbio sw func for 7.5.1 nbioPrike Liang1-0/+1
add nbio sw func for the new 7.5.1 nbio block. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu: make cyan skillfish support code more consistentAlex Deucher5-8/+6
Since this is an existing asic, adjust the code to follow the same logic as previously so the driver state is consistent. No functional change intended. Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: For vblank_disable_immediate, check PSR is really usedMichel Dänzer1-8/+9
Even if PSR is allowed for a present GPU, there might be no eDP link which supports PSR. Fixes: 708978487304 ("drm/amdgpu/display: Only set vblank_disable_immediate when PSR is not enabled") Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdkfd: add return value check for queue evictionTao Zhou1-1/+1
Otherwise gpu reset will be triggered unconditionally in poison consumption. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdkfd: Replace zero-length array with flexible-array memberChangcheng Deng1-1/+1
There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use "flexible array members" for these cases. The older style of one-element or zero-length arrays should no longer be used. Reference: https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays Reported-by: Zeal Robot <[email protected]> Signed-off-by: Changcheng Deng <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: Add dsc pre-validation in atomic checkRoman Li5-16/+229
[Why] The previous change: "Add affected crtcs to atomic state for dsc mst unplug" forces modeset on all added crctc regardless whether timing changed or not. Per our implementation of dsc we need modeset only if timing changed. Otherwise dsc can be programmed incorrectly leading to dsc engine hang. [How] During atomic_check pre-compute dsc params. Only set mode_changed if timing is changed. Reviewed-by: Hersen Wu <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu: Fix wait for RLCG command completionVictor Skvortsov2-1/+3
if (!(tmp & flag)) condition will always evaluate to true when the flag is 0x0 (AMDGPU_RLCG_GC_WRITE). Instead check that address bits are cleared to determine whether the command is complete. Signed-off-by: Victor Skvortsov <[email protected]> Tested-by: Bokun Zhang <[email protected]> Reviewed by: Shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: add dsc mst stream pbn log for debugHersen Wu4-0/+52
[why] payload and slot number of display on dsc mst hub will be adjusted when there is change on any display on dsc hub. to monitor dsc enable/disable, pbn change, we need add log. [How] add mst_pbn to dc_dsc_config of dc_crtc_timing. add dsc, pbn, display name within dc_core_enable_stream, dc_core_disable_stream, dc_stream_log Reviewed-by: Jerry Zuo <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Hersen Wu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: 3.2.173Aric Cyr1-1/+1
This version brings along the following fixes: -Fixes bugs for dsc mst hub -Enables 29 denial itnerface by default -Fixes dmub outbox notificatoin Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: [FW Promotion] Release 0.0.104.0Anthony Koo1-2/+2
Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: Add affected crtcs to atomic state for dsc mst unplugRoman Li1-2/+5
[Why] When display topology changed on DSC hub we add all crtcs with dsc support to atomic state. Refer to patch:"drm/amd/display: Trigger modesets on MST DSC connectors" However the original implementation may skip crtc if the topology change caused by unplug. That potentially could lead to no-lightup or corruption on DSC hub after unplug event on one of the connectors. [How] Update add_affected_mst_dsc_crtcs() to use old connector state if new connector state has no crtc (undergoes modeset due to unplug) Fixes: 44be939ff7ac58 ("drm/amd/display: Trigger modesets on MST DSC connectors") Reviewed-by: Hersen Wu <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: enable z9 denial interface by defaultEric Yang1-1/+1
Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Eric Yang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu: Add "harvest" to IP discovery sysfsLuben Tuikov1-0/+8
Add the "harvest" field to the IP attributes in the IP discovery sysfs visualization, as this field is present in the binary data. At the time of this commit, the harvest data isn't consistently correct in VBIOS, but it is exposed for completeness, in the hopes that VBIOS will be fixed in the future. Cc: Alex Deucher <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: make sure pipe power gating reach requested hw stateCharlene Liu1-3/+18
[why] display mapping change will involved pipe power gating on and off. when doing this too fase, sometimes usbc will have no display. check HW status, it is still in pipe power gating. [how] insert polling HW status to make sure the required state reached. also add dal registry key handling. Reviewed-by: Sung joon Kim <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: dsc mst re-compute pbn for changes on hubHersen Wu1-8/+45
[why] when unplug 1 dp from dsc mst hub, atomic_check new request dc_state only include info for the unplug dp. this will not trigger re-compute pbn for displays still connected to hub. [how] all displays connected to dsc hub are available in dc->current_state, by comparing dc->current_state and new request from atomic_chceck, it will provide info of displays connected to hub and do pbn re-compute. Reviewed-by: Roman Li <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Hersen Wu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: Fix for dmub outbox notification enableMeenakshikumar Somasundaram6-24/+80
[Why] Currently driver enables dmub outbox notification before oubox ISR is registered. During boot scenario, sometimes dmub issues hpd outbox message before driver registers ISR and those messages are missed. [How] Enable dmub outbox notification after outbox ISR is registered. Also, restructured outbox enable code to call from dm layer and renamed APIs. Reviewed-by: Jun Lei <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/pm: fix some OEM SKU specific stability issuesEvan Quan1-1/+31
Add a quirk in sienna_cichlid_ppt.c to fix some OEM SKU specific stability issues. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu: disable MMHUB PG for PicassoEvan Quan1-1/+4
MMHUB PG needs to be disabled for Picasso for stability reasons. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/pm: fulfill Sienna_Cichlid implementations for DriverSmuConfig settingEvan Quan1-0/+54
Fulfill the implementations for DriverSmuConfig setting on Sienna_Cichlid. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/pm: fulfill Navi1x implementations for DriverSmuConfig settingEvan Quan1-0/+50
Fulfill the implementations for DriverSmuConfig setting on Navi1x. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/pm: enable pm sysfs write for one VF modeYiqing Yao1-2/+2
[why] pm sysfs should be writable in one VF mode as is in passthrough [how] do not remove write access on pm sysfs if device is in one VF mode Fixes: 11c9cc95f818 ("amdgpu/pm: Make sysfs pm attributes as read-only for VFs") Signed-off-by: Yiqing Yao <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/pm: correct the default DriverSmuConfig table settingsEvan Quan4-0/+44
For Some ASICs, with the PMFW default settings, we may see the power consumption reported via metrics table is "Very Erratic". With the socket power alpha filter set as 10/100ms, we can correct that issue. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu/sdma5.2: Adjust the name string for firmwareAlex Deucher1-7/+7
This will make it easier to add new firmwares in the future. Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu: check return status before using stable_pstateTom Rix1-1/+2
Clang static analysis reports this problem amdgpu_ctx.c:616:26: warning: Assigned value is garbage or undefined args->out.pstate.flags = stable_pstate; ^ ~~~~~~~~~~~~~ amdgpu_ctx_stable_pstate can fail without setting stable_pstate. So check. Fixes: 8cda7a4f96e4 ("drm/amdgpu/UAPI: add new CTX OP to get/set stable pstates") Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: Protect update_bw_bounding_box FPU code.Bas Nieuwenhuizen2-2/+7
For DCN3/3.01/3.02 at least these use the fpu. v2: squash in build fix for when DCN is not enabled (Leo) Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/i915: Add missing intel_mchbar_regs.hMatt Roper1-0/+221
The new header from the previous commit didn't get added after a conflict resolution...let's add it now. Fixes: e30e6c7b82a1 ("drm/i915: Move MCHBAR registers to their own header") Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-02-16drm/i915: Move MCHBAR registers to their own headerMatt Roper16-210/+14
Registers that exist within the MCH BAR and are mirrored into the GPU's MMIO space are a good candidate to separate out into their own header. For reference, the mirror of the MCH BAR starts at the following locations in the graphics MMIO space (the end of the MCHBAR range differs slightly on each platform): * Pre-gen6: 0x10000 * Gen6-Gen11 + RKL: 0x140000 v2: - Create separate patch to swtich a few register definitions to be relative to the MCHBAR mirror base. - Drop upper bound of MCHBAR mirror from commit message; there are too many different combinations between various platforms to list out, and the documentation is spotty for the older pre-gen6 platforms anyway. Bspec: 134, 51771 Cc: Ville Syrjälä <[email protected]> Suggested-by: Ville Syrjälä <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-02-16drm/i915: Define MCH registers relative to MCHBAR_MIRROR_BASEMatt Roper1-6/+6
A few of our MCH registers are defined with absolute register offsets. For consistency, let's switch their definitions to be relative offsets from MCHBAR_MIRROR_BASE. Cc: Ville Syrjälä <[email protected]> Suggested-by: Ville Syrjälä <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-02-16drm/i915/gt: Order GT registers by MMIO offsetMatt Roper1-1059/+1064
The random order of register definitions we have today causes a lot of confusion and unintentional duplication when new registers/bits are added to the driver. Let's order the GT register file by MMIO offset A couple duplicated/unused register definitions are dropped while doing this re-order: GEN11_GT_INTR_DW{0,1}, GEN11_IIR_REG{0,1}_SELECTOR, and GEN11_INTR_IDENTITY_REG{0,1} aren't used anywhere in the driver because we have other parameterized macros referencing those registers. Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-02-16drm/i915/gt: Use consistent offset notation in intel_gt_regs.hMatt Roper1-103/+103
Switch all register offsets to use lowercase hex values for consistency. Also strip any unnecessary leading 0's. For example, "_MMIO(0x0D08)" becomes "_MMIO(0xd08)." Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-02-16drm/i915/gt: Cleanup spacing of intel_gt_regs.hMatt Roper1-1069/+1069
There's a lot of inconsistent spacing and indentation in our register definitions. Let's clean things up a bit and follow some consistent rules: * "#define" always starts in column 0 * There's exactly one space between '#define' and the name of a register. * There's exactly three spaces between '#define' and the name of a bit/bitfield. * Tabs (no spaces) are used between a definition name and its value; the value starts on column 48 unless the name is too long, in which case a single tab is used. Final diff for this patch is empty if whitespace is ignored: $ git diff -w $ Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-02-16drm/i915/gt: Use parameterized RING_MI_MODEMatt Roper4-12/+10
We have both a parameterized RING_MI_MODE() macro and an RCS-specific MI_MODE; drop the latter and use the former everywhere. Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-02-16drm/i915/gt: Move SFC lock bits to intel_engine_regs.hMatt Roper3-26/+24
These SFC registers were defined in an unusual way, taking an engine as a parameter rather than an engine MMIO base offset. Let's adjust them to match the style used by other per-engine registers and move them to intel_engine_regs.h. While doing this move, we can drop GEN12_HCP_SFC_FORCED_LOCK completely; it was intended for use in an early version of a hardware workaround, but was no longer necessary by the time the workaround was finalized. It is not used anywhere in the driver. Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-02-16drm/panel-edp: Add eDP sharp panel supportSankeerth Billakanti1-0/+44
Add support for the 14" sharp,lq140m1jw46 eDP panel. Signed-off-by: Sankeerth Billakanti <[email protected]> Reviewed-by: Douglas Anderson <[email protected]> Signed-off-by: Douglas Anderson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-02-16drm/i915/gt: Drop duplicate register definition for VDBOX_CGCTL3F18Matt Roper1-3/+0
Due to some mistaken merge conflict resolution, we wound up with a copy of VDBOX_CGCTL3F18 in both intel_engine_regs.h and intel_gt_regs.h. Since this is a per-engine register, referenced relative to an engine's base offset, drop the copy from intel_gt_regs.h Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-02-16gpu: host1x: Always return syncpoint value when waitingMikko Perttunen1-17/+2
The new TegraDRM UAPI uses syncpoint waiting with timeout set to zero to indicate reading the syncpoint value. To support that we need to return the syncpoint value always when waiting. Fixes: 44e961381354 ("drm/tegra: Implement syncpoint wait UAPI") Signed-off-by: Mikko Perttunen <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-02-16drm/mediatek: Allow commands to be sent during video modeJulien STEPHAN1-9/+24
Mipi dsi panel drivers can use mipi_dsi_dcs_{set,get}_display_brightness() to request backlight changes. This can be done during panel initialization (dsi is in command mode) or afterwards (dsi is in Video Mode). When the DSI is in Video Mode, all commands are rejected. Detect current DSI mode in mtk_dsi_host_transfer() and switch modes temporarily to allow commands to be sent. Signed-off-by: Julien STEPHAN <[email protected]> Signed-off-by: Mattijs Korpershoek <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Chun-Kuang Hu <[email protected]>
2022-02-16drm/i915: Unconfuse pre-icl vs. icl+ intel_sagv_{pre,post}_plane_update()Ville Syrjälä1-4/+6
intel_sagv_{pre,post}_plane_update() can accidentally forget to bail out early on pre-icl and proceed down the icl+ codepath at the end of the function. Fortunately it'll bail out before it gets too far due to old_qgv_mask==new_qgv_mask==0 so no real bug here. But lets make the code less confusing anyway. Cc: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Stanislav Lisovskiy <[email protected]>
2022-02-16drm/i915: Widen the QGV point maskVille Syrjälä1-4/+4
adlp+ adds some extra bits to the QGV point mask. The code attempts to handle that but forgot to actually make sure we can store those bits in the bw state. Fix it. Cc: [email protected] Cc: Stanislav Lisovskiy <[email protected]> Fixes: 192fbfb76744 ("drm/i915: Implement PSF GV point support") Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Stanislav Lisovskiy <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.