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2022-03-02drm/amdgpu: Remove redundant calls of amdgpu_ras_block_late_fini in umc ras ↵yipechai4-10/+2
block Remove redundant calls of amdgpu_ras_block_late_fini in umc ras block. Signed-off-by: yipechai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02drm/amdgpu: Remove redundant calls of amdgpu_ras_block_late_fini in nbio ras ↵yipechai3-9/+1
block Remove redundant calls of amdgpu_ras_block_late_fini in nbio ras block. Signed-off-by: yipechai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02drm/amdgpu: Remove redundant calls of amdgpu_ras_block_late_fini in mmhub ↵yipechai3-5/+2
ras block Remove redundant calls of amdgpu_ras_block_late_fini in mmhub ras block. Signed-off-by: yipechai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02drm/amdgpu: Remove redundant calls of amdgpu_ras_block_late_fini in gfx ras ↵yipechai3-9/+1
block Remove redundant calls of amdgpu_ras_block_late_fini in gfx ras block. Signed-off-by: yipechai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02drm/amdgpu: centrally calls the .ras_fini function of all ras blocksyipechai5-26/+14
centrally calls the .ras_fini function of all ras blocks. Signed-off-by: yipechai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02drm/amdgpu: Optimize xxx_ras_fini function of each ras blockyipechai11-21/+21
1. Move the variables of ras block instance members from specific xxx_ras_fini to general ras_fini call. 2. Function calls inside the modules only use parameters passed from xxx_ras_fini instead of ras block instance members. Signed-off-by: yipechai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02drm/amdgpu: Modify .ras_fini function pointer parameteryipechai19-24/+24
Modify .ras_fini function pointer parameter so that we can remove redundant intermediate calls in some ras blocks. Signed-off-by: yipechai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02drm/amd/display: Adding a dc_debug option and dmub setting to use PHY FSM ↵Shah Dharati4-2/+9
for PSR [Why] PSR Power on/off is done in PSR. Add a dc_debug option and dmub setting to use PHY implementation of this instead. [How] Add a dc_debug option and dmub setting to use PHY FSM Power up/down for PSR. Co-authored-by: Shah Dharati <[email protected]> Reviewed-by: Hansen Dsouza <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Shah Dharati <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02drm/amd/display: Add frame alternate 3D & restrict HW packed on donglesDillon Varone3-12/+13
[WHY?] Some projectors support frame alternate 3D modes at 120Hz, but DAL3 does not create timings. Most active DP to HDMI dongles do not translate infoframes properly to use HW packing stereo mode. [HOW?] Create frame alternate 3D timings for displays that support it. Disable HW packing 3D mode on DP active dongles. Reviewed-by: Martin Leung <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02drm/amdgpu: Fix realloc of ptrTom Rix1-2/+7
Clang static analysis reports this error amdgpu_debugfs.c:1690:9: warning: 1st function call argument is an uninitialized value tmp = krealloc_array(tmp, i + 1, ^~~~~~~~~~~~~~~~~~~~~~~~~~~ realloc uses tmp, so tmp can not be garbage. And the return needs to be checked. Fixes: 5ce5a584cb82 ("drm/amdgpu: add debugfs for reset registers list") Reviewed-by: Christian König <[email protected]> Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02drm/amd/display: Reset VIC if HDMI_VIC is presentChris Park1-0/+2
[Why] HDMI Compliance requires VIC to be set to 0 on 2D mode if HDMI_VIC is present. [How] When VIC and HDMI_VIC is both present, reset VIC to 0. Reviewed-by: Martin Leung <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Chris Park <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02drm/amd/display: Make functional resource functions non-staticNicholas Kazlauskas2-2/+7
[Why & How] To align coding style for how we use this across DCN. The resource creation ones can remain static, however. Reviewed-by: Eric Yang <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02drm/amd/display: Remove invalid RDPCS Programming in DALHansen Dsouza1-9/+0
RDPCS programming is done in DMUB remove legacy invalid code Reviewed-by: Alvin Lee <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Hansen Dsouza <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02drm/amdkfd: Add SMI add event helperPhilip Yang1-46/+22
To remove duplicate code, unify event message format and simplify new event add in the following patches. Use KFD_SMI_EVENT_MSG_SIZE to define msg size, the same size will be used in user space to alloc the msg receive buffer. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02drm/amdkfd: Correct SMI event read sizePhilip Yang1-2/+3
sizeof(buf) is 8 bytes because it is defined as unsigned char *buf, each SMI event read only copy max 8 bytes to user buffer. Correct this by using the buf allocate size. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02Revert "drm/amdkfd: process_info lock not needed for svm"Philip Yang1-0/+9
This reverts commit 3abfe30d803e62cc75dec254eefab3b04d69219b. To fix deadlock in kFDSVMEvictTest when xnack off. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02gpu/amd: vega10_hwmgr: fix inappropriate private variable nameMeng Tang1-30/+38
In file vega10_hwmgr.c, the names of struct vega10_power_state * and struct pp_power_state * are confusingly used, which may lead to some confusion. Status quo is that variables of type struct vega10_power_state * are named "vega10_ps", "ps", "vega10_power_state". A more appropriate usage is that struct are named "ps" is used for variabled of type struct pp_power_state *. So rename struct vega10_power_state * which are named "ps" and "vega10_power_state" to "vega10_ps", I also renamed "psa" to "vega10_psa" and "psb" to "vega10_psb" to make it more clearly. The rows longer than 100 columns are involved. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Meng Tang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-02drm/amd/display: Don't fill up the logsLuben Tuikov1-4/+4
Don't fill up the logs with: [253557.859575] [drm:amdgpu_dm_atomic_check [amdgpu]] DSC precompute is not needed. [253557.892966] [drm:amdgpu_dm_atomic_check [amdgpu]] DSC precompute is not needed. [253557.926070] [drm:amdgpu_dm_atomic_check [amdgpu]] DSC precompute is not needed. [253557.959344] [drm:amdgpu_dm_atomic_check [amdgpu]] DSC precompute is not needed. which prints many times a second, when the kernel is run with drm.debug=2. Instead of DRM_DEBUG_DRIVER(), make it DRM_INFO_ONCE(). Cc: Alex Deucher <[email protected]> Cc: Roman Li <[email protected]> Cc: Felix Kuehling <[email protected]> Cc: Hersen Wu <[email protected]> Cc: Daniel Wheeler <[email protected]> Fixes: 17ce8a6907f7 ("drm/amd/display: Add dsc pre-validation in atomic check") Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-03drm/aspeed: Add AST2600 chip supportTommy Haung1-0/+9
Add AST2600 chip support and setting. Signed-off-by: Tommy Haung <[email protected]> Reviewed-by: Joel Stanley <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-03drm/aspeed: Update INTR_STS handlingTommy Haung2-1/+6
Add interrupt clear register define for further chip support. Signed-off-by: Tommy Haung <[email protected]> Reviewed-by: Joel Stanley <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/i915/xehpsdv: Move render/compute engine reset domains related workaroundsSrinivasan Shanmugam1-13/+13
Registers that exist in the shared render/compute reset domain need to be placed on an engine workaround list to ensure that they are properly re-applied whenever an RCS or CCS engine is reset. We have a number of workarounds (updating registers MLTICTXCTL, L3SQCREG1_CCS0, GEN12_MERT_MOD_CTRL, and GEN12_GAMCNTRL_CTRL) that are incorrectly implemented on the 'gt' workaround list and need to be moved accordingly. Cc: Matt Roper <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/i915/xehp: Add compute workaroundsMatt Roper3-0/+56
Additional workarounds are required once we start exposing CCS engines. Note that we have a number of workarounds that update registers in the shared render/compute reset domain. Historically we've just added such registers to the RCS engine's workaround list. But going forward we should be more careful to place such workarounds on a wa_list for an engine that definitely exists and is not fused off (e.g., a platform with no RCS would never apply the RCS wa_list). We'll keep rcs_engine_wa_init() focused on RCS-specific workarounds that only need to be applied if the RCS engine is present. A separate general_render_compute_wa_init() function will be used to define workarounds that touch registers in the shared render/compute reset domain and that we need to apply regardless of what render and/or compute engines actually exist. Any workarounds defined in this new function will internally be added to the first present RCS or CCS engine's workaround list to ensure they get applied (and only get applied once rather than being needlessly re-applied several times). Co-author: Srinivasan Shanmugam Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Daniele Ceraolo Spurio <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/i915/xehp: handle fused off CCS enginesDaniele Ceraolo Spurio3-4/+42
HW resources are divided across the active CCS engines at the compute slice level, with each CCS having priority on one of the cslices. If a compute slice has no enabled DSS, its paired compute engine is not usable in full parallel execution because the other ones already fully saturate the HW, so consider it fused off. v2 (José): - moved it to its own function - fixed definition of ccs_mask v3 (Matt): - Replace fls() condition with a simple IP version test v4 (Matt): - Don't try to calculate a ccs_mask using intel_slicemask_from_dssmask() until we've determined that we're running on an Xe_HP platform where the logic makes sense (and won't overflow). Cc: Stuart Summers <[email protected]> Cc: Vinay Belgaumkar <[email protected]> Cc: Ashutosh Dixit <[email protected]> Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Signed-off-by: Stuart Summers <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/i915/xehp: Don't support parallel submission on compute / renderMatthew Brost2-0/+14
A different emit breadcrumbs ring programming is required for compute / render and we don't have UMD user so just reject parallel submission for these engine classes. Signed-off-by: Matthew Brost <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Daniele Ceraolo Spurio <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/i915/xehp/guc: enable compute engine inside GuCDaniele Ceraolo Spurio1-0/+1
Tell GuC that CCS is enabled by setting the CCS mask in its ADS. Cc: Vinay Belgaumkar <[email protected]> Original-author: Michel Thierry Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Daniele Ceraolo Spurio <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODEMatt Roper6-0/+32
We have to specify in the Render Control Unit Mode register when CCS is enabled. v2: - Move RCU_MODE programming to a helper function. (Tvrtko) - Clean up and clarify comments. (Tvrtko) - Add RCU_MODE to the GuC save/restore list. (Daniele) v3: - Move this patch before the GuC ADS update to enable compute engines; the definition of RCU_MODE and its insertion into the save/restore list moves to this patch. (Daniele) v4: - Call xehp_enable_ccs_engines() directly in guc_resume() and execlists_resume() rather than adding an extra layer of wrapping to the engine->resume() vfunc. (Umesh) Bspec: 46034 Original-author: Michel Thierry Cc: Daniele Ceraolo Spurio <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Vinay Belgaumkar <[email protected]> Cc: Umesh Nerlige Ramappa <[email protected]> Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Signed-off-by: Aravind Iddamsetty <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Umesh Nerlige Ramappa <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/i915/xehp: Define context scheduling attributes in lrc descriptorMatt Roper4-2/+26
In Dual Context mode the EUs are shared between render and compute command streamers. The hardware provides a field in the lrc descriptor to indicate the prioritization of the thread dispatch associated to the corresponding context. The context priority is set to 'low' at creation time and relies on the existing context priority to set it to low/normal/high. Bspec: 46145, 46260 Original-author: Michel Thierry Cc: Tvrtko Ursulin <[email protected]> Signed-off-by: Aravind Iddamsetty <[email protected]> Signed-off-by: Prasad Nallani <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/i915: Move context descriptor fields to intel_lrc.hMatt Roper3-34/+35
This is a more appropriate header for these definitions. v2: - Cleanup whitespace. (Lucas) Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/i915/xehp: CCS should use RCS setup functionsMatt Roper6-7/+16
The compute engine handles the same commands the render engine can (except 3D pipeline), so it makes sense that CCS is more similar to RCS than non-render engines. The CCS context state (lrc) is also similar to the render one, so reuse it. Note that the compute engine has its own CTX_R_PWR_CLK_STATE register. In order to avoid having multiple RCS && CCS checks, add the following engine flag: - I915_ENGINE_HAS_RCS_REG_STATE - use the render (larger) reg state ctx. BSpec: 46260 Original-author: Michel Thierry Cc: Tvrtko Ursulin <[email protected]> Cc: Daniele Ceraolo Spurio <[email protected]> Signed-off-by: Aravind Iddamsetty <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/i915/xehp: compute engine pipe_controlDaniele Ceraolo Spurio2-9/+40
CCS will reuse the RCS functions for breadcrumb and flush emission. However, CCS pipe_control has additional programming restrictions: - Command Streamer Stall Enable must be always set - Post Sync Operations must not be set to Write PS Depth Count - 3D-related bits must not be set v2: - Drop unwanted blank line. (Lucas) Bspec: 47112 Cc: Vinay Belgaumkar <[email protected]> Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Signed-off-by: Aravind Iddamsetty <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/i915/xehp: Add Compute CS IRQ handlersMatt Roper3-1/+19
Add execlists and GuC interrupts for compute CS into existing IRQ handlers. All compute command streamers belong to the same compute class, so the only change needed to enable their interrupts is to program their GT engine interrupt mask registers. CCS0 shares the register with CCS1, while CCS2 and CCS3 are in a new one. BSpec: 50844, 54029, 54030, 53223, 53224. Original-author: Michel Thierry Cc: Tvrtko Ursulin <[email protected]> Cc: Vinay Belgaumkar <[email protected]> Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Signed-off-by: Aravind Iddamsetty <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/i915/xehp: CCS shares the render reset domainMatt Roper1-0/+4
The reset domain is shared between render and all compute engines, so resetting one will affect the others. Note: Before performing a reset on an RCS or CCS engine, the GuC will attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid impacting other clients (since some shared modules will be reset). If other engines are executing non-preemptable workloads, the impact is unavoidable and some work may be lost. Bspec: 52549 Original-author: Michel Thierry Cc: Tvrtko Ursulin <[email protected]> Cc: Vinay Belgaumkar <[email protected]> Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Signed-off-by: Aravind Iddamsetty <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/i915/xehp: Define compute class and engineMatt Roper6-11/+71
Introduce a Compute Command Streamer (CCS), which has access to the media and GPGPU pipelines (but not the 3D pipeline). To begin with, define the compute class/engine common functions, based on the existing render ones. v2: - Add kerneldoc for drm_i915_gem_engine_class since we're adding a new element to it. (Daniel) - Make engine class <-> guc class converters use lookup tables to make it more clear/explicit how the IDs map. (Tvrtko) v3: - Don't update uapi for now; we'll just include the driver-internal changes for the time being. Bspec: 46167, 45544 Original-author: Michel Thierry Cc: Daniele Ceraolo Spurio <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Vinay Belgaumkar <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Signed-off-by: Aravind Iddamsetty <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> #v1 Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/panfrost: cleanup commentsTom Rix5-5/+5
For spdx change tab to space delimiter Use // for *.c Replacements commited to committed regsiters to registers initialze to initialize Signed-off-by: Tom Rix <[email protected]> Reviewed-by: Steven Price <[email protected]> Signed-off-by: Steven Price <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/bridge: nwl-dsi: Remove superfluous write to NWL_DSI_IRQ_MASK registerLiu Ying1-9/+5
To initialize register NWL_DSI_IRQ_MASK, it's enough to write it only once in function nwl_dsi_init_interrupts(). Signed-off-by: Liu Ying <[email protected]> Reviewed-by: Guido Günther <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/bridge: Clear the DP_AUX_I2C_MOT bit passed in aux read command.Hsin-Yi Wang1-0/+2
If the previous transfer didn't end with a command without DP_AUX_I2C_MOT, the next read trasnfer will miss the first byte. But if the command in previous transfer is requested with length 0, it's a no-op to anx7625 since it can't process this command. anx7625 requires the last command to be read command with length > 0. It's observed that if we clear the DP_AUX_I2C_MOT in read transfer, we can still get correct data. Clear the read commands with DP_AUX_I2C_MOT bit to fix this issue. Fixes: adca62ec370c ("drm/bridge: anx7625: Support reading edid through aux channel") Signed-off-by: Hsin-Yi Wang <[email protected]> Reviewed-by: Xin Ji <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-02drm/i915: Depend on !PREEMPT_RT.Sebastian Andrzej Siewior1-0/+1
There are a few sections in the driver which are not compatible with PREEMPT_RT. They trigger warnings and can lead to deadlocks at runtime. Disable the i915 driver on a PREEMPT_RT enabled kernel. This way PREEMPT_RT itself can be enabled without needing to address the i915 issues first. The RT related patches are still in RT queue and will be handled later. Signed-off-by: Sebastian Andrzej Siewior <[email protected]> Acked-by: Tvrtko Ursulin <[email protected]> Signed-off-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-01drm/v3d: centralize error handling when init scheduler failsMelissa Wen1-27/+13
Remove redundant error message (since now it is very similar to what we do in drm_sched_init) and centralize all error handling in a unique place, as we follow the same steps in any case of failure. Signed-off-by: Melissa Wen <[email protected]> Acked-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-01drm/i915/guc: Do not complain about stale reset notificationsJohn Harrison1-4/+3
It is possible for reset notifications to arrive for a context that is in the process of being banned. So don't flag these as an error, just report it as informational (because it is still useful to know that resets are happening even if they are being ignored). v2: Better wording for the message (review feedback from Tvrtko). v3: Fix rebase issue (review feedback from Daniele). Signed-off-by: John Harrison <[email protected]> Reviewed-by: Daniele Ceraolo Spurio <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-01drm/i915/guc: Initialize GuC submission locks and queues earlyDaniele Ceraolo Spurio1-13/+14
Move initialization of submission-related spinlock, lists and workers to init_early. This fixes an issue where if the GuC init fails we might still try to get the lock in the context cleanup code. Note that it is safe to call the GuC context cleanup code even if the init failed because all contexts are initialized with an invalid GuC ID, which will cause the GuC side of the cleanup to be skipped, so it is easier to just make sure the variables are initialized than to special case the cleanup to handle the case when they're not. References: https://gitlab.freedesktop.org/drm/intel/-/issues/4932 Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Matthew Brost <[email protected]> Cc: John Harrison <[email protected]> Reviewed-by: John Harrison <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-01drm/i915/guc: Fix flag query helper function to not modify stateJohn Harrison1-5/+2
A flag query helper was actually writing to the flags word rather than just reading. Fix that. Also update the function's comment as it was out of date. NB: No need for a 'Fixes' tag. The test was only ever used inside a BUG_ON during context registration. Rather than asserting that the condition was true, it was making the condition true. So, in theory, there was no consequence because we should never have hit a BUG_ON anyway. Which means the write should always have been a no-op. Signed-off-by: John Harrison <[email protected]> Reviewed-by: Daniele Ceraolo Spurio <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-01drm/bridge: chipone-icn6211: switch to devm_drm_of_get_bridgeJosé Expósito1-6/+1
The function "drm_of_find_panel_or_bridge" has been deprecated in favor of "devm_drm_of_get_bridge". Switch to the new function and reduce boilerplate. Signed-off-by: José Expósito <[email protected]> Reviewed-by: Maxime Ripard <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-01drm/bridge: anx7625: Fix release wrong workqueueXin Ji1-2/+2
If "hdcp_workqueue" exist, must release "hdcp_workqueue", not "workqueue". Fixes: cd1637c7e480 ("drm/bridge: anx7625: add HDCP support") Signed-off-by: Xin Ji <[email protected]> Reviewed-by: Hsin-Yi Wang <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-01drm/tegra: Support YVYU, VYUY and YU24 formatsThierry Reding3-2/+27
Signed-off-by: Thierry Reding <[email protected]>
2022-03-01drm/tegra: Support semi-planar formats on Tegra114+Thierry Reding5-23/+91
The NV12, NV21, NV16, NV61, NV24 and NV42 formats are supported by Tegra114 and later display hardware. Add the necessary programming to allow them to be used. Note that this does not work for Tegra186 and later yet because those generations have a different display architecture that doesn't support the same formats. Signed-off-by: Thierry Reding <[email protected]>
2022-03-01drm/tegra: Fix planar formats on Tegra186 and laterThierry Reding1-1/+1
Use the correct pitch when programming the DC_WIN_PLANAR_STORAGE_UV register's PITCH_U field to ensure the correct value is used in all cases. This isn't currently causing any problems because the pitch for both U and V planes is always the same. Signed-off-by: Thierry Reding <[email protected]>
2022-03-01gpu: host1x: Fix a memory leak in 'host1x_remove()'Christophe JAILLET1-0/+1
Add a missing 'host1x_channel_list_free()' call in the remove function, as already done in the error handling path of the probe function. Fixes: 8474b02531c4 ("gpu: host1x: Refactor channel allocation code") Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-03-01gpu: host1x: Fix an error handling path in 'host1x_probe()'Christophe JAILLET1-2/+5
Add the missing 'host1x_bo_cache_destroy()' call in the error handling path of the probe, as already done in the remove function. In order to simplify the error handling, move the 'host1x_bo_cache_init()' call after all the devm_ function. Fixes: 1f39b1dfa53c ("drm/tegra: Implement buffer object cache") Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2022-03-01drm/i915/selftests: exercise mmap migrationMatthew Auld3-0/+344
Exercise each of the migration scenarios, verifying that the final placement and buffer contents match our expectations. v2(Thomas): Replace for_i915_gem_ww() block with simpler object_lock() v3: - For testing purposes allow forcing the io_size such that we can exercise the allocation + migration path on devices that don't have the small BAR limit. Signed-off-by: Matthew Auld <[email protected]> Cc: Thomas Hellström <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-03-01drm/i915/selftests: handle allocation failuresMatthew Auld2-2/+8
If we have to contend with non-mappable LMEM, then we need to ensure the object fits within the mappable portion, like in the selftests, where we later try to CPU access the pages. However if it can't then we need to gracefully handle this, without throwing an error. Also it looks like TTM will return -ENOMEM, in ttm_bo_mem_space() after exhausting all possible placements. Signed-off-by: Matthew Auld <[email protected]> Cc: Thomas Hellström <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Acked-by: Nirmoy Das <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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