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2017-11-16drm/amdgpu:fix memleakMonk Liu3-0/+25
those RLC used buffers are not cleared in GFX's sw_fini Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-11-16drm/amdgpu:fix memleak in takedownMonk Liu2-11/+0
this can fix the memory leak under the case that not all BO are freed during "takedown" stage, because originally it blocks following kfree on mgr. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-11-16drm/i915/cnl: Extend HDMI 2.0 support to CNL.Rodrigo Vivi1-3/+4
Starting on GLK we support HDMI 2.0. So this patch only extend the work Shashank has made to GLK to CNL. v2: The version that compiles :/ v3: Invert order to newer || older platforms check. (Ville). Cc: Ville Syrjälä <[email protected]> Cc: Paulo Zanoni <[email protected]> Cc: Shashank Sharma <[email protected]> Cc: Manasi Navare <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-16drm/i915/cnl: Simplify dco_fraction calculation.Rodrigo Vivi1-3/+6
I confess I never fully understood that previous calculation, so this is not a "fix". But let's simplify this math so poor brains like mine can read and make some sense of it in the future. v2: Don't follow the spec since that gives invalid values and it is also confusing. This Ville's version is much simpler. v3: Use u64 cast instead of declaring a u64 dco. (Ville). Cc: Ville Syrjälä <[email protected]> Cc: Mika Kahola <[email protected]> Cc: Manasi Navare <[email protected]> Cc: James Ausmus <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-16drm/i915/cnl: Don't blindly replace qdiv.Rodrigo Vivi1-2/+1
Accordingly to spec "If Kdiv != 2, then Qdiv must be 1." but we already handle qdiv values properly and this case here should be spurious. But instead of blindly replacing let's warn loudly instead. Because it means something was really wrong on initial setup. Cc: Mika Kahola <[email protected]> Cc: Manasi Navare <[email protected]> Cc: James Ausmus <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Manasi Navare <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-16drm/i915/cnl: Fix wrpll math for higher freqs.Rodrigo Vivi1-3/+3
Spec describe all values in MHz. We handle our clocks in KHz. This includes the best_dco_centrality that was forgot in the same unity as spec. Consequently we couldn't get a good divider for high frequenies. Hence HDMI 2.0 wasn't working. Spec tells 999999 for initial best_dco_centrality meaning the max value in MHz. Since we convert dco from MHz to KHz we also need to convert this initial best_doc_centrality to 999999000 or 999999999 or even better, to the max that its variable allow. This patch also replaces the use of "* KHz(1)" with the values directly on KHz to avoid future confusion. v2: Use U32_MAX instead of random 99999 as spec tells. (Ville). Cc: Ville Syrjälä <[email protected]> Cc: Shashank Sharma <[email protected]> Cc: Mika Kahola <[email protected]> Cc: Manasi Navare <[email protected]> Cc: James Ausmus <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-16drm/i915/cnl: Fix, simplify and unify wrpll variable sizes.Rodrigo Vivi1-18/+12
- 64 bits is not needed for afe_clock now we don't convert that to Hz. - 16 bits is not enough for all dco stuff. - unsigned is not relevant/needed for all divisors values. Cc: Mika Kahola <[email protected]> Cc: Manasi Navare <[email protected]> Cc: James Ausmus <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Manasi Navare <[email protected] Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-16drm/i915/cnl: Remove useless conversion.Rodrigo Vivi1-3/+3
No functional change. Just starting the wrpll fixes with a clean-up to make units a bit more clear. Cc: Mika Kahola <[email protected]> Cc: Manasi Navare <[email protected]> Cc: James Ausmus <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Manasi Navare <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-16drm/i915/cnl: Remove spurious central_freq.Rodrigo Vivi1-1/+0
"Display software must leave this field at the default value. It no longer needs to be configured as part of PLL programming." We respect this already and we are setting up the default one line below: "DPLL_CFGCR1_CENTRAL_FREQ". Also we don't touch anywhere else this central_freq for cnl. So let's remove from the final write. No functional change. Only a clean-up patch. Cc: Manasi Navare <[email protected]> Cc: Mika Kahola <[email protected]> Cc: James Ausmus <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Manasi Navare <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-16drm/i915/selftests: exercise_ggtt may have nothing to doChris Wilson1-1/+1
When operating on the live_ggtt we have to find a usuable hole for our test. It is possible for there to be no hole we can use, so initialise the err to 0 for the early exit. Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Joonas Lahtinen <[email protected]>
2017-11-16drm/i915: Don't sanitize frame start delay if the pipe is offVille Syrjälä1-1/+1
Avoid touching PIPECONF in intel_sanitize_crtc() unless the pipe is actually on. Should cure some unclaimed register accesses during reset, as we are rather cavalier in our approach to powerdomain management. We don't have to sanitize this if the pipe is off since we will overwrite the frame start delay anyway when turning the pipe on. v2: Amended commit message to implicate the reset path (Chris) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102249 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2017-11-16drm/i915/guc: Rename i915_guc_submission.c|h to intel_guc_submission.c|hSagar Arun Kamble6-28/+43
With all component structures and functions named appropriately, change the names of GuC submission source files. There were bunch of style issues in guc_submission.c that are highlighted now by checkpatch. Fix those. Update name in Documentation/gpu. (Joonas) v2: Rebase. v3: Rebase. Signed-off-by: Sagar Arun Kamble <[email protected]> Cc: Michal Wajdeczko <[email protected]> Cc: Michal Winiarski <[email protected]> Cc: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Acked-by: Chris Wilson <[email protected]> Acked-by: Joonas Lahtinen <[email protected]> Acked-by: Oscar Mateo <[email protected]> Reviewed-by: Michal Wajdeczko <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Chris Wilson <[email protected]>
2017-11-16drm/i915/guc: Rename i915_guc_client struct to intel_guc_clientSagar Arun Kamble4-37/+37
GuC submission clients are currently being used in kernel only hence update the structure name to intel_guc_client. Signed-off-by: Sagar Arun Kamble <[email protected]> Cc: Michal Wajdeczko <[email protected]> Cc: Michal Winiarski <[email protected]> Cc: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Acked-by: Chris Wilson <[email protected]> Acked-by: Joonas Lahtinen <[email protected]> Acked-by: Oscar Mateo <[email protected]> Reviewed-by: Michal Wajdeczko <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Chris Wilson <[email protected]>
2017-11-16drm/i915/guc: Update name and prototype of GuC submission interface functionsSagar Arun Kamble3-20/+19
i915 GuC submission is hardware interface and GuC APIs that are not user facing should be named intel_guc* hence we change GuC submission related functions name prefix to intel_guc. Also changed the parameter to these functions to intel_guc struct. v2: Using local guc variable in intel_uc_fini_hw. (Michal Wajdeczko) Rebase. Suggested-by: Chris Wilson <[email protected]> Signed-off-by: Sagar Arun Kamble <[email protected]> Cc: Michal Wajdeczko <[email protected]> Cc: Michal Winiarski <[email protected]> Cc: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Acked-by: Chris Wilson <[email protected]> Acked-by: Joonas Lahtinen <[email protected]> Acked-by: Oscar Mateo <[email protected]> Reviewed-by: Michal Wajdeczko <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Chris Wilson <[email protected]>
2017-11-16drm/i915/guc: Update names of submission related static functionsSagar Arun Kamble1-10/+10
i915_guc_submit, i915_guc_dequeue, i915_guc_submission_park and i915_guc_submission_upark are functions internal to GuC submission hence remove "i915_" prefix. Suggested-by: Michal Wajdeczko <[email protected]> Signed-off-by: Sagar Arun Kamble <[email protected]> Cc: Michal Wajdeczko <[email protected]> Cc: Michal Winiarski <[email protected]> Cc: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Reviewed-by: Michal Wajdeczko <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Chris Wilson <[email protected]>
2017-11-16drm/i915: Update execlists tasklet namingSagar Arun Kamble6-20/+21
intel_lrc_irq_handler and i915_guc_irq_handler are HW submission related tasklet functions. Name them with "submission_tasklet" suffix and remove intel/i915 prefix as they are static. Also rename irq_tasklet as just tasklet for clarity. v2: s/_bh/_tasklet (Chris) Suggested-by: Michal Wajdeczko <[email protected]> Signed-off-by: Sagar Arun Kamble <[email protected]> Cc: Michal Wajdeczko <[email protected]> Cc: Michal Winiarski <[email protected]> Cc: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Reviewed-by: Michal Wajdeczko <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Chris Wilson <[email protected]>
2017-11-16drm/i915: Prevent overflow of execbuf.buffer_count and num_cliprectsChris Wilson1-23/+43
We check whether the multiplies will overflow prior to calling kmalloc_array so that we can respond with -EINVAL for the invalid user arguments rather than treating it as an -ENOMEM that would otherwise occur. However, as Dan Carpenter pointed out, we did an addition on the unsigned int prior to passing to kmalloc_array where it would be promoted to size_t for the calculation, thereby allowing it to overflow and underallocate. v2: buffer_count is currently limited to INT_MAX because we treat it as signaled variable for LUT_HANDLE in eb_lookup_vma v3: Move common checks for eb1/eb2 into the same function v4: Put the check back for nfence*sizeof(user_fence) overflow v5: access_ok uses ULONG_MAX but kvmalloc_array uses SIZE_MAX v6: size_t and unsigned long are not type-equivalent on 32b Reported-by: Dan Carpenter <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Tvrtko Ursulin <[email protected]>
2017-11-16drm/i915: Clear breadcrumb node when cancelling signalingChris Wilson1-0/+1
When we call intel_engine_cancel_signaling() to stop reporting when a request is completed via an asynchronous signal, we remove that request from the breadcrumb wait queue. However, we may be concurrently processing that request in the signaler itself, the actual operations on the request's node itself are serialised but we do not actually clear the waiter after removing it from the tree allowing both parties to attempt to do so and corrupting the rbtree. (Previously removing from the breadcrumb wait queue could only be done on behalf of i915_wait_request, so this race could not happen). Reported-by: "He, Bo" <[email protected]> Fixes: 9eb143bbec7d ("drm/i915: Allow a request to be cancelled") Signed-off-by: Chris Wilson <[email protected]> Cc: "He, Bo" <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Michał Winiarski <[email protected]> Cc: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Joonas Lahtinen <[email protected]>
2017-11-16drm/i915: Print the condition causing GEM_BUG_ONMika Kuoppala1-1/+5
It is easier to categorize and debug bugs if the failed condition is in plain sight in the actual dmesg output. Make it so. Cc: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Marta Lofstedt <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Reviewed-by: Joonas Lahtinen <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-16drm/bridge/sii8620: add DVI mode supportMaciej Purski1-18/+18
If the sink device is in HDMI mode, enable infoframe interrupt in scdt irq handle function else call start_video function immediately, because in DVI mode, there is no infoframe interrupt provided. Rename start_hdmi function to start_video and get rid of the old start_video function. In start_video, if the sink is DVI and mode is MHL1 or MHl2, write appropriate values to registers else the path should remain the same as in HDMI mode. Signed-off-by: Maciej Purski <[email protected]> Signed-off-by: Andrzej Hajda <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-16drm/bridge/sii8620: filter unsupported modesMarek Szyprowski1-0/+14
The maximum pixel clock depends on the version of the connected MHL adapter. Add mode_valid callback to filter out modes with too high pixel clock to avoid failure in mode_fixup later. Signed-off-by: Marek Szyprowski <[email protected]> Signed-off-by: Andrzej Hajda <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-16drm/rockchip: vop: add rk3126 vop supportSandy Huang2-0/+36
RK3126 vop register layout is similar with rk3036, so some feature can reuse with rk3036. RK3126 support two overlay plane and one hwc plane, max output resolution is 1080p. it support IOMMU, and its IOMMU same as rk3288's Signed-off-by: Sandy Huang <[email protected]> Reviewed-by: Mark Yao <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-11-15Merge tag 'drm-for-v4.15' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds962-55836/+63190
Pull drm updates from Dave Airlie: "This is the main drm pull request for v4.15. Core: - Atomic object lifetime fixes - Atomic iterator improvements - Sparse/smatch fixes - Legacy kms ioctls to be interruptible - EDID override improvements - fb/gem helper cleanups - Simple outreachy patches - Documentation improvements - Fix dma-buf rcu races - DRM mode object leasing for improving VR use cases. - vgaarb improvements for non-x86 platforms. New driver: - tve200: Faraday Technology TVE200 block. This "TV Encoder" encodes a ITU-T BT.656 stream and can be found in the StorLink SL3516 (later Cortina Systems CS3516) as well as the Grain Media GM8180. New bridges: - SiI9234 support New panels: - S6E63J0X03, OTM8009A, Seiko 43WVF1G, 7" rpi touch panel, Toshiba LT089AC19000, Innolux AT043TN24 i915: - Remove Coffeelake from alpha support - Cannonlake workarounds - Infoframe refactoring for DisplayPort - VBT updates - DisplayPort vswing/emph/buffer translation refactoring - CCS fixes - Restore GPU clock boost on missed vblanks - Scatter list updates for userptr allocations - Gen9+ transition watermarks - Display IPC (Isochronous Priority Control) - Private PAT management - GVT: improved error handling and pci config sanitizing - Execlist refactoring - Transparent Huge Page support - User defined priorities support - HuC/GuC firmware refactoring - DP MST fixes - eDP power sequencing fixes - Use RCU instead of stop_machine - PSR state tracking support - Eviction fixes - BDW DP aux channel timeout fixes - LSPCON fixes - Cannonlake PLL fixes amdgpu: - Per VM BO support - Powerplay cleanups - CI powerplay support - PASID mgr for kfd - SR-IOV fixes - initial GPU reset for vega10 - Prime mmap support - TTM updates - Clock query interface for Raven - Fence to handle ioctl - UVD encode ring support on Polaris - Transparent huge page DMA support - Compute LRU pipe tweaks - BO flag to allow buffers to opt out of implicit sync - CTX priority setting API - VRAM lost infrastructure plumbing qxl: - fix flicker since atomic rework amdkfd: - Further improvements from internal AMD tree - Usermode events - Drop radeon support nouveau: - Pascal temperature sensor support - Improved BAR2 handling - MMU rework to support Pascal MMU exynos: - Improved HDMI/mixer support - HDMI audio interface support tegra: - Prep work for tegra186 - Cleanup/fixes msm: - Preemption support for a5xx - Display fixes for 8x96 (snapdragon 820) - Async cursor plane fixes - FW loading rework - GPU debugging improvements vc4: - Prep for DSI panels - fix T-format tiling scanout - New madvise ioctl Rockchip: - LVDS support omapdrm: - omap4 HDMI CEC support etnaviv: - GPU performance counters groundwork sun4i: - refactor driver load + TCON backend - HDMI improvements - A31 support - Misc fixes udl: - Probe/EDID read fixes. tilcdc: - Misc fixes. pl111: - Support more variants adv7511: - Improve EDID handling. - HDMI CEC support sii8620: - Add remote control support" * tag 'drm-for-v4.15' of git://people.freedesktop.org/~airlied/linux: (1480 commits) drm/rockchip: analogix_dp: Use mutex rather than spinlock drm/mode_object: fix documentation for object lookups. drm/i915: Reorder context-close to avoid calling i915_vma_close() under RCU drm/i915: Move init_clock_gating() back to where it was drm/i915: Prune the reservation shared fence array drm/i915: Idle the GPU before shinking everything drm/i915: Lock llist_del_first() vs llist_del_all() drm/i915: Calculate ironlake intermediate watermarks correctly, v2. drm/i915: Disable lazy PPGTT page table optimization for vGPU drm/i915/execlists: Remove the priority "optimisation" drm/i915: Filter out spurious execlists context-switch interrupts drm/amdgpu: use irq-safe lock for kiq->ring_lock drm/amdgpu: bypass lru touch for KIQ ring submission drm/amdgpu: Potential uninitialized variable in amdgpu_vm_update_directories() drm/amdgpu: potential uninitialized variable in amdgpu_vce_ring_parse_cs() drm/amd/powerplay: initialize a variable before using it drm/amd/powerplay: suppress KASAN out of bounds warning in vega10_populate_all_memory_levels drm/amd/amdgpu: fix evicted VRAM bo adjudgement condition drm/vblank: Tune drm_crtc_accurate_vblank_count() WARN down to a debug drm/rockchip: add CONFIG_OF dependency for lvds ...
2017-11-16drm/i915/gvt: Move request alloc to dispatch_workload path onlyfred gao1-4/+27
Previously the performance is improved through the workload auditing and shadowing ahead of vGPU scheduling, however, there is the case that more requests are allocated in submit_context before the previous request is added, the timeline will hold its seqno which is later. This patch is to move the request alloc to dispatch_workload function, where is the same place as request is added. It will fix the issue of kernel BUG for (timeline->seqno != request->fence.seqno) check when add_request. Fixes: 89ea20b930cb ("drm/i915/gvt: Factor out scan and shadow from workload dispatch") Signed-off-by: Chuanxiao Dong <[email protected]> Signed-off-by: fred gao <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-11-16drm/i915/gvt: Let each vgpu has separate opregion memoryXiong Zhang3-78/+42
Currently every vgpu share a common gvt opregion memory, but it is freed at vgpu destroy, then the later vgpu doesn't have opregion memory once the first vgpu is destroyed. This cause guest function failure like reboot, second or later boot. This patch allocate and init virt opregion memory for each vgpu, so this memory could be freed at vgpu destroy. Signed-off-by: Xiong Zhang <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-11-16drm/i915/gvt: Limit read hw reg to active vgpuXiong Zhang2-4/+37
mmio_read_from_hw() let vgpu could read hw reg, if vgpu's workload is running on hw, things is good. Otherwise vgpu will get other vgpu's reg val, it is unsafe. This patch limit such hw access to active vgpu. If vgpu isn't running on hw, the reg read of this vgpu will get the last active val which saved at schedule_out. v2: ring timestamp is walking continuously even if the ring is idle. so read hw directly. (Zhenyu) Signed-off-by: Xiong Zhang <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-11-16Revert "drm/i915/gvt: Refine broken PPGTT scratch"Zhenyu Wang2-112/+101
This reverts commit b20d09886fd1b74cd2255d846029a049e524db14. This caused windows driver boot errors for invalid page address. Revert for now. Signed-off-by: Zhenyu Wang <[email protected]> Cc: Zhi Wang <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-11-16drm/i915/gvt: Emulate PCI expansion ROM base address registerChangbin Du1-0/+21
Our vGPU doesn't have a device ROM, we need follow the PCI spec to report this info to drivers. Otherwise, we would see below errors. Inspecting possible rom at 0xfe049000 (vd=8086:1912 bdf=00:10.0) qemu-system-x86_64: vfio-pci: Cannot read device rom at 00000000-0000-0000-0000-000000000001 Device option ROM contents are probably invalid (check dmesg). Skip option ROM probe with rombar=0, or load from file with romfile=No option rom signature (got 4860) I will also send a improvement patch to PCI subsystem related to PCI ROM. But no idea to omit below error, since no pattern to detect vbios shadow without touch its content. 0000:00:10.0: Invalid PCI ROM header signature: expecting 0xaa55, got 0x0000 Signed-off-by: Changbin Du <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-11-16drm/i915/gvt: Make gvt_vgpu_err use pr_errChangbin Du1-2/+2
gvt_vgpu_err means something goes wrong. We need the error propagates to kernel message by default. Signed-off-by: Changbin Du <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-11-16drm/i915/gvt: Don't dump partial state in cmd parserChangbin Du1-8/+3
I have seen the cmd parser dump partial odd info. Stop that and only dump the full verbose info when debug enabled. Signed-off-by: Changbin Du <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-11-16drm/i915/gvt: Reduce rcs mocs switch latencyChangbin Du1-1/+1
Use I915_WRITE_FW instead of I915_WRITE to reduce overhead. The overall mmio switch latency lowers from ~600us to ~180us. Signed-off-by: Changbin Du <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-11-16drm/i915/gvt: Add new debugfs tool mmio_diffChangbin Du1-0/+115
This new debugfs entry is used to figure out which registers of vGPU is different to host. It is a useful tool for new platform enabling and debugging. When read this entry, all the diff mmio are recognized and sorted by mmio offset. Besides, the bit positions of different value are listed in 'Diff' column. Here is a show: $ sudo cat ./mmio_diff Offset HW vGPU Diff 00002030 000025f8 00000000 3-8,10,13 00002034 012025f8 00000000 3-8,10,13,21,24 00002038 027fb000 00000000 12-13,15-22,25 0000203c 00003000 00000000 12-13 00002054 0000000a 00000040 1,3,6 00002074 012025f8 00000000 3-8,10,13,21,24 00002080 fffe6000 00000000 13-14,17-31 000020a8 fffffeff ffffffff 8 000020d4 00000004 00000000 2 .... 00145974 eb42718c 010c11b0 2-5,13-14,17-19,22,25,27,29-31 00145978 0000002f 0000002a 0,2 0014597c 0000002f 0000002a 0,2 00145980 0000002b 00000028 0-1 00145984 a5a87c9e b27d20c0 1-4,6,10-12,14,16,18,20,22-26,28 001459c0 88390000 883c0000 16,18 00146200 88350000 883a0000 16-19 Total: 72432, Diff: 901 v3: fix a typo. v2: add mmio_hw_access_pre/post(). Signed-off-by: Changbin Du <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-11-16drm/i915/gvt: Add mmio iterator intel_gvt_for_each_tracked_mmio()Changbin Du3-15/+49
This patch add a function intel_gvt_for_each_tracked_mmio() to iterate each tracked mmio. The caller don't be aware of how the tracked mmios are presented internally. v2: remove snapshot_hw_mmio_registers(). Signed-off-by: Changbin Du <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-11-16drm/i915/gvt: opregion virtualization for win guestXiaolin Zhang1-9/+73
this is an enhanced opregion emulation for win guest support by initializing more data members including opregion header size, version and child device propertity for display port. for simplicity, redefined child_device_config structure. Signed-off-by: Xiaolin Zhang <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-11-16drm/i915/gvt: update CSB and CSB write pointer in virtual HWSPWeinan Li4-1/+49
The engine provides a mirror of the CSB and CSB write pointer in the HWSP. Read these status from virtual HWSP in VM can reduce CPU utilization while applications have much more short GPU workloads. Here we update the corresponding data in virtual HWSP as it in virtual MMIO. Before read these status from HWSP in GVT-g VM, please ensure the host support it by checking the BIT(3) of caps in PVINFO. Virtual HWSP only support GEN8+ platform, since the HWSP MMIO may change follow the platform update, please add the corresponding MMIO emulation when enable new platforms in GVT-g. v3 : Add address audit in HWSP address update. v4 : Separate this patch with enalbe virtual HWSP in VM. Use intel_gvt_render_mmio_to_ring_id() to determine ring_id by offset. v5 : Remove unnessary check about Gen8, GVT-g only support Gen8+. Signed-off-by: Weinan Li <[email protected]> Cc: Zhenyu Wang <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-11-16drm/i915/gvt: Refine broken PPGTT scratchZhi Wang2-101/+112
Refine previously broken PPGTT scratch. Scratch PTE was no correctly handled and also the handling of scratch entries in page table walk was not well organized, which brings gaps of introducing lazy shadow. Signed-off-by: Zhi Wang <[email protected]>
2017-11-16drm/i915/gvt: Introduce ops->set_present()Zhi Wang2-0/+7
We need ops->set_present() during generating a new scratch page table entry. Signed-off-by: Zhi Wang <[email protected]>
2017-11-16drm/i915/gvt: Introduce page table type of current level in GTT type ↵Zhi Wang1-1/+21
enumerations Need to figure out page table type of current level by GTT entry type during getting a scratch page table entry. Signed-off-by: Zhi Wang <[email protected]>
2017-11-16drm/i915/gvt: Fix a bug of unexpectedly clear scratch page tableZhi Wang1-9/+0
During a vGPU reset, the scratch page table shouldn't be cleared, what needs to be cleared should be the scratch page. Signed-off-by: Zhi Wang <[email protected]>
2017-11-16drm/i915/gvt: Let the caller choose if a shadow page should be put into hash ↵Zhi Wang2-14/+15
table As we want to re-use intel_vgpu_shadow_page in buidling scrach page table and we don't want to put scrach page table page into hash table, a new param is introduced to give the caller a choice to decide if a shadow page should be put into hash table. Signed-off-by: Zhi Wang <[email protected]>
2017-11-16drm/i915/gvt: Use I915_GTT_PAGE_SIZEZhi Wang5-43/+45
As there is already an I915_GTT_PAGE_SIZE marco in i915, let GVT-g use it as well. Also this patch re-names some GTT marcos with additional prefix. Signed-off-by: Zhi Wang <[email protected]>
2017-11-16drm/i915/gvt: Export intel_gvt_render_mmio_to_ring_id()Zhi Wang2-6/+17
Since many emulation logic needs to convert the offset of ring registers into ring id, we export it for other caller which might need it. Signed-off-by: Zhi Wang <[email protected]>
2017-11-16drm/i915/gvt: Factor intel_vgpu_page_trackZhi Wang4-114/+136
As the data structure of "intel_vgpu_guest_page" will become much heavier in future, it's better to factor out the guest memory page track mechnisim as early as possible. Signed-off-by: Zhi Wang <[email protected]>
2017-11-16drm/i915/gvt: Refine shadow batch bufferZhi Wang3-71/+100
1) Use standard i915 GEM object sequence to access the shadow batch buffer. 2) Manage i915 vma life cycle to solve one FIXME. v2: - Refine code structure. - Refine the usage of GEM APIs. - Add the missing lock/unlock in release_shadow_batch_buffer. Test on my SKL NuC. Signed-off-by: Zhi Wang <[email protected]>
2017-11-16drm/i915/gvt: Refine find_bb_size()Zhi Wang1-16/+14
Returns the error code if something is wrong and the size of batch buffer is passed through the pointer. Signed-off-by: Zhi Wang <[email protected]>
2017-11-16drm/i915/gvt: Use BIT() to make klockwork happyZhi Wang1-3/+3
Replace the plain bit usage with BIT() to make klockwork happy. Cc: Deng Hongyi <[email protected]> Signed-off-by: Zhi Wang <[email protected]>
2017-11-16drm/i915/gvt: Add basic debugfs infrastructureChangbin Du6-4/+121
We need debugfs entry to expose some debug information of gvt and vGPUs. The first tool will be added is mmio-diff, which help to find the difference values of host and vGPU mmio. It's useful for platform enabling. This patch just add a basic debugfs infrastructure, each vGPU has its own sub-folder. Two simple attributes are created as a template. . ├── num_tracked_mmio ├── vgpu1 | └── active └── vgpu2 └── active Signed-off-by: Changbin Du <[email protected]> Reviewed-by: Zhi Wang <[email protected]> Signed-off-by: Zhi Wang <[email protected]>
2017-11-16drm/i915/gvt: Refactor vGPU type code in kvmgt partfred gao1-120/+8
all the vGPU type related code in kvmgt will be moved into gvt.c/gvt.h files while the common vGPU type related interfaces will be called. v2: - intel_gvt_{init,cleanup}_vgpu_type_groups are initialized in gvt part. (Wang, Zhi) Signed-off-by: fred gao <[email protected]> Reviewed-by: Zhi Wang <[email protected]> Signed-off-by: Zhi Wang <[email protected]>
2017-11-16drm/i915/gvt: Move vGPU type related code into gvt filefred gao2-0/+138
In this patch, all the vGPU type related code will be merged into same gvt file and the common interface will be exposed to both XenGT and KvmGT. v2: - remove the useless mdev_* gvt_ops. add get_gvt_attr ops for MPT module. intel_gvt_{init,cleanup}_vgpu_type_groups are initialized in gvt part. (Wang, Zhi) - set gvt_vgpu_type_groups[i] to NULL. (Zhang,Xiong) Signed-off-by: fred gao <[email protected]> Reviewed-by: Zhi Wang <[email protected]> Signed-off-by: Zhi Wang <[email protected]>
2017-11-16drm/i915/gvt: Move clean_workloads() into scheduler.cZhi Wang2-40/+38
Move clean_workloads() into scheduler.c since it's not specific to execlist. v2: - Remove clean_workloads in intel_vgpu_select_submission_ops. (Zhenyu) Signed-off-by: Zhi Wang <[email protected]>
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