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2020-10-07drm/i915/dg1: Initialize RAWCLK properlyMatt Roper1-1/+15
DG1 always uses a 38.4 MHz rawclk rather than the 19.2/24 MHz frequencies on CNP+. Note that register bits associated with this frequency confusingly use 37 for the divider field rather than 38 as you might expect. For simplicity, let's just assume that this 38.4 MHz frequency will hold true for other future platforms with "fake" PCH south displays and that the CNP-style behavior will remain for other platforms with a real PCH. Bspec: 49950 Bspec: 49309 Cc: Aditya Swarup <[email protected]> Cc: Clinton Taylor <[email protected]> Cc: Lucas De Marchi <[email protected]> Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-07drm/i915/display/ehl: Limit eDP to HBR2José Roberto de Souza2-8/+12
Recent update in documentation defeatured eDP HBR3 for EHL and JSL. v2: - Remove dead code in ehl_get_combo_buf_trans() v3: - Rebase BSpec: 32247 Cc: Matt Roper <[email protected]> Cc: Vidya Srinivas <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-07Revert "gpu/drm: ingenic: Add option to mmap GEM buffers cached"Paul Cercueil3-119/+13
This reverts commit 37054fc81443 ("gpu/drm: ingenic: Add option to mmap GEM buffers cached") At the very moment this commit was created, the DMA API it relied on was modified in the DMA tree, which caused the driver to break in linux-next. Revert it for now, and it will be resubmitted later to work with the new DMA API. Signed-off-by: Paul Cercueil <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-07drm/amdgpu: enable vcn support for green_sardine (v2)Thong Thai1-1/+7
Enable Green_Sardine VCN support and VCN firmware loading v2: use apu flags Signed-off-by: Thong Thai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-07drm/amdgpu: enable green_sardine_asd.bin loading (v2)Aaron Liu1-1/+5
This patch enable green_sardine_asd.bin loading. v2: use apu flags Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-07drm/amdgpu/sdma: add sdma engine support for green_sardine (v2)Prike Liang1-1/+5
Initialize the SDMA IP for green_sardine. v2: use apu flags Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-07drm/amdgpu: add gfx support for green_sardine (v2)Prike Liang1-1/+11
Enable the gfx base HW function of green_sardine. v2: use apu flags Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-07drm/amdgpu: add soc15 common ip block support for green_sardine (v3)Prike Liang1-2/+9
This patch adds common ip support for green_sardine. v2: use apu flags, squash in CG/PG enablement v3: rebase Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-07drm/amdgpu: add green_sardine support for gpu_info and ip block setting (v2)Prike Liang1-1/+5
This patch adds green_sardine support for gpu_info firmware and ip block setting. v2: use apu flag Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-07drm/amdgpu: add Green_Sardine APU flagAlex Deucher1-0/+1
Will be used for Green_Sardine which is a new APU. Signed-off-by: Alex Deucher <[email protected]>
2020-10-07drm/amdgpu: prevent spurious warningAlex Deucher1-1/+3
The default auto setting for kcq should not generate a warning. Fixes: a300de40f66b ("drm/amdgpu: introduce a new parameter to configure how many KCQ we want(v5)") Reviewed-by: Kent Russell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-07drm/amdgpu/swsmu: fix ARC build errorsAlex Deucher2-4/+24
We want to use the dev_* functions here rather than the pr_* variants. Switch to using dev_warn() which mirrors what we do on other asics. Fixes the following build errors on ARC: ../drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c: In function 'navi10_fill_i2c_req': ../arch/arc/include/asm/bug.h:24:2: error: implicit declaration of function 'pr_warn'; did you mean 'drm_warn'? [-Werror=implicit-function-declaration] ../drivers/gpu/drm/amd/amdgpu/../powerplay/sienna_cichlid_ppt.c: In function 'sienna_cichlid_fill_i2c_req': ../arch/arc/include/asm/bug.h:24:2: error: implicit declaration of function 'pr_warn'; did you mean 'drm_warn'? [-Werror=implicit-function-declaration] Reported-by: kernel test robot <[email protected]> Cc: Randy Dunlap <[email protected]> Cc: Evan Quan <[email protected]> Cc: Vineet Gupta <[email protected]> Cc: [email protected] Acked-by: Randy Dunlap <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-07drm/amdgpu: add xgmi perfmons for arcturusJonathan Kim2-0/+52
Add xgmi perfmons for Arcturus. v4: Align with patch 2 with struct improvements v3: Align with patch 2 streamlining perf types versus event config types. v2: Resend for re-review with alignment for v3 in patch 2. Signed-off-by: Jonathan Kim <[email protected]> Tested-by: Chris Freehill <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-07drm/amdgpu: add per device user friendly xgmi events for vega20Jonathan Kim5-148/+408
Non-outbound data metrics are non useful so mark them as legacy. Bucket new perf counters into device and not device ip. Bind events to chip instead of IP. Report available event counters and not number of hw counter banks. Move DF public macros to private since not needed outside of IP version. v5: cleanup by moving per chip configs into structs v4: After more discussion, replace *_LEGACY references with IP references to indicate concept of pmu-typed versus event-config-typed event registration. v3: attr groups const array is global but attr groups are allocated per device which doesn't work and causes problems on memory allocation and de-allocation for pmu unregister. Switch to building const attr groups per pmu instead to simplify solution. v2: add comments on sysfs structure and formatting. Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-07drm/amdgpu: fix xgmi perfmon a-b-a problemJonathan Kim3-75/+78
Mapping hw counters per event config will cause ABA problems so map per event instead. v2: Discontinue starting perf counters if add fails. Make it clear what's happening with pmc_start. Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-07drm/ttm: move ttm_set_memory.h out of includeChristian König3-2/+88
This is not something drivers should use. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michael J. Ruhl <[email protected]> Link: https://patchwork.freedesktop.org/patch/393430/
2020-10-07drm/ttm: remove ttm_bo_unmap_virtual_locked declaration v2Christian König1-1/+1
That was missed during the cleanup. v2: fix comment in vmwgfx as well Signed-off-by: Christian König <[email protected]> Reviewed-by: Michael J. Ruhl <[email protected]> Link: https://patchwork.freedesktop.org/patch/394092/
2020-10-07drm/vmwgfx: move ttm_bo_swapout_all into vmwgfxChristian König2-12/+5
It is the sole user of this. Signed-off-by: Christian König <[email protected]> Acked-by: Daniel Vetter <[email protected]> Link: https://patchwork.freedesktop.org/patch/393498/
2020-10-07drm/ttm: drop glob parameter from ttm_bo_swapoutChristian König2-3/+4
We can always access the global state. Signed-off-by: Christian König <[email protected]> Acked-by: Daniel Vetter <[email protected]> Link: https://patchwork.freedesktop.org/patch/393499/
2020-10-07drm/ttm: nuke ttm_bo_evict_mm and rename mgr function v3Christian König14-39/+47
Make it more clear what the resource manager function does and nuke the wrapper function. v2: nuke the wrapper v3: fix typo in radeon, rebased Signed-off-by: Christian König <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> (v2) Link: https://patchwork.freedesktop.org/patch/393914/
2020-10-07drm/ttm: cleanup ttm_handle_caching_state_failureChristian König1-12/+8
Remove unused parameters, shorten the function name. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michael J. Ruhl <[email protected]> Link: https://patchwork.freedesktop.org/patch/393431/
2020-10-07drm/ttm: make move callback compulstoryDave Airlie1-12/+1
All drivers should have a move callback now so make it compulsory. Reviewed-by: Christian König <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-07drm/vram_helper: implement a ttm move callback.Dave Airlie1-0/+21
This will always do memcpy moves. Acked-by: Christian König <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-07drm/vmwgfx: add a move callback.Dave Airlie1-1/+19
This just copies the fallback to vmwgfx, I'm going to iterate on this a bit until it's not the same as the fallback path. Acked-by: Christian König <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-07drm/vmwgfx: move null mem checks outside move notifiesDave Airlie3-4/+3
Both fns checked mem == NULL, just move the check outside. Acked-by: Christian König <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-07drm/qxl: drop unused code (v2)Dave Airlie1-21/+8
v2: drop the wrapper struct Acked-by: Christian König <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-07drm/nouveau/mem: guard against NULL pointer access in mem_delKarol Herbst1-0/+2
other drivers seems to do something similar Signed-off-by: Karol Herbst <[email protected]> Cc: dri-devel <[email protected]> Cc: Dave Airlie <[email protected]> Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-07drm/nouveau/device: return error for unknown chipsetsKarol Herbst1-0/+1
Previously the code relied on device->pri to be NULL and to fail probing later. We really should just return an error inside nvkm_device_ctor for unsupported GPUs. Fixes: 24d5ff40a732 ("drm/nouveau/device: rework mmio mapping code to get rid of second map") Signed-off-by: Karol Herbst <[email protected]> Cc: dann frazier <[email protected]> Cc: dri-devel <[email protected]> Cc: Dave Airlie <[email protected]> Cc: [email protected] Reviewed-by: Jeremy Cline <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-06drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clockImre Deak1-16/+25
Apply Display WA #22010492432 for combo PHY PLLs too. This should fix a problem where the PLL output frequency is slightly off with the current PLL fractional divider value. I haven't seen an actual case where this causes a problem, but let's follow the spec. It's also needed on some EHL platforms, but for that we also need a way to distinguish the affected EHL SKUs, so I leave that for a follow-up. v2: - Apply the WA at one place when calculating the PLL dividers from the frequency and the frequency from the dividers for all the combo PLL use cases (DP, HDMI, TBT). (Ville) Cc: Ville Syrjälä <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-06drm/i915: Add an encoder hook to sanitize its state during init/resumeImre Deak5-0/+47
Atm, if a full modeset is performed during the initial modeset the link training will happen with uninitialized max DP rate and lane count. Make sure the corresponding encoder state is initialized by adding an encoder hook called during driver init and system resume. A better alternative would be to store all states in the CRTC state and make this state available for the link re-training code. Also instead of the DPCD read in the hook there should be really a proper sink HW readout in place. Both of these require a bigger rework, so for now opting for this minimal fix to make at least full initial modesets work. The patch is based on https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3 v2: (Ville) - s/sanitize_state/sync_state/ - No point in calling the hook when CRTC is disabled, remove the call. - No point in calling the hook for MST, remove it. v3: Check only DPCD_REV to avoid clobbering intel_dp->dpcd. (Ville) Cc: Ville Syrjälä <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-06drm/i915: Check for unsupported DP link rates during initial commitImre Deak1-0/+12
Some BIOSes set an unsupported/imprecise DP link rate (for instance on TGL A stepping). Make sure that we do an encoder recompute and a modeset in this case. Cc: Ville Syrjälä <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-06drm/i915: Move the initial fastset commit check to encoder hooksImre Deak7-16/+78
Move the checks to decide whether a fastset is possible during the initial commit to an encoder hook. This check is really encoder specific and the next patch will also require this adding a DP encoder specific check. v2: Fix negated condition in gen11_dsi_initial_fastset_check(). v3: Make sure to call the hook for all encoders on the crtc. (Ville) Cc: Ville Syrjälä <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-06drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programmingImre Deak2-0/+14
The BIOS of at least one ASUS-Z170M system with an SKL I have programs the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with bit#0 incorrectly set. This happens with the "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9 HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1 WRPLL parameters (assuming PDIV=7 was the intended setting). This corresponds to 262749 PLL frequency/port clock. Later the driver sets the same mode for which it calculates the same dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding). Based on the above, let's assume that PDIV=7 was intended and the HW just ignores bit#0 in the PDIV register field for this setting, treating 100b and 101b encodings the same way. While at it add the MISSING_CASE() for the p0,p2 divider decodings. v2: (Ville) - Add a define for the incorrect divider value. - Emit only a debug message when detecting the incorrect divider value. - Use fallthrough from the incorrect divider value case. - Add the MISSING_CASE()s. v3: Return 0 freq for incorrect divider values. (Ville) Cc: Ville Syrjälä <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-06dma-mapping: split <linux/dma-mapping.h>Christoph Hellwig2-1/+2
Split out all the bits that are purely for dma_map_ops implementations and related code into a new <linux/dma-map-ops.h> header so that they don't get pulled into all the drivers. That also means the architecture specific <asm/dma-mapping.h> is not pulled in by <linux/dma-mapping.h> any more, which leads to a missing includes that were pulled in by the x86 or arm versions in a few not overly portable drivers. Signed-off-by: Christoph Hellwig <[email protected]>
2020-10-06drm/nouveau/ttm: memcpy waits for bo alreadyDave Airlie1-3/+1
no need for driver to wait here. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-06drm/nouveau/ttm: handle ttm moves properly.Dave Airlie1-0/+12
The idea is to flip the core over to calling the driver always, so add support for moves here. Signed-off-by: Dave Airlie <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-05lib/scatterlist: Add support in dynamic allocation of SG table from pagesMaor Gottlieb2-12/+15
Extend __sg_alloc_table_from_pages to support dynamic allocation of SG table from pages. It should be used by drivers that can't supply all the pages at one time. This function returns the last populated SGE in the table. Users should pass it as an argument to the function from the second call and forward. As before, nents will be equal to the number of populated SGEs (chunks). With this new extension, drivers can benefit the optimization of merging contiguous pages without a need to allocate all pages in advance and hold them in a large buffer. E.g. with the Infiniband driver that allocates a single page for hold the pages. For 1TB memory registration, the temporary buffer would consume only 4KB, instead of 2GB. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Maor Gottlieb <[email protected]> Reviewed-by: Christoph Hellwig <[email protected]> Signed-off-by: Leon Romanovsky <[email protected]> Signed-off-by: Jason Gunthorpe <[email protected]>
2020-10-05drm/i915/dg1: Wait for pcode/uncore handshake at startupMatt Roper4-0/+23
DG1 does some additional pcode/uncore handshaking at boot time; this handshaking must complete before various other pcode commands are effective and before general work is submitted to the GPU. We need to poll a new pcode mailbox during startup until it reports that this handshaking is complete. The bspec doesn't give guidance on how long we may need to wait for this handshaking to complete. For now, let's just set a really long timeout; if we still don't get a completion status by the end of that timeout, we'll just continue on and hope for the best. v2 (Lucas): Rename macros to make clear the relation between command and result (requested by José) Bspec: 52065 Cc: Clinton Taylor <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: Radhakrishna Sripada <[email protected]> Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-05drm/i915: don't conflate is_dgfx with fake lmemLucas De Marchi2-3/+1
When using fake lmem for tests, we are overriding the setting in device info for dgfx devices. Current users of IS_DGFX() except one are correct. However, as we add support for DG1, we are going to use it in additional places to trigger dgfx-only code path. In future if we need we can use HAS_LMEM() instead of IS_DGFX() in the places that make sense to also contemplate fake lmem use. v2: update gen8_gmch_probe() to use HAS_LMEM(): we need to steal the mappable aperture later(which is fine since it doesn't exist on "DGFX"), and use it as a substitute for LMEMBAR. The !mappable aperture property is also useful since it exercises some other parts of the code too. (Matthew Auld) Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-05drm/amd/display: 3.2.106Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: [FW Promotion] Release 0.0.36Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Only flush inst_fb if backdoor loadingAlvin Lee1-8/+9
[Why] DAL resume from BACO time is longer if we always flush inst_fb [How] Check if backdoor loading to flush inst_fb Signed-off-by: Alvin Lee <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Program meta addresses correctlyAlvin Lee2-0/+4
[Why] When forcing 3D mode in DAL, we set the right address to be the same as the left address. We need to do the same for the meta addresses. [How] Program right meta to be same as left meta. Signed-off-by: Alvin Lee <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Hardcode 45W Bounding Box for DCN2.1 DiagsSung Lee1-83/+36
[WHY] Currently construction of clock limits gets skipped for diags. This logic would be useful to get tested in diags. [HOW] Copy existing states to clk_table such that update_bw_bounding_box logic gets used to fill the table. Signed-off-by: Sung Lee <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: FreeSync not active near lower bound of non-LFC monitor rangeAric Cyr1-4/+6
[Why] On narrow range monitors without LFC, a margin prevents good utilization of the available range. [How] Decrease the margin for exiting fixed mode and fix the frame counter to reset if a non-consecutive render is found. Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Fix OPTC_DATA_FORMAT programmingDmytro Laktyushkin3-16/+11
This should be programmed with timing rather than with odm. Signed-off-by: Dmytro Laktyushkin <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Add i2c speed arbitration for dc_i2c and hdcp_i2cCharlene Liu11-3/+20
[why] HDCP 1.4 failed on SL8800 SW w/a test driver use. [how] Slow down the HW i2c speed when used by HW i2c. This request: each acquired_i2c_engine setup the i2c speed needed and sets the I2c engine for HDCP use at release_engine. This covers SW using HW i2c engine and HDCP using HW i2c engine. for dmcu using HW i2c engine, needs add similar logic in dmcu fw. Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Chris Park <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Block ABM in case of eDP ODMYongqiang Sun6-0/+24
[Why] enable ODM on eDP panel with ABM will result in color difference on the panel due to only one ABM module to set one pipe. [How] Block ABM in case of ODM enabled on eDP. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Copy WM values from set A to other sets in hw_initJoshua Aberback3-0/+47
[Why] When we transfer the WM range table to SMU, they can perform a watermark switch right away. This can be a problem if we're in not in accelerated mode during hw_init as SMU may initiate a dummy p-state change before the rest of the watermarks are programmed. Watermark set A is defined to be sufficient for all cases, so we can copy the values from set A to all other sets, avoiding any issues from SMU doing WM switches. [How] - new hubbub func init_watermarks - copy register values from set A to all other sets - call init_watermarks before calling notify_wm_ranges Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Force enable pstate on driver unloadJoshua Aberback7-6/+29
[Why] During driver unload, it is expected that p-state switching is supported. If it's not supported, PMFW will hang due to a forced p-state switch. Even if the current timing does not support p-state normally, we still want to force allow because the worst that can happen is underflow. This will match Navi10 behaviour. [How] - new hubbub func to control the force pstate register - force allow when releasing display ownership - registers are inaccessible after due to m_cgs.hwNotAvailable - explicitly disable force signal during hw_init - if driver is disabled and re-enabled, register not cleared otherwise Also, remove DCN3 part of dcn10_init_hw, we will not be going back to it. Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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