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2021-08-09drm/amdgpu: fix kernel-doc warnings on non-kernel-doc commentsRandy Dunlap1-3/+3
Don't use "begin kernel-doc notation" (/**) for comments that are not kernel-doc. This eliminates warnings reported by the 0day bot. drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:89: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * This shader is used to clear VGPRS and LDS, and also write the input drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:209: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * The below shaders are used to clear SGPRS, and also write the input drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:301: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * This shader is used to clear the uninitiated sgprs after the above Fixes: 0e0036c7d13b ("drm/amdgpu: fix no full coverage issue for gprs initialization") Signed-off-by: Randy Dunlap <[email protected]> Reported-by: kernel test robot <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Cc: "Pan, Xinhui" <[email protected]> Cc: Dennis Li <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: use do-while-0 for DC_TRACE_LEVEL_MESSAGE()Randy Dunlap1-1/+1
Building with W=1 complains about an empty 'else' statement, so use the usual do-nothing-while-0 loop to quieten this warning. ../drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_psr.c:113:53: warning: suggest braces around empty body in an 'else' statement [-Wempty-body] 113 | *state, retry_count); Fixes: b30eda8d416c ("drm/amd/display: Add ETW log to dmub_psr_get_state") Signed-off-by: Randy Dunlap <[email protected]> Cc: Wyatt Wood <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Cc: "Pan, Xinhui" <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Leo Li <[email protected]> Cc: [email protected] Cc: [email protected] Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: use GFP_ATOMIC in amdgpu_dm_irq_schedule_workAnson Jacob1-1/+1
Replace GFP_KERNEL with GFP_ATOMIC as amdgpu_dm_irq_schedule_work can't sleep. BUG: sleeping function called from invalid context at include/linux/sched/mm.h:196 in_atomic(): 1, irqs_disabled(): 1, non_block: 0, pid: 253, name: kworker/6:1H CPU: 6 PID: 253 Comm: kworker/6:1H Tainted: G W OE 5.11.0-promotion_2021_06_07-18_36_28_prelim_revert_retrain #8 Hardware name: System manufacturer System Product Name/PRIME X570-PRO, BIOS 3405 02/01/2021 Workqueue: events_highpri dm_irq_work_func [amdgpu] Call Trace: <IRQ> dump_stack+0x5e/0x74 ___might_sleep.cold+0x87/0x98 __might_sleep+0x4b/0x80 kmem_cache_alloc_trace+0x390/0x4f0 amdgpu_dm_irq_handler+0x171/0x230 [amdgpu] amdgpu_irq_dispatch+0xc0/0x1e0 [amdgpu] amdgpu_ih_process+0x81/0x100 [amdgpu] amdgpu_irq_handler+0x26/0xa0 [amdgpu] __handle_irq_event_percpu+0x49/0x190 ? __hrtimer_get_next_event+0x4d/0x80 handle_irq_event_percpu+0x33/0x80 handle_irq_event+0x33/0x60 handle_edge_irq+0x82/0x190 asm_call_irq_on_stack+0x12/0x20 </IRQ> common_interrupt+0xbb/0x140 asm_common_interrupt+0x1e/0x40 RIP: 0010:amdgpu_device_rreg.part.0+0x44/0xf0 [amdgpu] Code: 53 48 89 fb 4c 3b af c8 08 00 00 73 6d 83 e2 02 75 0d f6 87 40 62 01 00 10 0f 85 83 00 00 00 4c 03 ab d0 08 00 00 45 8b 6d 00 <8b> 05 3e b6 52 00 85 c0 7e 62 48 8b 43 08 0f b7 70 3e 65 8b 05 e3 RSP: 0018:ffffae7740fff9e8 EFLAGS: 00000286 RAX: ffffffffc05ee610 RBX: ffff8aaf8f620000 RCX: 0000000000000006 RDX: 0000000000000000 RSI: 0000000000005430 RDI: ffff8aaf8f620000 RBP: ffffae7740fffa08 R08: 0000000000000001 R09: 000000000000000a R10: 0000000000000001 R11: 0000000000000001 R12: 0000000000005430 R13: 0000000071000000 R14: 0000000000000001 R15: 0000000000005430 ? amdgpu_cgs_write_register+0x20/0x20 [amdgpu] amdgpu_device_rreg+0x17/0x20 [amdgpu] amdgpu_cgs_read_register+0x14/0x20 [amdgpu] dm_read_reg_func+0x38/0xb0 [amdgpu] generic_reg_wait+0x80/0x160 [amdgpu] dce_aux_transfer_raw+0x324/0x7c0 [amdgpu] dc_link_aux_transfer_raw+0x43/0x50 [amdgpu] dm_dp_aux_transfer+0x87/0x110 [amdgpu] drm_dp_dpcd_access+0x72/0x110 [drm_kms_helper] drm_dp_dpcd_read+0xb7/0xf0 [drm_kms_helper] drm_dp_get_one_sb_msg+0x349/0x480 [drm_kms_helper] drm_dp_mst_hpd_irq+0xc5/0xe40 [drm_kms_helper] ? drm_dp_mst_hpd_irq+0xc5/0xe40 [drm_kms_helper] dm_handle_hpd_rx_irq+0x184/0x1a0 [amdgpu] ? dm_handle_hpd_rx_irq+0x184/0x1a0 [amdgpu] handle_hpd_rx_irq+0x195/0x240 [amdgpu] ? __switch_to_asm+0x42/0x70 ? __switch_to+0x131/0x450 dm_irq_work_func+0x19/0x20 [amdgpu] process_one_work+0x209/0x400 worker_thread+0x4d/0x3e0 ? cancel_delayed_work+0xa0/0xa0 kthread+0x124/0x160 ? kthread_park+0x90/0x90 ret_from_fork+0x22/0x30 Reviewed-by: Aurabindo Jayamohanan Pillai <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Anson Jacob <[email protected]> Cc: [email protected] Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: Increase timeout threshold for DMCUB resetNicholas Kazlauskas1-5/+5
[Why] If we're backdoor loading the DMCUB performs more work than just the PHY reset so we can end up resetting before the cleanup has fully finished. [How] Increase timeout, add udelay between spins to guarantee a minimum. Reviewed-by: Roy Chan <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: Clear GPINT after DMCUB has resetNicholas Kazlauskas1-4/+4
[Why] Otherwise we can end up processing whatever was left in the register if the DMCUB was previously reset. If DMCUB gets force reset too early from another client then we might not have even acked the disable yet - causing DMCUB instantly shutdown if the command was 10020000. [How] Move the GPINT clear outside of the reset loop and do it unconditionally after the DMCUB has been properly reset. Reviewed-by: Roy Chan <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: 3.2.148Anthony Koo1-1/+1
This version brings along following fixes: - Fix memory allocation in dm IRQ context to use GFP_ATOMIC - Increase timeout threshold for DMCUB reset - Clear GPINT after DMCUB has reset - Add AUX I2C tracing - Fix code commenting style - Some refactoring - Remove invalid assert for ODM + MPC case Reviewed-by: Wyatt Wood <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: [FW Promotion] Release 0.0.78Anthony Koo1-2/+2
Acked-by: Anson Jacob <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: add authentication_complete in hdcp outputWenjing Liu7-79/+93
[why] DM needs to be notified when hdcp module has completed authentication attempt. Reviewed-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: Add AUX I2C tracing.Ashley Thomas1-9/+183
[Why] Developers can find it useful if the driver can produce AUX traces without special equipment. [How] Add AUX tracing. Reviewed-by: Zhan Liu <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Ashley Thomas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: Correct comment styleRoy Chan1-1/+1
Acked-by: Anson Jacob <[email protected]> Signed-off-by: Roy Chan <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: fix incorrect CM/TF programming sequence in dwbRoy Chan1-26/+64
[How] the programming sequeune was for old asic. the correct programming sequeunce should be similar to the one used in mpc. the fix is copied from the mpc programming sequeunce. Reviewed-by: Anthony Koo <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Roy Chan <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: refactor the cursor programing codesRoy Chan1-41/+65
Acked-by: Anson Jacob <[email protected]> Signed-off-by: Roy Chan <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: refactor the codes to centralize the stream/pipe checking logicRoy Chan1-21/+41
Acked-by: Anson Jacob <[email protected]> Signed-off-by: Roy Chan <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: fix missing writeback disablement if plane is removedRoy Chan2-7/+19
[Why] If the plane has been removed, the writeback disablement logic doesn't run [How] fix the logic order Acked-by: Anson Jacob <[email protected]> Signed-off-by: Roy Chan <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: Remove invalid assert for ODM + MPC caseEric Bernstein1-1/+0
Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Eric Bernstein <[email protected]> Cc: [email protected] Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/amdgpu: skip locking delayed work if not initialized.YuBiao Wang1-1/+2
When init failed in early init stage, amdgpu_object has not been initialized, so hasn't the ttm delayed queue functions. Signed-off-by: YuBiao Wang <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amdgpu: Extend full access wait time in guestVictor Zhao1-4/+12
- Extend wait time and add retry, currently 6s * 2times - Change timing algorithm Signed-off-by: Victor Zhao <[email protected]> Signed-off-by: Peng Ju Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/mediatek: Test component initialization earlier in the function ↵Dafna Hirschfeld1-8/+8
mtk_drm_crtc_create The initialization is currently tested in a later stage in the function for no reason. In addition, the test '!comp' will never fail since comp is set with the '&' operator. Instead, test if a comp was not initialized by testing "!comp->dev". Signed-off-by: Dafna Hirschfeld <[email protected]> Signed-off-by: Chun-Kuang Hu <[email protected]>
2021-08-09drm/mediatek: Add support for main DDP path on MT8167Fabien Parent1-0/+38
Add the main (DSI) drm display path for MT8167. Signed-off-by: Fabien Parent <[email protected]> Signed-off-by: Chun-Kuang Hu <[email protected]>
2021-08-09drm/mediatek: Implement mmap as GEM object functionThomas Zimmermann3-46/+14
Moving the driver-specific mmap code into a GEM object function allows for using DRM helpers for various mmap callbacks. The respective mediatek functions are being removed. The file_operations structure fops is now being created by the helper macro DEFINE_DRM_GEM_FOPS(). Signed-off-by: Thomas Zimmermann <[email protected]> Signed-off-by: Chun-Kuang Hu <[email protected]>
2021-08-09drm/i915/gvt: Fix cached atomics setting for Windows VMZhenyu Wang2-0/+3
We've seen recent regression with host and windows VM running simultaneously that cause gpu hang or even crash. Finally bisect to commit 58586680ffad ("drm/i915: Disable atomics in L3 for gen9"), which seems cached atomics behavior difference caused regression issue. This tries to add new scratch register handler and add those in mmio save/restore list for context switch. No gpu hang produced with this one. Cc: [email protected] # 5.12+ Cc: "Xu, Terrence" <[email protected]> Cc: "Bloomfield, Jon" <[email protected]> Cc: "Ekstrand, Jason" <[email protected]> Reviewed-by: Colin Xu <[email protected]> Fixes: 58586680ffad ("drm/i915: Disable atomics in L3 for gen9") Signed-off-by: Zhenyu Wang <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-09drm/xlnx/zynqmp_disp: Fix incorrectly named enum 'zynqmp_disp_layer_id'Lee Jones1-1/+1
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/xlnx/zynqmp_disp.c:101: warning: expecting prototype for enum zynqmp_disp_id. Prototype was for enum zynqmp_disp_layer_id instead Signed-off-by: Lee Jones <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-09drm: xlnx: zynqmp_dpsub: Expose plane ordering to userspaceLaurent Pinchart1-0/+1
While the DPSUB has a fixed plane order, it still makes sense to expose it to userspace to avoid hardcoding assumptions. Do so by adding an immutable zpos property to planes. Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-09drm: xlnx: zynqmp_dpsub: Add global alpha supportLaurent Pinchart1-2/+7
The graphics plane has a global alpha setting. Expose it through the plane's alpha property. Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-09drm: xlnx: zynqmp_dpsub: Fix graphics layer blendingLaurent Pinchart1-1/+11
To display the graphics layer, the global alpha needs to be enabled. Enable it when the graphics plane is enabled (with full opacity), and disable it otherwise. Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-09drm: xlnx: zynqmp_dpsub: Pass disp structure to all internal functionsLaurent Pinchart1-145/+121
The internal functions dealing with the audio/video buffer manager, the blender, and the audio mixer, all receive pointers to the respective objects. Those objects are embedded in the zynqmp_disp structure, and a very small. Treating them as separate objects would require expanding them with back-pointers to the zynqmp_disp in order to access fields such as the device pointer for debug messages, and this isn't worth it. Instead, merge those structures with the zynqmp_disp structure, and pass the zynqmp_disp pointer to all internal functions. Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-09drm: xlnx: zynqmp: Add zynqmp_disp_layer_is_video() to simplify the codeQuanyang Wang1-17/+22
Add a new function zynqmp_disp_layer_is_video() to simplify the code that judges if a layer is the video layer. Acked-by: Paul Cercueil <[email protected]> Signed-off-by: Quanyang Wang <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> [Renamed is_layer_vid() to zynqmp_disp_layer_is_video()]] Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-09drm: xlnx: zynqmp: release reset to DP controller before accessing DP registersQuanyang Wang1-10/+12
When insmod zynqmp-dpsub.ko after rmmod it, system will hang with the error log as below: root@xilinx-zynqmp:~# insmod zynqmp-dpsub.ko [ 88.391289] [drm] Initialized zynqmp-dpsub 1.0.0 20130509 for fd4a0000.display on minor 0 [ 88.529906] Console: switching to colour frame buffer device 128x48 [ 88.549402] zynqmp-dpsub fd4a0000.display: [drm] fb0: zynqmp-dpsubdrm frame buffer device [ 88.571624] zynqmp-dpsub fd4a0000.display: ZynqMP DisplayPort Subsystem driver probed root@xilinx-zynqmp:~# rmmod zynqmp_dpsub [ 94.023404] Console: switching to colour dummy device 80x25 root@xilinx-zynqmp:~# insmod zynqmp-dpsub.ko <hang here> This is because that in zynqmp_dp_probe it tries to access some DP registers while the DP controller is still in the reset state. When running "rmmod zynqmp_dpsub", zynqmp_dp_reset(dp, true) in zynqmp_dp_phy_exit is called to force the DP controller into the reset state. Then insmod will call zynqmp_dp_probe to program the DP registers, but at this moment the DP controller hasn't been brought out of the reset state yet since the function zynqmp_dp_reset(dp, false) is called later and this will result the system hang. Releasing the reset to DP controller before any read/write operation to it will fix this issue. And for symmetry, move zynqmp_dp_reset() call from zynqmp_dp_phy_exit() to zynqmp_dp_remove(). Signed-off-by: Quanyang Wang <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-09drm: xlnx: zynqmp_dpsub: Update dependencies for ZynqMP DPDylan Yip1-0/+2
ZynqMP DP requires the ZynqMP PHY and DPDMA to operate properly. So depend on both the PHY and DPDMA. Signed-off-by: Dylan Yip <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-09drm: xlnx: zynqmp_dpsub: Call pm_runtime_get_sync before setting pixel clockQuanyang Wang1-1/+2
The Runtime PM subsystem will force the device "fd4a0000.zynqmp-display" to enter suspend state while booting if the following conditions are met: - the usage counter is zero (pm_runtime_get_sync hasn't been called yet) - no 'active' children (no zynqmp-dp-snd-xx node under dpsub node) - no other device in the same power domain (dpdma node has no "power-domains = <&zynqmp_firmware PD_DP>" property) So there is a scenario as below: 1) DP device enters suspend state <- call zynqmp_gpd_power_off 2) zynqmp_disp_crtc_setup_clock <- configurate register VPLL_FRAC_CFG 3) pm_runtime_get_sync <- call zynqmp_gpd_power_on and clear previous VPLL_FRAC_CFG configuration 4) clk_prepare_enable(disp->pclk) <- enable failed since VPLL_FRAC_CFG configuration is corrupted From above, we can see that pm_runtime_get_sync may clear register VPLL_FRAC_CFG configuration and result the failure of clk enabling. Putting pm_runtime_get_sync at the very beginning of the function zynqmp_disp_crtc_atomic_enable can resolve this issue. Signed-off-by: Quanyang Wang <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-08drm/vkms: Use offset-adjusted shadow-plane mappings and outputThomas Zimmermann4-3/+4
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in vkms. Also provide use the offset-adjusted data address for the writeback job's output buffers. Output framebuffers with non-zero offsets now have their content written to the correct location. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/vbox: Use offset-adjusted shadow-plane mappingsThomas Zimmermann1-1/+1
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in vbox. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/udl: Use offset-adjusted shadow-plane mappingThomas Zimmermann1-2/+2
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in udl. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/simpledrm: Use offset-adjusted shadow-plane mappingThomas Zimmermann1-2/+2
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in simpledrm. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/gm12u320: Use offset-adjusted shadow-plane mappingsThomas Zimmermann1-2/+2
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in gm12u320. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/cirrus: Use offset-adjusted shadow-plane mappingsThomas Zimmermann1-2/+2
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in cirrus. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Use offset-adjusted shadow-plane mappingsThomas Zimmermann1-2/+2
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in mgag200. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/hyperv: Use offset-adjusted shadow-plane mappingsThomas Zimmermann1-2/+2
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in hyperv. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/gud: Get offset-adjusted mapping from drm_gem_fb_vmap()Thomas Zimmermann1-2/+3
Pass the data parameter to drm_gem_fb_vmap() to retrieve pointers to the data. This address is different from the mapping addresses for framebuffers with non-zero offsets. Replaces gud's internal computation. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/ast: Use offset-adjusted shadow-plane mappingsThomas Zimmermann1-1/+1
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in ast. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/gem: Provide offset-adjusted framebuffer BO mappingsThomas Zimmermann4-4/+19
Add an additional argument to drm_gem_fb_vmap() to return each BO's mapping adjusted by the respective offset. Update all callers. The newly returned values point to the first byite of the data stored in the framebuffer BOs. Drivers that access the BO data should use it. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Compute PLL values during atomic checkThomas Zimmermann2-18/+22
PLL setup can fail if the display mode's clock is not supported by any PLL configuration. Compute the PLL values during atomic check, so that atomic commits can fail at the appropriate time. If successful, use the values in the atomic-update phase. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Introduce custom CRTC stateThomas Zimmermann2-0/+55
Inherit from struct drm_crtc_state by embeding it and providing the rsp callbacks for simple-kms helpers. No functional changes. The new state struct mgag200_crtc_state will hold PLL values for modeset operations. v2: * move the simple-kms changes into a separate patch (Sam) Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/simple-kms: Support custom CRTC stateThomas Zimmermann1-3/+36
Simple KMS helpers already support custom state for planes. Extend the helpers to support custom CRTC state as well. Drivers can set the reset, duplicate and destroy callbacks for the display pipeline's CRTC state and inherit from struct drm_crtc_state by embedding an instance. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Abstract pixel PLL via struct mgag200_pllThomas Zimmermann4-903/+1019
Move all PLL compute and update functions into mgag200_pll.c. No functional changes to the rsp algorithms. Introduce struct mgag200_pll and mgag200_pll_funcs. The data strutures abstract the details of each revision's PLL. Perform calls to compute and update functionality via function pointers. Init the PLL once as part of the driver initialization. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Declare PLL clock constants static constThomas Zimmermann1-44/+31
Move the PLL constants to the RO data section by declaring them as static const. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Split PLL compute function for G200SE by revThomas Zimmermann1-70/+96
The compute function for G200SE pixel PLLs handles two revisions with different algorithms. Split it accordingly to make it readable. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Split PLL compute functions by device typeThomas Zimmermann1-110/+146
Several PLL functions compute values for different device types. Split them up to make the code more readable. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Store values (not bits) in struct mgag200_pll_valuesThomas Zimmermann1-62/+91
The fields in struct mgag200_pll_values currently hold the bits of each register. Store the PLL values instead and let the PLL-update code figure out the bits for each register. Until now, the compute function either stored plain values or register bits in struct mgag200_pll_values. The rsp update function used the values as-is. This made it very hard to correctly interpret the stored values (e.g., for logging or debugging). With the cleanup, the stored values now have a clear meaning. v2: * add a bit more context in the commit message (Sam) Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Introduce separate variable for PLL S parameterThomas Zimmermann1-20/+16
The S parameter is controls the loop filter bandwidth when programming the PLL. It's currently stored as part of P (i.e., the clock divider.) Add a separate variable for S prepares the PLL code for further refactoring. The value of s is currently 0, so it has not yet an effect on the programming. v2: * add a note on the current value of s to commit message Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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