aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu
AgeCommit message (Collapse)AuthorFilesLines
2020-01-24Merge tag 'amd-drm-fixes-5.5-2020-01-23' of ↵Dave Airlie1-1/+1
git://people.freedesktop.org/~agd5f/linux into drm-fixes amd-drm-fixes-5.5-2020-01-23: amdgpu: - remove the experimental flag from renoir Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-01-24Merge tag 'drm-intel-fixes-2020-01-23' of ↵Dave Airlie4-12/+15
git://anongit.freedesktop.org/drm/drm-intel into drm-fixes - Avoid overflow with huge userptr objects - uAPI fix to correctly handle negative values in engine->uabi_class/instance (cc: stable) Signed-off-by: Dave Airlie <[email protected]> From: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-01-23drm/amdgpu: remove the experimental flag for renoirAlex Deucher1-1/+1
Should work properly with the latest sbios on 5.5 and newer kernels. Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-23Merge tag 'drm-misc-fixes-2020-01-22-1' of ↵Dave Airlie10-134/+380
git://anongit.freedesktop.org/drm/drm-misc into drm-fixes -mst: Fix SST branch device handling (Wayne) -panfrost: Fix mapping of globally visible BO's (Boris) Cc: Wayne Lin <[email protected]> CC: Boris Brezillon <[email protected]> Signed-off-by: Dave Airlie <[email protected]> From: Sean Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20200122213725.GA22099@art_vandelay
2020-01-23Merge branch 'linux-5.6' of git://github.com/skeggsb/linux into drm-nextDave Airlie9-12/+21
Just a couple of fixes to GP10x ACR support after the work, and a (fairly severe if you're running piglit a lot) memory leak fix. Signed-off-by: Dave Airlie <[email protected]> From: Ben Skeggs <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/ <CACAvsv51mZaRuT5R=VhbKSTPzd15L4FbDiPQ+wsF+C23c_fOAQ@mail.gmail.com
2020-01-23Merge tag 'exynos-drm-next-for-v5.6' of ↵Dave Airlie8-34/+34
git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next Change Exynos DRM specific callback function names - it changes enable and disable callback functions names of struct exynos_drm_crtc_ops to atomic_enable and atomic_disable for consistency. Modify "EXYNOS" prefix to "Exynos" - "Exynos" name is a regular trademarked name promoted by its manufacturer, Samsung Electronics Co., Ltd.. This patch corrects the name. Signed-off-by: Dave Airlie <[email protected]> From: Inki Dae <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-01-23Merge branch 'vmwgfx-next' of git://people.freedesktop.org/~thomash/linux ↵Dave Airlie7-34/+183
into drm-next vmwgfx updates + new logging uapi https://patchwork.freedesktop.org/patch/349809/ is appropriate userpsace patch. Signed-off-by: Dave Airlie <[email protected]> From: =?UTF-8?q?Thomas=20Hellstr=C3=B6m=20=28VMware=29?= Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-01-23drm/nouveau: fix build error without CONFIG_IOMMU_APIChen Zhou1-0/+1
If CONFIG_IOMMU_API is n, build fails: vers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c:37:9: error: implicit declaration of function dev_iommu_fwspec_get; did you mean iommu_fwspec_free? [-Werror=implicit-function-declaration] spec = dev_iommu_fwspec_get(device->dev); ^~~~~~~~~~~~~~~~~~~~ iommu_fwspec_free drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c:37:7: warning: assignment makes pointer from integer without a cast [-Wint-conversion] spec = dev_iommu_fwspec_get(device->dev); ^ drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c:39:17: error: struct iommu_fwspec has no member named ids u32 sid = spec->ids[0] & 0xffff; Seletc IOMMU_API under config DRM_NOUVEAU to fix this. Reported-by: Hulk Robot <[email protected]> Signed-off-by: Chen Zhou <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-01-23drm/nouveau/kms/nv04: remove set but not used variable 'width'YueHaibing1-2/+1
drivers/gpu/drm/nouveau/dispnv04/arb.c: In function nv04_calc_arb: drivers/gpu/drm/nouveau/dispnv04/arb.c:56:21: warning: variable width set but not used [-Wunused-but-set-variable] 'width' is never used, so remove it. Reported-by: Hulk Robot <[email protected]> Signed-off-by: YueHaibing <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-01-23drm/nouveau/kms/nv50: remove set but not unused variable 'nv_connector'YueHaibing1-2/+0
drivers/gpu/drm/nouveau/dispnv50/disp.c: In function nv50_pior_enable: drivers/gpu/drm/nouveau/dispnv50/disp.c:1672:28: warning: variable nv_connector set but not used [-Wunused-but-set-variable] commit ac2d9275f371 ("drm/nouveau/kms/nv50-: Store the bpc we're using in nv50_head_atom") left behind this. Reported-by: Hulk Robot <[email protected]> Signed-off-by: YueHaibing <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-01-23drm/nouveau/mmu: fix comptag memory leakBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-23drm/nouveau/gr/gp10b: Use gp100_grctx and gp100_gr_zbcThierry Reding3-3/+4
gp10b doesn't have all the registers that gp102_gr_zbc wants to access, which causes IBUS MMIO faults to occur. Avoid this by using the gp100 variants of grctx and gr_zbc. Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-01-23drm/nouveau/pmu/gm20b,gp10b: Fix Falcon bootstrappingThierry Reding2-4/+14
The low-level Falcon bootstrapping callbacks are expected to return 0 on success or a negative error code on failure. However, the implementation on Tegra returns the ID or mask of the Falcons that were bootstrapped on success, thus breaking the calling code, which treats this as failure. Fix this by making sure we only return 0 or a negative error code, just like the code for discrete GPUs does. Fixes: 86ce2a71539c ("drm/nouveau/flcn/cmdq: move command generation to subdevs") Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-01-22drm/amd/display: use odm combine for YCbCr420 timing with h_active greater ↵Wenjing Liu3-22/+45
than 4096 [why] FMT has limitation to support YCbCr420 with h_active greater than 4096. [how] Use odm combine to overcome the limitation. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: init hw i2c speedLewis Huang2-9/+1
[Why] Driver didn't init hw i2c speed cause hdcp hw cannot send command, because the default value of speed register is 0x2. [How] Restore the default speed when release i2c engine Signed-off-by: Lewis Huang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: changed max_downscale_src_width to 4096.Isabel Zhang1-1/+1
[Why] MPO isn't enabled on some 4k videos due to video source width is 4096 and the current limit is 3840. [How] Changed the limit to 4096. Signed-off-by: Isabel Zhang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: support VSC SDP update on video test pattern requestWenjing Liu1-8/+3
[why] MSA will be deprecated in the future. Need to support VSC during DP test automation. [how] Do not disable VSC during DP test automation. TODO - need to add VSC update on DM side on test request. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: Check hw_init state when determining if DMCUB is initializedNicholas Kazlauskas1-0/+3
[Why] CW2 may already be programmed when coming back from S4. In this case we want to unconditionally replace whatever DMCUB version is currently enabled with the latest. [How] Check the hw_init flag to know whether or not we've previously executed the initliazed routine. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: Reset inbox rptr/wptr when resetting DMCUBNicholas Kazlauskas1-2/+2
[Why] These logically make sense more to be set after the DMCUB has been reset rather than when we setup the inbox. [How] Move them into the reset callback. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: Call ATOM_INIT instead of ATOM_ENABLE for DMCUBNicholas Kazlauskas1-0/+4
[Why] DMCUB command table doesn't support ATOM_ENABLE/ATOM_DISABLE anymore so we never end up calling the DCN init path in DMCUB. [How] Map ATOM_ENABLE to ATOM_INIT only for DMCUB command table offloading. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: Add hardware reset interface for DMUB serviceNicholas Kazlauskas2-0/+31
[Why] We'll need this to perform a clean shutdown before unloading the driver. [How] It will call reset internally and set hw_init to false. It won't do anything if the hardware isn't initialized. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: Fix update type for multiple planesRoman Li1-30/+34
[Why] determine_update_type_for_commit() uses pointers to single instance of local variable to fill scaling/color info for all planes updates. This is a bug, that leads to incorrect update type for commit in case of multiple planes per crtc. Each plane should refer to separate scaling/color data. [How] Use arrays for plane properties. Bundle all properties into a single structure to simplify memory allocation. Signed-off-by: Roman Li <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: fix rotation_angle to use enum valuesBrandon Syu1-6/+6
[Why] Hardcoded fixed values are not proper. [How] Use enum values instead of fixed numbers. Signed-off-by: Brandon Syu <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: 3.2.69Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: Refine i2c frequency calculating sequenceLewis Huang1-49/+19
[Why] In HG mode, vbios didn't call DispController_Init to program NV1x XTAL_REF_DIV value when ASIC_INIT, but driver read XTAL_REF_DIV to calculate i2c reference frequency. it cause i2c frequency change from 100kHz to 200kHz. [How] remove get_speed function and calculate reference frequency at set_speed functiton. Signed-off-by: Lewis Huang <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: Refactor to remove diags specific rgam funcAnthony Koo2-182/+129
[Why] It has duplicate code for building regamma curve [How] Remove the duplicate code and use the same function for building regamma Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Reviewed-by: Krunoslav Kovac <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: Fix DML dummyinteger types mismatchJerry (Fangzhi) Zuo1-2/+2
[Why] The types for dummyinteger1 and dummyinteger2 are unsigned as part of the DML spec. They should not be long. [How] Make them unsigned int instead of long. Signed-off-by: Jerry (Fangzhi) Zuo <[email protected]> Reviewed-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: Do DMCUB hw_init before DCNicholas Kazlauskas1-2/+2
[Why] For DMCUB enabled hardware DC has a dependency on DMCUB already being running. Command table offloading will fail on first modeset if DMCUB isn't initialized first. [How] Perform DMCUB hardware initialization before DC. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: Fixed comment stylingHaiyi Zhou1-1/+1
Switched to C-style comments for consistency Signed-off-by: Haiyi Zhou <[email protected]> Reviewed-by: Reza Amini <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: check pipe_ctx is split pipe or notPaul Hsieh1-2/+15
[Why] Driver use pipe_ctx to reallocate payload may cause allocate payload twice on same sink with split pipe. [How] Drvier must to check pipe_ctx is split pipe or not to avoid reallocate payload twice on same sink. Signed-off-by: Paul Hsieh <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: Fallback to DMCUB when command table is missingNicholas Kazlauskas1-4/+70
[Why] If the command table isn't available then we can fallback to DMCUB offloading if it's enabled and available. [How] Instead of assigning NULL for supported command table functions we can fallback to the DMCUB when it's available. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Wesley Chalmers <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: Get fb base and fb offset for DMUB from registersNicholas Kazlauskas3-4/+27
[Why] Under some hardware initialization sequences the fb base/fb offset provided can be zero or hardwareinit can happen too late. We want to ensure that we always have the correct fb_base/fb_offset when performing DMCUB hardware initialization so we can do DMCUB command table offloading during first dc hardware init. [How] Read from the DCN registers. VBIOS already filled these in for us. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Wesley Chalmers <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: Add debug option to disable DSC supportWenjing Liu2-1/+3
[how] Empty dsc enc caps when debug option is set to disable DSC. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: Do not send training pattern if VS DifferentSung Lee1-1/+1
[Why] The DP 1.4a Spec requires that training pattern only under certain specific conditions. Currently driver will re-send training pattern every time voltage swing value changes, but that should not be the case. [How] Do not re-send training pattern every time VS values are different. Only send it on the first iteration. Signed-off-by: Sung Lee <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Abdoulaye Berthe <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amd/display: update MSA and VSC SDP on video test pattern requestWenjing Liu1-1/+36
[why] On video test pattern request we need to update MSA and VSC so it will match the requested test pattern dynamic range field. [how] Update dynamic range field in MSA and disable VSC as updating VSC info packet is complicated and not required for test pattern purpose. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: individualize fence allocation per entityNirmoy Das2-18/+27
Allocate fences for each entity and remove ctx->fences reference as fences should be bound to amdgpu_ctx_entity instead amdgpu_ctx. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22Revert "drm/amdgpu: fix modprobe failure of the secondary GPU when GDDR6 ↵Tianci.Yin2-31/+1
training enabled(V5)" This reverts commit 9e441478623fd913d4340654682b19f0c24e629d. The patch will be replaced with a better solution, revert it. Reviewed-by: Christian König <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: fix VRAM partially encroached issue in GDDR6 memory training(V2)Tianci.Yin2-3/+35
[why] In GDDR6 BIST training, a certain mount of bottom VRAM will be encroached by UMC, that causes problems(like GTT corrupted and page fault observed). [how] Saving the content of this bottom VRAM to system memory before training, and restoring it after training to avoid VRAM corruption. Acked-by: Christian König <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: remove unnecessary conversion to boolNirmoy Das25-50/+50
Better clean that up before some automation starts to complain about it Signed-off-by: Nirmoy Das <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: add RAS support for the gfx block of ArcturusDennis Li4-1/+1039
Implement functions to do the RAS error injection and query EDC counter. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: add EDC counter registers of gc for ArcturusDennis Li2-0/+1012
add reg headers to gc includes v2: remove unused registers and fields in this patch set Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: abstract EDC counter clear to a separated functionDennis Li1-35/+77
1. Add IP prefix for the IP related codes. 2. Refactor the code to clear EDC counter. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: refine the security check for RAS functionsDennis Li1-2/+2
To avoid calling RAS related functions when RAS feature isn't supported in hardware. Change to check supported features, instead of checking asic type. v2: reuse amdgpu_ras_is_supported function, instead of introducing a new flag for hardware ras feature. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: enable RAS feature for more mmhub sub-blocks of AcrturusDennis Li1-6/+695
Compared with Vg20, the size of mmhub range is changed from 2 to 8. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: update mmhub 9.4.1 header files for AcrturusDennis Li1-0/+128
Add mask & shift definition of MAM_D(0~3)MEM for all mmhub ranges. Signed-off-by: Dennis Li <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: read gfx register using RREG32_KIQ macrochen gong1-5/+5
Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to hang when GPU is in "gfxoff" state. I do a uniform substitution here. Signed-off-by: chen gong <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: add kiq version interface for RREG32/WREG32chen gong2-2/+6
Reading some registers by mmio will result in hang when GPU is in "gfxoff" state.This problem can be solved by GPU in "ring command packages" way. Signed-off-by: chen gong <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: provide a generic function interface for reading/writing ↵chen gong8-104/+108
register by KIQ Move amdgpu_virt_kiq_rreg/amdgpu_virt_kiq_wreg function to amdgpu_gfx.c, and rename them to amdgpu_kiq_rreg/amdgpu_kiq_wreg.Make it generic and flexible. Signed-off-by: chen gong <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: added support to get mGPU DRAM baseJohn Clements5-1/+92
resolves issue with RAS error injection in mGPU configuration Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: modify packet size for pm4 flush tlbsAlex Sierra4-4/+6
[Why] PM4 packet size for flush message was oversized. [How] Packet size adjusted to allocate flush + fence packets. Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.