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2020-05-22drm/nouveau/kms/nv50-: Probe SOR and PIOR caps for DP interlacing supportLyude Paul15-3/+118
Right now, we make the mistake of allowing interlacing on all connectors. Nvidia hardware does not always support interlacing with DP though, so we need to make sure that we don't allow interlaced modes to be set in such situations as otherwise we'll end up accidentally hanging the display HW. This fixes some hangs with Turing, which would be caused by attempting to set an interlaced mode on hardware that doesn't support it. This patch likely fixes other hardware hanging in the same way as well. Note that we say we probe PIOR caps, but they don't actually have any interlacing caps. So, the get_caps() function for PIORs just sets interlacing support to true. Changes since v1: * Actually probe caps correctly this time, both on EVO and NVDisplay. Changes since v2: * Fix probing for < GF119 * Use vfunc table, in prep for adding more caps in the future. Signed-off-by: Lyude Paul <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms/nv50-: Initialize core channel in nouveau_display_create()Lyude Paul1-1/+4
We'll need the core channel initialized and ready by the time that we start creating modesetting objects, so that we can call the NV507D_GET_CAPABILITIES method to make the hardware expose it's modesetting capabilities for later probing. So, when loading the driver prepare the core channel from within nouveau_display_create(). Everywhere else, we initialize the core channel during resume. Signed-off-by: Lyude Paul <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/disp/hda/gv100-: NV_PDISP_SF_AUDIO_CNTRL0 register movedBen Skeggs5-2/+35
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/disp/hda/gf119-: select HDA device entry based on bound headBen Skeggs1-3/+4
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/disp/hda/gf119-: add HAL for programming device entry in SFBen Skeggs8-2/+17
Register has moved on GV100. Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/disp/hda/gt215-: pass head to nvkm_ior.hda.eld()Ben Skeggs4-6/+6
We're going to use the bound head to select HDA device entry. Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/disp/nv50-: increase timeout on pio channel free() pollingBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms: Fix regression by audio component transitionTakashi Iwai1-6/+10
Since the commit 742db30c4ee6 ("drm/nouveau: Add HD-audio component notifier support"), the nouveau driver notifies and pokes the HD-audio HPD and ELD via audio component, but this seems broken. The culprit is the naive assumption that crtc->index corresponds to the HDA pin. Actually this rather corresponds to the MST dev_id (alias "pipe" in the audio component framework) while the actual port number is given from the output ior id number. This patch corrects the assignment of port and dev_id arguments in the audio component ops to recover from the HDMI/DP audio regression. Fixes: 742db30c4ee6 ("drm/nouveau: Add HD-audio component notifier support") BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=207223 Cc: <[email protected]> Signed-off-by: Takashi Iwai <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/device: use regular PRI accessors in chipset detectionBen Skeggs1-18/+13
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/device: detect vGPUsKarol Herbst1-3/+12
Using ENODEV as this prevents probe failed errors in dmesg. v2: move check further down Signed-off-by: Karol Herbst <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/device: detect if changing endianness failedKarol Herbst1-5/+21
v2: relax the checks a little Signed-off-by: Karol Herbst <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/device: rework mmio mapping code to get rid of second mapKarol Herbst1-12/+15
Fixes warnings on GPUs with smaller a smaller mmio region like vGPUs. Signed-off-by: Karol Herbst <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/mmu: Remove unneeded semicolonZheng Bin2-2/+2
Fixes coccicheck warning: drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h:307:2-3: Unneeded semicolon drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c:583:2-3: Unneeded semicolon Reported-by: Hulk Robot <[email protected]> Signed-off-by: Zheng Bin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau: Use generic helper to check _PR3 presenceKai-Heng Feng1-34/+10
Replace nouveau_pr3_present() in favor of a more generic one, pci_pr3_present(). Also the presence of upstream bridge _PR3 doesn't need to go hand in hand with device's _DSM, so check _PR3 before _DSM. Signed-off-by: Kai-Heng Feng <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/acr: Use kmemdup instead of kmalloc and memcpyZou Wei1-8/+4
Fixes coccicheck warning: drivers/gpu/drm/nouveau/nvkm/subdev/acr/hsfw.c:103:23-30: WARNING opportunity for kmemdup drivers/gpu/drm/nouveau/nvkm/subdev/acr/hsfw.c:113:22-29: WARNING opportunity for kmemdup Fixes: 22dcda45a3d1 ("drm/nouveau/acr: implement new subdev to replace "secure boot"") Reported-by: Hulk Robot <[email protected]> Signed-off-by: Zou Wei <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/core/memory: remove redundant assignments to variable retColin Ian King1-1/+1
The variable ret is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/svm: map pages after migrationRalph Campbell4-17/+95
When memory is migrated to the GPU, it is likely to be accessed by GPU code soon afterwards. Instead of waiting for a GPU fault, map the migrated memory into the GPU page tables with the same access permissions as the source CPU page table entries. This preserves copy on write semantics. Signed-off-by: Ralph Campbell <[email protected]> Cc: Christoph Hellwig <[email protected]> Cc: Jason Gunthorpe <[email protected]> Cc: "Jérôme Glisse" <[email protected]> Cc: Ben Skeggs <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/disp/gv100-: expose capabilities classBen Skeggs6-0/+69
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/bios: move ACPI _ROM handlingBen Skeggs3-76/+47
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau: remove open-coded version of remove_conflicting_pci_framebuffers()Ben Skeggs1-28/+3
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/gr/gk20a: move MODULE_FIRMWARE firmware definitionsBen Skeggs2-11/+11
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/ibus: use nvkm_subdev_new_()Ben Skeggs6-30/+6
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/core: add nvkm_subdev_new_() for bare subdevsBen Skeggs2-0/+13
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms: Support NVIDIA format modifiersJames Jones3-9/+104
Allow setting the block layout of a nouveau FB object using DRM format modifiers. When specified, the format modifier block layout and kind overrides the GEM buffer's implicit layout and kind. The specified format modifier is validated against the list of modifiers supported by the target display hardware. v2: Used Tesla family instead of NV50 chipset compare v4: Do not cache kind, tile_mode in nouveau_framebuffer v5: Resolved against nouveau_framebuffer cleanup Signed-off-by: James Jones <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms: Check framebuffer size against boJames Jones1-0/+98
Make sure framebuffer dimensions and tiling parameters will not result in accesses beyond the end of the GEM buffer they are bound to. v3: Return EINVAL when creating FB against BO with unsupported tiling v5: Resolved against nouveau_framebuffer cleanup Signed-off-by: James Jones <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms: Add format mod prop to base/ovly/nvdispJames Jones6-4/+112
Advertise support for the full list of format modifiers supported by each class of NVIDIA desktop GPU display hardware. Stash the array of modifiers in the nouveau_display struct for use when validating userspace framebuffer creation requests, which will be supportd in a subsequent change. Signed-off-by: James Jones <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/acr: ensure falcon providing acr functions is bootstrapped firstBen Skeggs1-0/+5
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms: Remove struct nouveau_framebufferThomas Zimmermann4-38/+28
After its cleanup, struct nouveau_framebuffer is only a wrapper around struct drm_framebuffer. Use the latter directly. Signed-off-by: Thomas Zimmermann <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms: Remove field nvbo from struct nouveau_framebufferThomas Zimmermann7-84/+75
The buffer object stored in nvbo is also available GEM object in obj[0] of struct drm_framebuffer. Therefore remove nvbo in favor obj[0] and replace all references accordingly. This may require an additional cast. With this change we can already replace nouveau_user_framebuffer_destroy() and nouveau_user_framebuffer_create_handle() with generic GEM helpers. Calls to nouveau_framebuffer_new() receive a GEM object. Signed-off-by: Thomas Zimmermann <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms: Move struct nouveau_framebuffer.vma to struct nouveau_fbdevThomas Zimmermann5-14/+14
The vma field of struct nouveau_framebuffer is a special field for the the accelerated fbdev console. Hence there's at most one single instance for the active console. Moving it into struct nouveau_fbdev makes struct nouveau_framebuffer slightly smaller and brings it closer to struct drm_framebuffer. Signed-off-by: Thomas Zimmermann <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms: Remove unused fields from struct nouveau_framebufferThomas Zimmermann1-5/+0
Signed-off-by: Thomas Zimmermann <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau: fix out-of-tree module buildBen Skeggs1-4/+6
The $(srctree) addition a while back busted building the out-of-tree version of the module, and I've been hacking it up ever since. This allows us to work around the issue. Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22Merge tag 'amd-drm-fixes-5.7-2020-05-21' of ↵Dave Airlie18-95/+126
git://people.freedesktop.org/~agd5f/linux into drm-fixes amd-drm-fixes-5.7-2020-05-21: amdgpu: - DP fix - Floating point fix - Fix cursor stutter issue Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-22Merge branch 'etnaviv/fixes' of https://git.pengutronix.de/git/lst/linux ↵Dave Airlie2-2/+4
into drm-fixes two fixes: - memory leak fix when userspace passes a invalid softpin address - off-by-one crashing the kernel in the perfmon domain iteration when the GPU core has both 2D and 3D capabilities Signed-off-by: Dave Airlie <[email protected]> From: Lucas Stach <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-21drm/amdgpu: resize VRAM BAR for CPU access on gfx10Alan Swanson1-4/+10
Try to resize BAR0 to let CPU access all of VRAM on Navi. Syncs code with previous gfx generations from commit d6895ad39f3b39 ("drm/amdgpu: resize VRAM BAR for CPU access v6"). Signed-off-by: Alan Swanson <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-21drm/amdgpu: drop navi pcie bw callbackAlex Deucher1-8/+0
It's not implemented yet so just drop it so the sysfs pcie bw file returns an appropriate error instead of garbage. Reviewed-by: Yong Zhao <[email protected]> Reviewed-By: Kent Russell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-21drm/amdgpu: improve error handling in pcie_bwAlex Deucher1-1/+7
1. Initialize the counters to 0 in case the callback fails to initialize them. 2. The counters don't exist on APUs so return an error for them. 3. Return an error if the callback doesn't exist. Reviewed-by: Yong Zhao <[email protected]> Reviewed-By: Kent Russell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-21drm/amdkfd: fix restore worker race conditionPhilip Yang1-3/+3
In free memory of gpu path, remove bo from validate_list to make sure restore worker don't access the BO any more, then unregister bo MMU interval notifier. Otherwise, the restore worker will crash in the middle of validating BO user pages if MMU interval notifer is gone. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-21drm/amdgpu: off by one in amdgpu_device_attr_create_groups() error handlingDan Carpenter1-2/+1
This loop in the error handling code should start a "i - 1" and end at "i == 0". Currently it starts a "i" and ends at "i == 1". The result is that it removes one attribute that wasn't created yet, and leaks the zeroeth attribute. Fixes: 4e01847c38f7 ("drm/amdgpu: optimize amdgpu device attribute code") Acked-by: Michael J. Ruhl <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-21drm/amdgpu/smu10: Replace one-element array and use struct_size() helperGustavo A. R. Silva2-5/+3
The current codebase makes use of one-element arrays in the following form: struct something { int length; u8 data[1]; }; struct something *instance; instance = kmalloc(sizeof(*instance) + size, GFP_KERNEL); instance->length = size; memcpy(instance->data, source, size); but the preferred mechanism to declare variable-length types such as these ones is a flexible array member[1][2], introduced in C99: struct foo { int stuff; struct boo array[]; }; By making use of the mechanism above, we will get a compiler warning in case the flexible array does not occur last in the structure, which will help us prevent some kind of undefined behavior bugs from being inadvertently introduced[3] to the codebase from now on. So, replace the one-element array with a flexible-array member. Also, make use of the new struct_size() helper to properly calculate the size of struct smu10_voltage_dependency_table. This issue was found with the help of Coccinelle and, audited and fixed _manually_. [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html [2] https://github.com/KSPP/linux/issues/21 [3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour") Acked-by: Christian König <[email protected]> Signed-off-by: Gustavo A. R. Silva <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-21drm/amd/display: Set/Reset avmute when disable/enable streamJinze Xu1-0/+8
[Why] When disconnect fe from be, something such as unstable clock may cause garbage occurs. [How] Send set avmute at the beginning of disable stream and send reset avmute at the end of enable stream. Signed-off-by: Jinze Xu <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Acked-by: Tony Cheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-21drm/amd/display: Fix incorrectly pruned modes with deep colorStylon Wang1-38/+64
[Why] When "max bpc" is set to enable deep color, some modes are removed from the list if they fail validation on max bpc. These modes should be kept if they validates fine with lower bpc. [How] - Retry with lower bpc in mode validation. - Same in atomic commit to apply working bpc, not necessarily max bpc. Signed-off-by: Stylon Wang <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-21drm/amd/display: correct rn NUM_VMIDDmytro Laktyushkin4-9/+9
Save the correct num vmid during resource creation and fix RN gpuvm level from 1 to 16 vmid entries. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-21drm/amd/display: Avoid pipe split when plane is too smallNicholas Kazlauskas2-2/+33
[Why] The minimum plane size we can support in DML is 16x16. If we try to pass a 16x16 plane with dynamic pipe split then validation will fail since it tries to split it into two pipes, each 8x8. Some userspace doesn't check that the commit fails and because the commit fails the old state is retained, resulting in corruption. [How] Add a workaround to avoid pipe split if any plane is 16x16 or smaller. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-21drm/amd/display: Defer cursor lock until after VUPDATENicholas Kazlauskas6-1/+81
[Why] We dropped the delay after changed the cursor functions locking the entire pipe to locking just the CURSOR registers to fix page flip stuttering - this introduced cursor stuttering instead, and an underflow issue. The cursor update can be delayed indefinitely if the cursor update repeatedly happens right around VUPDATE. The underflow issue can happen if we do a viewport update on a pipe on the same frame where a cursor update happens around VUPDATE - the old cursor registers are retained which can be in an invalid position. This can cause a pipe hang and indefinite underflow. [How] The complex, ideal solution to the problem would be a software triple buffering mechanism from the DM layer to program only one cursor update per frame just before VUPDATE. The simple workaround until we have that infrastructure in place is this change - bring back the delay until VUPDATE before locking, but with some corrections to the calculations. This didn't work for all timings before because the calculation for VUPDATE was wrong - it was using the offset from VSTARTUP instead and didn't correctly handle the case where VUPDATE could be in the back porch. Add a new hardware sequencer function to use the existing helper to calculate the real VUPDATE start and VUPDATE end - VUPDATE can last multiple lines after all. Change the udelay to incorporate the width of VUPDATE as well. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-21drm/amd/display: DP training to set properly SCRAMBLING_DISABLEVladimir Stempen1-0/+27
[Why] DP training sequence to set SCRAMBLING_DISABLE bit properly based on training pattern - per DP Spec. [How] Update dpcd_pattern.v1_4.SCRAMBLING_DISABLE with 1 for TPS1, TPS2, TPS3, but not for TPS4. Signed-off-by: Vladimir Stempen <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-21drm/amd/display: Remove dml_common_def fileRodrigo Siqueira11-94/+18
During the rework for removing the FPU issues, I found the following warning: [..] dml_common_defs.o: warning: objtool: dml_round()+0x9: FPU instruction outside of kernel_fpu_{begin,end}() This file has a single function that does not need to be in a specific file. This commit drop dml_common_defs file, and move dml_round function to dml_inline_defs. CC: Christian König <[email protected]> CC: Alexander Deucher <[email protected]> CC: Peter Zijlstra <[email protected]> CC: Tony Cheng <[email protected]> CC: Harry Wentland <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-21drm/amd/display: fix and simplify pipe split logicDmytro Laktyushkin4-91/+94
Current odm/mpc combine logic to detect which pipes need to split logically is flawed leading to incorrect pipe merge/split operations being taken. This change cleans up the logic and fixes the logical errors. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-21drm/amd/display: Minimize DSC resource re-assignmentNikola Cornij3-10/+23
[why] Assigning a different DSC resource than the one previosly used is currently not handled. This causes black screen on mode change when more than one monitor is connected on some ASICs. [how] - Acquire the previously used DSC if available - Make sure re-program is triggered if new DSC is used Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Nikola Cornij <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-21drm/amdgpu: add condition to set MP1 state on gpu resetLikun Gao1-1/+2
Only ras supportted need to set MP1 state to prepare for unload before reloading SMU FW. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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