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2017-08-24drm/ttm: fix missing inc bo_countMonk Liu1-0/+1
Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-08-24drm/amdgpu: set sched_hw_submission higher for KIQ (v3)Alex Deucher1-4/+12
KIQ doesn't really use the GPU scheduler. The base drivers generally use the KIQ ring directly rather than submitting IBs. However, amdgpu_sched_hw_submission (which defaults to 2) limits the number of outstanding fences to 2. KFD uses the KIQ for TLB flushes and the 2 fence limit hurts performance when there are several KFD processes running. v2: move some expressions to one line change KIQ sched_hw_submission to at least 16 v3: bump to 256 Reviewed-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-08-24drm/amdgpu: move default gart size setting into gmc modulesAlex Deucher6-57/+74
Move the asic specific code into the IP modules. Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-08-24drm/amdgpu: refine default gart sizeAlex Deucher2-7/+33
Be more explicit and add comments explaining each case. Also s/gart/GART/ in the parameter string as per Felix' suggestion. Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-08-24drm/amd/powerplay: ACG frequency added in PPTableEvan Quan2-5/+12
Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-08-24drm/amdgpu: discard commands of killed processesChristian König1-4/+19
When a process is killed we shouldn't submit all waiting jobs, but instead clean up as fast as possible. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-08-24drm/amdgpu: fix and cleanup shadow handlingChristian König3-37/+23
Set the shadow flag on the shadow and not the parent, always bind shadow BOs during allocation instead of manually, use the reservation_object wrappers to grab the lock. This fixes a couple of issues with binding the shadow BOs as well as correctly evicting them when memory becomes tight. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-08-24drm/amdgpu: add automatic per asic settings for gart_sizeAlex Deucher4-6/+20
We need a larger gart for asics that do not support GPUVM on all engines (e.g., MM) to make sure we have enough space for all gtt buffers in physical mode. Change the default size based on the asic type. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-08-24drm/amdgpu/gfx8: fix spelling typo in mqd allocationAlex Deucher2-8/+8
Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-08-23drm/amd/powerplay: unhalt mec after loadingEvan Quan1-1/+2
Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-08-23drm/amdgpu/virtual_dce: Virtual display doesn't support disable vblank ↵Emily Deng1-2/+3
immediately For virtual display, it uses software timer to emulate the vsync interrupt, it doesn't have high precision, so doesn't support disable vblank immediately. BUG: SWDEV-129274 Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-08-23drm/amdgpu: Fix huge page updates with CPUFelix Kuehling1-1/+15
Correctly detect system memory mappings when using CPU and don't use huge pages for them. Avoid incorrectly translating a physical page table GPU address when splitting a huge page while mapping system memory. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-08-23drm/sun4i: use of_graph_get_remote_endpoint()Kuninori Morimoto1-1/+1
Now, we can use of_graph_get_remote_endpoint(). Let's use it. Signed-off-by: Kuninori Morimoto <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2017-08-23drm/omap: work-around for omap3 display enableTomi Valkeinen1-17/+30
Seems that on omap3 enabling a crtc without any planes causes a sync lost flood. This only happens on the first enable, and after that it works. This looks like an HW issue and it's unclear why this is happening or how to fix it. This started happening after 897145d0c7010b4e07fa9bc674b1dfb9a2c6fff9 ("drm/omapdrm: Move commit_modeset_enables() before commit_planes()") which, as a work-around, changed omapdrm first to do the modeset enable, and plane set only after that. This WA should be fine on all DSS versions, but apparently OMAP3 DSS is an exception. This patch reverts that work-around for OMAP3 DSS. Signed-off-by: Tomi Valkeinen <[email protected]>
2017-08-23drm/omap: fix i886 work-aroundTomi Valkeinen3-9/+25
7d267f068a8b4944d52e8b0ae4c8fcc1c1c5c5ba ("drm/omap: work-around for errata i886") changed how the PLL dividers and multipliers are calculated. While the new way should work fine for all the PLLs, it breaks omap5 PLLs. The issues seen are rather odd: seemed that the output clock rate is half of what we asked. It is unclear what's causing there issues. As a work-around this patch adds a "errata_i886" flag, which is set only for DRA7's PLLs, and the PLL setup is done according to that flag. Signed-off-by: Tomi Valkeinen <[email protected]> Tested-by: H. Nikolaus Schaller <[email protected]>
2017-08-23drm/omap: fix analog tv-out modecheckTomi Valkeinen1-14/+51
omapdrm rejects all venc (analog tv-out) videomodes, due to somewhat strict checking of the values, making tv-out unusable. We only support two videomodes, one for PAL and one for NTSC, so instead of trying to check every field in the videomode struct, this patch makes the driver check only the pixel clock and the size of the display. Signed-off-by: Tomi Valkeinen <[email protected]>
2017-08-23Merge tag 'gvt-fixes-2017-08-23' of https://github.com/01org/gvt-linux into ↵Jani Nikula1-1/+1
drm-intel-fixes gvt-fixes-2017-08-23 - Fix possible null ptr reference in error path (Fred) Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-08-23drm/i915/gvt: Fix the kernel null pointer errorfred gao1-1/+1
once error happens in shadow_indirect_ctx function, the variable wa_ctx->indirect_ctx.obj is not initialized but accessed, so the kernel null point panic occurs. Fixes: 894cf7d15634 ("drm/i915/gvt: i915_gem_object_create() returns an error pointer") Cc: [email protected] # v4.8+ Signed-off-by: fred gao <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2017-08-22drm/msm/mdp5: mark runtime_pm functions as __maybe_unusedArnd Bergmann1-2/+2
When CONFIG_PM is disabled, we get harmless warnings about unused functions: drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c:1025:12: error: 'mdp5_runtime_resume' defined but not used [-Werror=unused-function] static int mdp5_runtime_resume(struct device *dev) ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c:1015:12: error: 'mdp5_runtime_suspend' defined but not used [-Werror=unused-function] static int mdp5_runtime_suspend(struct device *dev) ^~~~~~~~~~~~~~~~~~~~ This marks both functions as __maybe_unused so the compiler can drop them silently. Fixes: d68fe15b1878 ("drm/msm/mdp5: Use runtime PM get/put API instead of toggling clocks") Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-08-22drm/msm: remove unused variableArnd Bergmann1-1/+0
A cleanup left behind an unused variable that we have to remove in order to avoid this harmless warning: drivers/gpu/drm/msm/adreno/a5xx_gpu.c: In function 'a5xx_zap_shader_init': drivers/gpu/drm/msm/adreno/a5xx_gpu.c:493:19: error: unused variable 'a5xx_gpu' [-Werror=unused-variable] Fixes: 8d6f08272b6f ("drm/msm: Remove uneeded platform dev members") Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-08-22drm/msm/mdp5: make helper function staticRob Clark1-1/+1
Not needed outside of mdp5_crtc.c. Signed-off-by: Rob Clark <[email protected]>
2017-08-22drm/msm: make msm_framebuffer_init() staticRob Clark2-3/+3
Only needed in msm_fb.c so don't export it. Signed-off-by: Rob Clark <[email protected]>
2017-08-22drm/msm: add helper to allocate stolen fbRob Clark3-28/+50
We'll later want to re-use this for state-readback when bootloader enables display, so that we can create an fb for the initial plane->state->fb. Signed-off-by: Rob Clark <[email protected]>
2017-08-22drm/msm: don't track fbdev's gem object separatelyRob Clark1-15/+19
The drm_framebuffer is refcnt'd these days and will unref the underlying bo as needed. So we can simplify a little. Signed-off-by: Rob Clark <[email protected]>
2017-08-22drm/msm: add modeset module paramRob Clark1-0/+7
At least for debugging it is nice to have an easy way to force the driver not to load. Signed-off-by: Rob Clark <[email protected]>
2017-08-22drm/msm/mdp5: add tracking for clk enable-countRob Clark2-0/+9
Accessing registers for an unclocked block is an insta-reboot on snapdragon devices. So add a bit of logic to track the enable_count so we can WARN_ON() unclocked register writes. This makes it much easier to track down mistakes. Signed-off-by: Rob Clark <[email protected]>
2017-08-22drm/msm: remove unused defineRob Clark1-2/+0
Signed-off-by: Rob Clark <[email protected]>
2017-08-22drm/msm: Add a helper function for in-kernel buffer allocationsJordan Crouse6-54/+72
Nearly all of the buffer allocations for kernel allocate an buffer object, virtual address and GPU iova at the same time. Make a helper function to handle the details. Signed-off-by: Jordan Crouse <[email protected]> [dropped msm_fbdev conversion to new helper, since it interferes with display-handover work, where we want to separate allocation and mapping] Signed-off-by: Rob Clark <[email protected]>
2017-08-22drm/msm: Attach the GPU MMU when it is createdJordan Crouse3-55/+62
Currently the GPU MMU is attached in the adreno_gpu code but as more and more of the GPU initialization moves to the generic GPU path we have a need to map and use GPU memory earlier and earlier. There isn't any reason to defer attaching the MMU until later so attach it right after the address space is created so it can be used immediately. Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2017-08-22drm: Release driver tracking before making the object available againChris Wilson1-3/+3
This is the same bug as we fixed in commit f6cd7daecff5 ("drm: Release driver references to handle before making it available again"), but now the exposure is via the PRIME lookup tables. If we remove the object/handle from the PRIME lut, then a new request for the same object/fd will generate a new handle, thus for a short window that object is known to userspace by two different handles. Fix this by releasing the driver tracking before PRIME. Fixes: 0ff926c7d4f0 ("drm/prime: add exported buffers to current fprivs imported buffer list (v2)") Signed-off-by: Chris Wilson <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Rob Clark <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: Thierry Reding <[email protected]> Cc: [email protected] Reviewed-by: Daniel Vetter <[email protected]> Signed-off-by: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-08-22drm/nouveau/kms/nv50: perform null check on msto[i] rathern than mstoColin Ian King1-1/+1
The null check on the array msto is incorrect since msto is never null. The null check should be instead on msto[i] since this is being dereferenced in the call to drm_mode_connector_attach_encoder. Thanks to Emil Velikov for pointing out the mistake in my original fix and for suggesting the correct fix. Detected by CoverityScan, CID#1375915 ("Array compared against 0") Fixes: f479c0ba4a17 ("drm/nouveau/kms/nv50: initial support for DP 1.2 multi-stream") Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/pci/msi: disable MSI on big-endian platforms by defaultIlia Mirkin1-0/+4
It appears that MSI does not work on either G5 PPC nor on a E5500-based platform, where other hardware is reported to work fine with MSI. Both tests were conducted with NV4x hardware, so perhaps other (or even this) hardware can be made to work. It's still possible to force-enable with config=NvMSI=1 on load. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected] Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau: silence suspend/resume debugging messagesBen Skeggs1-11/+11
These are particularly annoying on Optimus systems where these paths can be called regularly. Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/kms/nv04-nv4x: fix exposed format listIlia Mirkin1-1/+35
drm_crtc_init exposes the XRGB8888 and ARGB8888 formats. In actuality, ARGB8888's 32-bit depth messes up some formulas that weren't meant for it, and the alpha is fairly meaningless for the primary plane. The modesetting logic appears to be fully prepared for RGB565 as well as XRGB1555 however, as tested with modetest. Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/kms/nv10-nv40: add NV21 support to overlayIlia Mirkin1-3/+6
Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/kms/nv04-nv40: improve overlay error detection, fix pitch settingIlia Mirkin1-28/+34
We were previously setting the pitch based on a perfectly packed buffer. This does not necessarily happen. Either modetest started generating such buffers recently, or earlier testing only happened with well-picked overlay sizes. While we're at it, beef up and refactor the error state detection. Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/kms/nv04-nv40: prevent undisplayable framebuffers from creationIlia Mirkin1-0/+21
Pre-nv50 YUV overlays have stringent requirements for working with the internal machinery. Instead of rejecting these at update_plane time, we should instead prevent the framebuffers from being created in the first place. Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/mpeg: print more debug info when rejecting dma objectsIlia Mirkin2-2/+12
Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Tobias Klausmann <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/fb/gf100-: zero mmu debug buffersBen Skeggs1-2/+2
These are used for accesses to sparse mappings, and we want reads of such mappings to return 0. Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/bar/gf100: add config option to limit BAR2 to 16MiBBen Skeggs2-0/+7
Useful for testing, and for the userspace build where we can't kick a framebuffer driver off the device. Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22initial support (display-only) for GP108Ilia Mirkin1-0/+30
Forked from GP107 implementation. Secboot/gr left out as we don't have signed blobs from NVIDIA in linux-firmware. (Ben): Was unable to mmiotrace the binary driver for unknown reasons, so not able to 100% confirm that no other changes from GP107 are needed. Quick testing shows it seems to work well enough for display. Due to NVIDIA dragging their heels on getting signed firmware to us, this is the best we can do for now. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101601 Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/falcon: use a more reasonable msgqueue timeout valueBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/disp: Silence DCB warnings.Rosen Penev4-0/+7
Most of these errors seem to be WFD related. Official documentation says dcb type 8 is reserved. It's probably used for WFD. Silence the warning in either case. Connector type 70 is stated to be a virtual connector for WiFi display. Since we know this, don't warn that we don't. Signed-off by: Rosen Penev <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/bios: Demote missing fp table message to NV_DEBUG.Rosen Penev1-5/+2
This warning seems to pop up mainly in laptop cards. Silence it as it is expected behavior. Signed-off by: Rosen Penev <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/pmu/gt215-: abstract detection of whether reset is neededBen Skeggs13-1/+32
GT215, GF100-GP100, and GP10x are all different. Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/pmu/gt215: fix resetBen Skeggs10-13/+24
The NV_PMC_ENABLE bit for PMU did not appear until GF100, and some other unknown register needs to be poked instead. Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/mc/gf100: add pmu to reset maskBen Skeggs1-0/+1
An upcoming commit will replace direct NV_PMC register bashing from PMU with a call to the proper function. Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/disp/gf119-: avoid creating non-existent headsIlia Mirkin2-3/+8
We assume that each board has 4 heads for GF119+. However this is not necessarily true - in the case of a GP108 board, the register indicated that there were only 2. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101601 Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/therm/gm200: AddedKarol Herbst6-1/+46
This allows temperature readouts on maxwell2 GPUs. Signed-off-by: Karol Herbst <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-08-22drm/nouveau/therm: fix spelling mistake on array thresoldsColin Ian King1-3/+3
Array thresolds should be named thresholds, rename it. Also make it static static const char * const Signed-off-by: Colin Ian King <[email protected]> Reviewed-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
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