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2022-09-21drm/amd/display: Only consider pixle rate div policy for DCN32+Alvin Lee3-17/+2
[Why and How] - Only consider pixel rate div policy for DCN32+ Reviewed-by: Martin Leung <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-21drm/amd/display: Port DCN30 420 logic to DCN32Chris Park3-0/+29
[Why] 420 modes are limited by FMT buffer width of 4096 which requires multi-pipe support in form of ODM combine. If 420 modes have greater HActive than 4096, the DML logic should accomodate whether it should be rejected, or ODM combine 2:1 or 4:1 is triggered accordingly. [How] FMT Buffer limit of 4096 in DCN32. Force ODM combine depending on HActive and FMT Buffer limit. Reject modes if TMDS 420 and above 4096. Acked-by: Wayne Lin <[email protected]> Signed-off-by: Chris Park <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-21drm/amdgpu: Update PTE flags with TF enabledMukul Joshi2-4/+6
This patch updates the PTE flags when translate further (TF) is enabled: - With translate_further enabled, invalid PTEs can be 0. Reading consecutive invalid PTEs as 0 is considered a fault. To prevent this, ensure invalid PTEs have at least 1 bit set. - The current invalid PTE flags settings to translate a retry fault into a no-retry fault, doesn't work with TF enabled. As a result, update invalid PTE flags settings which works for both TF enabled and disabled case. Fixes: 352e683b72e79d ("drm/amdgpu: Enable translate_further to extend UTCL2 reach") Reviewed-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Mukul Joshi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-20drm/i915/gem: Really move i915_gem_context.link under ref protectionChris Wilson1-4/+4
i915_perf assumes that it can use the i915_gem_context reference to protect its i915->gem.contexts.list iteration. However, this requires that we do not remove the context from the list until after we drop the final reference and release the struct. If, as currently, we remove the context from the list during context_close(), the link.next pointer may be poisoned while we are holding the context reference and cause a GPF: [ 4070.573157] i915 0000:00:02.0: [drm:i915_perf_open_ioctl [i915]] filtering on ctx_id=0x1fffff ctx_id_mask=0x1fffff [ 4070.574881] general protection fault, probably for non-canonical address 0xdead000000000100: 0000 [#1] PREEMPT SMP [ 4070.574897] CPU: 1 PID: 284392 Comm: amd_performance Tainted: G E 5.17.9 #180 [ 4070.574903] Hardware name: Intel Corporation NUC7i5BNK/NUC7i5BNB, BIOS BNKBL357.86A.0052.2017.0918.1346 09/18/2017 [ 4070.574907] RIP: 0010:oa_configure_all_contexts.isra.0+0x222/0x350 [i915] [ 4070.574982] Code: 08 e8 32 6e 10 e1 4d 8b 6d 50 b8 ff ff ff ff 49 83 ed 50 f0 41 0f c1 04 24 83 f8 01 0f 84 e3 00 00 00 85 c0 0f 8e fa 00 00 00 <49> 8b 45 50 48 8d 70 b0 49 8d 45 50 48 39 44 24 10 0f 85 34 fe ff [ 4070.574990] RSP: 0018:ffffc90002077b78 EFLAGS: 00010202 [ 4070.574995] RAX: 0000000000000002 RBX: 0000000000000002 RCX: 0000000000000000 [ 4070.575000] RDX: 0000000000000001 RSI: ffffc90002077b20 RDI: ffff88810ddc7c68 [ 4070.575004] RBP: 0000000000000001 R08: ffff888103242648 R09: fffffffffffffffc [ 4070.575008] R10: ffffffff82c50bc0 R11: 0000000000025c80 R12: ffff888101bf1860 [ 4070.575012] R13: dead0000000000b0 R14: ffffc90002077c04 R15: ffff88810be5cabc [ 4070.575016] FS: 00007f1ed50c0780(0000) GS:ffff88885ec80000(0000) knlGS:0000000000000000 [ 4070.575021] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 4070.575025] CR2: 00007f1ed5590280 CR3: 000000010ef6f005 CR4: 00000000003706e0 [ 4070.575029] Call Trace: [ 4070.575033] <TASK> [ 4070.575037] lrc_configure_all_contexts+0x13e/0x150 [i915] [ 4070.575103] gen8_enable_metric_set+0x4d/0x90 [i915] [ 4070.575164] i915_perf_open_ioctl+0xbc0/0x1500 [i915] [ 4070.575224] ? asm_common_interrupt+0x1e/0x40 [ 4070.575232] ? i915_oa_init_reg_state+0x110/0x110 [i915] [ 4070.575290] drm_ioctl_kernel+0x85/0x110 [ 4070.575296] ? update_load_avg+0x5f/0x5e0 [ 4070.575302] drm_ioctl+0x1d3/0x370 [ 4070.575307] ? i915_oa_init_reg_state+0x110/0x110 [i915] [ 4070.575382] ? gen8_gt_irq_handler+0x46/0x130 [i915] [ 4070.575445] __x64_sys_ioctl+0x3c4/0x8d0 [ 4070.575451] ? __do_softirq+0xaa/0x1d2 [ 4070.575456] do_syscall_64+0x35/0x80 [ 4070.575461] entry_SYSCALL_64_after_hwframe+0x44/0xae [ 4070.575467] RIP: 0033:0x7f1ed5c10397 [ 4070.575471] Code: 3c 1c e8 1c ff ff ff 85 c0 79 87 49 c7 c4 ff ff ff ff 5b 5d 4c 89 e0 41 5c c3 66 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d a9 da 0d 00 f7 d8 64 89 01 48 [ 4070.575478] RSP: 002b:00007ffd65c8d7a8 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 [ 4070.575484] RAX: ffffffffffffffda RBX: 0000000000000006 RCX: 00007f1ed5c10397 [ 4070.575488] RDX: 00007ffd65c8d7c0 RSI: 0000000040106476 RDI: 0000000000000006 [ 4070.575492] RBP: 00005620972f9c60 R08: 000000000000000a R09: 0000000000000005 [ 4070.575496] R10: 000000000000000d R11: 0000000000000246 R12: 000000000000000a [ 4070.575500] R13: 000000000000000d R14: 0000000000000000 R15: 00007ffd65c8d7c0 [ 4070.575505] </TASK> [ 4070.575507] Modules linked in: nls_ascii(E) nls_cp437(E) vfat(E) fat(E) i915(E) x86_pkg_temp_thermal(E) intel_powerclamp(E) crct10dif_pclmul(E) crc32_pclmul(E) crc32c_intel(E) aesni_intel(E) crypto_simd(E) intel_gtt(E) cryptd(E) ttm(E) rapl(E) intel_cstate(E) drm_kms_helper(E) cfbfillrect(E) syscopyarea(E) cfbimgblt(E) intel_uncore(E) sysfillrect(E) mei_me(E) sysimgblt(E) i2c_i801(E) fb_sys_fops(E) mei(E) intel_pch_thermal(E) i2c_smbus(E) cfbcopyarea(E) video(E) button(E) efivarfs(E) autofs4(E) [ 4070.575549] ---[ end trace 0000000000000000 ]--- v3: fix incorrect syntax of spin_lock() replacing spin_lock_irqsave() v2: irqsave not required in a worker, neither conversion to irq safe elsewhere (Tvrtko), - perf: it's safe to call gen8_configure_context() even if context has been closed, no need to check, - drop unrelated cleanup (Andi, Tvrtko) Reported-by: Mark Janes <[email protected]> Closes: https://gitlab.freedesktop.org/drm/intel/issues/6222 References: a4e7ccdac38e ("drm/i915: Move context management under GEM") Fixes: f8246cf4d9a9 ("drm/i915/gem: Drop free_work for GEM contexts") Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Signed-off-by: Janusz Krzysztofik <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: <[email protected]> # v5.12+ Signed-off-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit ad3aa7c31efa5a09b0dba42e66cfdf77e0db7dc2) Signed-off-by: Rodrigo Vivi <[email protected]>
2022-09-20drm/i915/gem: Flush contexts on driver releaseJanusz Krzysztofik1-1/+2
Due to i915_perf assuming that it can use the i915_gem_context reference to protect its i915->gem.contexts.list iteration, we need to defer removal of the context from the list until last reference to the context is put. However, there is a risk of triggering kernel warning on contexts list not empty at driver release time if we deleagate that task to a worker for i915_gem_context_release_work(), unless that work is flushed first. Unfortunately, it is not flushed on driver release. Fix it. Instead of additionally calling flush_workqueue(), either directly or via a new dedicated wrapper around it, replace last call to i915_gem_drain_freed_objects() with existing i915_gem_drain_workqueue() that performs both tasks. Fixes: 75eefd82581f ("drm/i915: Release i915_gem_context from a worker") Suggested-by: Chris Wilson <[email protected]> Signed-off-by: Janusz Krzysztofik <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Cc: [email protected] # v5.16+ Signed-off-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit 1cec34442408a77ba5396b19725fed2c398005c3) Signed-off-by: Rodrigo Vivi <[email protected]>
2022-09-20drm/hisilicon: Add depends on MMURandy Dunlap1-0/+1
The Kconfig symbol depended on MMU but was dropped by the commit acad3fe650a5 ("drm/hisilicon: Removed the dependency on the mmu") because it already had as a dependency ARM64 that already selects MMU. But later, commit a0f25a6bb319 ("drm/hisilicon/hibmc: Allow to be built if COMPILE_TEST is enabled") allowed the driver to be built for non-ARM64 when COMPILE_TEST is set but that could lead to unmet direct dependencies and linking errors. Prevent a kconfig warning when MMU is not enabled by making DRM_HISI_HIBMC depend on MMU. WARNING: unmet direct dependencies detected for DRM_TTM Depends on [n]: HAS_IOMEM [=y] && DRM [=m] && MMU [=n] Selected by [m]: - DRM_TTM_HELPER [=m] && HAS_IOMEM [=y] && DRM [=m] - DRM_HISI_HIBMC [=m] && HAS_IOMEM [=y] && DRM [=m] && PCI [=y] && (ARM64 || COMPILE_TEST [=y]) Fixes: acad3fe650a5 ("drm/hisilicon: Removed the dependency on the mmu") Signed-off-by: Randy Dunlap <[email protected]> Cc: Gerd Hoffmann <[email protected]> Cc: Thomas Zimmermann <[email protected]> Cc: Xinliang Liu <[email protected]> Cc: Tian Tao <[email protected]> Cc: John Stultz <[email protected]> Cc: Xinwei Kong <[email protected]> Cc: Chen Feng <[email protected]> Cc: Christian Koenig <[email protected]> Cc: Huang Rui <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Reviewed-by: Javier Martinez Canillas <[email protected]> Signed-off-by: Javier Martinez Canillas <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-09-20drm/mgag200: Force 32 bpp on the consoleThomas Zimmermann1-1/+5
G200ER does not seem to support 24 bpp, so force the console to use 32 bpp. The problem got introduced when commit 73f54d5d9682 ("drm/mgag200: Remove special case for G200SE with <2 MiB") changed the preferred color depth from 32 bit to 24 bit. A setting of 24 is the correct color depth, but G200ER doesn't seem to be able to use the respective RGB888 color format. Using 24-bit color with forced 32 bpp works around the problem. Reported-by: Wang Yugui <[email protected]> Signed-off-by: Thomas Zimmermann <[email protected]> Tested-by: Wang Yugui <[email protected]> Reviewed-by: Jocelyn Falempe <[email protected]> Fixes: 73f54d5d9682 ("drm/mgag200: Remove special case for G200SE with <2 MiB") Cc: Thomas Zimmermann <[email protected]> Cc: Jocelyn Falempe <[email protected]> Cc: Dave Airlie <[email protected]> Cc: [email protected] Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-09-19drm/panel: simple: Fix innolux_g121i1_l01 bus_formatHeiko Schocher1-1/+1
innolux_g121i1_l01 sets bpc to 6, so use the corresponding bus format: MEDIA_BUS_FMT_RGB666_1X7X3_SPWG. Fixes: 4ae13e486866 ("drm/panel: simple: Add more properties to Innolux G121I1-L01") Signed-off-by: Heiko Schocher <[email protected]> Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Marek Vasut <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-09-16Merge tag 'drm-fixes-2022-09-16' of git://anongit.freedesktop.org/drm/drmLinus Torvalds59-908/+655
Pull drm fixes from Dave Airlie: "This is the regular drm fixes pull. The i915 and misc fixes are fairly regular, but the amdgpu contains fixes for new hw blocks, the dcn314 specific path hookups and also has a bunch of fixes for clang stack size warnings which are a bit churny but fairly straightforward. This means it looks a little larger than usual. amdgpu: - BACO fixes for some RDNA2 boards - PCI AER fixes uncovered by a core PCI change - Properly hook up dirtyfb helper - RAS fixes for GC 11.x - TMR fix - DCN 3.2.x fixes - DCN 3.1.4 fixes - LLVM DML stack size fixes i915: - Revert a display patch around max DP source rate now that the proper WaEdpLinkRateDataReload is in place - Fix perf limit reasons bit position - Fix unclaimmed mmio registers on suspend flow with GuC - A vma_move_to_active fix for a regression with video decoding - DP DSP fix gma500: - Locking and IRQ fixes meson: - OSD1 display fixes panel-edp: - Fix Innolux timings rockchip: - DP/HDMI fixes" * tag 'drm-fixes-2022-09-16' of git://anongit.freedesktop.org/drm/drm: (42 commits) drm/amdgpu: make sure to init common IP before gmc drm/amdgpu: move nbio sdma_doorbell_range() into sdma code for vega drm/amdgpu: move nbio ih_doorbell_range() into ih code for vega drm/rockchip: Fix return type of cdn_dp_connector_mode_valid drm/amd/display: Mark dml30's UseMinimumDCFCLK() as noinline for stack usage drm/amd/display: Reduce number of arguments of dml31's CalculateFlipSchedule() drm/amd/display: Reduce number of arguments of dml31's CalculateWatermarksAndDRAMSpeedChangeSupport() drm/amd/display: Reduce number of arguments of dml32_CalculatePrefetchSchedule() drm/amd/display: Reduce number of arguments of dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport() drm/amd/display: Refactor SubVP calculation to remove FPU drm/amd/display: Limit user regamma to a valid value drm/amd/display: add workaround for subvp cursor corruption for DCN32/321 drm/amd/display: SW cursor fallback for SubVP drm/amd/display: Round cursor width up for MALL allocation drm/amd/display: Correct dram channel width for dcn314 drm/amd/display: Relax swizzle checks for video non-RGB formats on DCN314 drm/amd/display: Hook up DCN314 specific dml implementation drm/amd/display: Enable dlg and vba compilation for dcn314 drm/amd/display: Fix compilation errors on DCN314 drm/amd/display: Fix divide by zero in DML ...
2022-09-16Merge tag 'drm-intel-fixes-2022-09-15' of ↵Dave Airlie6-40/+22
git://anongit.freedesktop.org/drm/drm-intel into drm-fixes - Revert a display patch around max DP source rate now that the proper WaEdpLinkRateDataReload is in place. (Ville) - Fix perf limit reasons bit position. (Ashutosh) - Fix unclaimmed mmio registers on suspend flow with GuC. (Umesh) - A vma_move_to_active fix for a regression with video decoding. (Nirmoy) - DP DSP fix. (Ankit) Signed-off-by: Dave Airlie <[email protected]> From: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-09-16Merge tag 'drm-misc-fixes-2022-09-15' of ↵Dave Airlie14-34/+38
git://anongit.freedesktop.org/drm/drm-misc into drm-fixes Short summary of fixes pull: * gma500: Locking and IRQ fixes * meson: OSD1 display fixes * panel-edp: Fix Innolux timings * rockchip: DP/HDMI fixes Signed-off-by: Dave Airlie <[email protected]> From: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/YyMUpP1w21CPXq+I@linux-uq9g
2022-09-14drm/amdgpu/mes: zero the sdma_hqd_mask of 2nd SDMA engine for SDMA 6.0.1Yifan Zhang1-0/+3
there is only one SDMA engine in SDMA 6.0.1, the sdma_hqd_mask has to be zeroed for the 2nd engine, otherwise MES scheduler will consider 2nd engine exists and map/unmap SDMA queues to the non-existent engine. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-14drm/amdgpu: make sure to init common IP before gmcAlex Deucher1-3/+11
Move common IP init before GMC init so that HDP gets remapped before GMC init which uses it. This fixes the Unsupported Request error reported through AER during driver load. The error happens as a write happens to the remap offset before real remapping is done. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216373 The error was unnoticed before and got visible because of the commit referenced below. This doesn't fix anything in the commit below, rather fixes the issue in amdgpu exposed by the commit. The reference is only to associate this commit with below one so that both go together. Fixes: 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") Acked-by: Christian König <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2022-09-14drm/amdgpu: move nbio sdma_doorbell_range() into sdma code for vegaAlex Deucher2-22/+5
This mirrors what we do for other asics and this way we are sure the sdma doorbell range is properly initialized. There is a comment about the way doorbells on gfx9 work that requires that they are initialized for other IPs before GFX is initialized. However, the statement says that it applies to multimedia as well, but the VCN code currently initializes doorbells after GFX and there are no known issues there. In my testing at least I don't see any problems on SDMA. This is a prerequisite for fixing the Unsupported Request error reported through AER during driver load. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216373 The error was unnoticed before and got visible because of the commit referenced below. This doesn't fix anything in the commit below, rather fixes the issue in amdgpu exposed by the commit. The reference is only to associate this commit with below one so that both go together. Fixes: 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") Acked-by: Christian König <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2022-09-14drm/amdgpu: move nbio ih_doorbell_range() into ih code for vegaAlex Deucher3-3/+8
This mirrors what we do for other asics and this way we are sure the ih doorbell range is properly initialized. There is a comment about the way doorbells on gfx9 work that requires that they are initialized for other IPs before GFX is initialized. In this case IH is initialized before GFX, so there should be no issue. This is a prerequisite for fixing the Unsupported Request error reported through AER during driver load. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216373 The error was unnoticed before and got visible because of the commit referenced below. This doesn't fix anything in the commit below, rather fixes the issue in amdgpu exposed by the commit. The reference is only to associate this commit with below one so that both go together. Fixes: 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") Acked-by: Christian König <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2022-09-14drm/rockchip: Fix return type of cdn_dp_connector_mode_validNathan Huckleberry1-2/+3
The mode_valid field in drm_connector_helper_funcs is expected to be of type: enum drm_mode_status (* mode_valid) (struct drm_connector *connector, struct drm_display_mode *mode); The mismatched return type breaks forward edge kCFI since the underlying function definition does not match the function hook definition. The return type of cdn_dp_connector_mode_valid should be changed from int to enum drm_mode_status. Reported-by: Dan Carpenter <[email protected]> Link: https://github.com/ClangBuiltLinux/linux/issues/1703 Cc: [email protected] Signed-off-by: Nathan Huckleberry <[email protected]> Reviewed-by: Nathan Chancellor <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-09-13drm/amd/display: Mark dml30's UseMinimumDCFCLK() as noinline for stack usageNathan Chancellor1-2/+1
This function consumes a lot of stack space and it blows up the size of dml30_ModeSupportAndSystemConfigurationFull() with clang: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c:3542:6: error: stack frame size (2200) exceeds limit (2048) in 'dml30_ModeSupportAndSystemConfigurationFull' [-Werror,-Wframe-larger-than] void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) ^ 1 error generated. Commit a0f7e7f759cf ("drm/amd/display: fix i386 frame size warning") aimed to address this for i386 but it did not help x86_64. To reduce the amount of stack space that dml30_ModeSupportAndSystemConfigurationFull() uses, mark UseMinimumDCFCLK() as noinline, using the _for_stack variant for documentation. While this will increase the total amount of stack usage between the two functions (1632 and 1304 bytes respectively), it will make sure both stay below the limit of 2048 bytes for these files. The aforementioned change does help reduce UseMinimumDCFCLK()'s stack usage so it should not be reverted in favor of this change. Link: https://github.com/ClangBuiltLinux/linux/issues/1681 Reported-by: "Sudip Mukherjee (Codethink)" <[email protected]> Tested-by: Maíra Canal <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Reduce number of arguments of dml31's CalculateFlipSchedule()Nathan Chancellor1-125/+47
Most of the arguments are identical between the two call sites and they can be accessed through the 'struct vba_vars_st' pointer. This reduces the total amount of stack space that dml31_ModeSupportAndSystemConfigurationFull() uses by 112 bytes with LLVM 16 (1976 -> 1864), helping clear up the following clang warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.c:3908:6: error: stack frame size (2216) exceeds limit (2048) in 'dml31_ModeSupportAndSystemConfigurationFull' [-Werror,-Wframe-larger-than] void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) ^ 1 error generated. Link: https://github.com/ClangBuiltLinux/linux/issues/1681 Reported-by: "Sudip Mukherjee (Codethink)" <[email protected]> Tested-by: Maíra Canal <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Reduce number of arguments of dml31's ↵Nathan Chancellor1-196/+52
CalculateWatermarksAndDRAMSpeedChangeSupport() Most of the arguments are identical between the two call sites and they can be accessed through the 'struct vba_vars_st' pointer. This reduces the total amount of stack space that dml31_ModeSupportAndSystemConfigurationFull() uses by 240 bytes with LLVM 16 (2216 -> 1976), helping clear up the following clang warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.c:3908:6: error: stack frame size (2216) exceeds limit (2048) in 'dml31_ModeSupportAndSystemConfigurationFull' [-Werror,-Wframe-larger-than] void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) ^ 1 error generated. Link: https://github.com/ClangBuiltLinux/linux/issues/1681 Reported-by: "Sudip Mukherjee (Codethink)" <[email protected]> Tested-by: Maíra Canal <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Reduce number of arguments of dml32_CalculatePrefetchSchedule()Nathan Chancellor3-133/+78
Several of the arguments are identical between the two call sites and they can be accessed through the 'struct vba_vars_st' pointer. This reduces the total amount of stack space that dml32_ModeSupportAndSystemConfigurationFull() uses by 208 bytes with LLVM 16 (1936 -> 1728), helping clear up the following clang warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1721:6: error: stack frame size (2152) exceeds limit (2048) in 'dml32_ModeSupportAndSystemConfigurationFull' [-Werror,-Wframe-larger-than] void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) ^ 1 error generated. Additionally, while modifying the arguments to dml32_CalculatePrefetchSchedule(), use 'v' consistently, instead of 'v' mixed with 'mode_lib->vba'. Link: https://github.com/ClangBuiltLinux/linux/issues/1681 Reported-by: "Sudip Mukherjee (Codethink)" <[email protected]> Tested-by: Maíra Canal <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Reduce number of arguments of ↵Nathan Chancellor3-259/+140
dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport() Most of the arguments are identical between the two call sites and they can be accessed through the 'struct vba_vars_st' pointer created at the top of dml32_ModeSupportAndSystemConfigurationFull(). This reduces the total amount of stack space that dml32_ModeSupportAndSystemConfigurationFull() uses by 216 bytes with LLVM 16 (2152 -> 1936), helping clear up the following clang warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1721:6: error: stack frame size (2152) exceeds limit (2048) in 'dml32_ModeSupportAndSystemConfigurationFull' [-Werror,-Wframe-larger-than] void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) ^ 1 error generated. Additionally, while modifying the arguments to dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(), use 'v' consistently, instead of 'v' mixed with 'mode_lib->vba'. Link: https://github.com/ClangBuiltLinux/linux/issues/1681 Reported-by: "Sudip Mukherjee (Codethink)" <[email protected]> Tested-by: Maíra Canal <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Refactor SubVP calculation to remove FPUAlvin Lee1-45/+44
Refactor calculation to remove floating point operations from dmub_srv. To ensure that 32-bit compilation works well, we use the div64 family of macros to do integer division for SubVP-related timing parameters. Cc: Maíra Canal <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Isabella Basso <[email protected]> Cc: Magali Lemes <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Samson Tam <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Co-developed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Co-developed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Limit user regamma to a valid valueYao Wang11-0/+4
[Why] For HDR mode, we get total 512 tf_point and after switching to SDR mode we actually get 400 tf_point and the rest of points(401~512) still use dirty value from HDR mode. We should limit the rest of the points to max value. [How] Limit the value when coordinates_x.x > 1, just like what we do in translate_from_linear_space for other re-gamma build paths. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Krunoslav Kovac <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Yao Wang1 <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: add workaround for subvp cursor corruption for DCN32/321Aurabindo Pillai2-2/+4
[Why&How] Kernel does not have a means to tell the userspace to use software cursor. Due to lack of this functionality, reducing the max cursor size is the only way to ensure that power savings of Subview port feature is utilized for asics that support it. The workaround could be removed after cursor caching is fixed while a subviewport config is active. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: SW cursor fallback for SubVPAlvin Lee4-0/+8
[Description] Leverage SW cursor fall back for SubVP when the cursor is too big. We want to take advantage of being able to fallback to SW cursor when possible because it's not worth it to disable MCLK switching because the cursor is slightly too big. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Round cursor width up for MALL allocationTaimur Hassan2-2/+46
[Why & How] When calculating cursor size for MALL allocation, the cursor width should be the actual width rounded up to 64 alignment. Additionally, the bit depth should vary depending on color format. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Correct dram channel width for dcn314Duncan Ma3-0/+6
[Why] The interpretation of the number of memory channels differ by memory type, and this affects channel width for the DML input. [How] Set dram channel width according to memory type for dcn314. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Duncan Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Relax swizzle checks for video non-RGB formats on DCN314Nicholas Kazlauskas1-3/+1
[Why] HW can support the display swizzle modes for video, and those are preferable over standard or linear for decode use. [How] Remove the check for DCN314. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Hook up DCN314 specific dml implementationNicholas Kazlauskas3-1/+14
[Why & How] Add support for the DML314 functions and hook up DCN314 to use them. This has some necessary additions for calculating Max VSTARTUP for future features, but there's also some changes that we have to make for pixel format/swizzle support. That will come in a following patch to make this transition easier to bisect. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Enable dlg and vba compilation for dcn314Rodrigo Siqueira1-0/+3
We were not using the VBA and DLG files for DCN314, but the next sequence of changes for DCN314 will require those files. This commit adds the necessary files to the Makefile. Cc: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Fix compilation errors on DCN314Rodrigo Siqueira1-4/+5
We have some compilation errors in some DML files from DCN314 that we never noticed because we were not compiling some of the DML files. This commit fixes those syntax errors before we enable the compilation. Cc: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Fix divide by zero in DMLAric Cyr2-18/+16
[why] Incorrectly using MicroTileWidth instead of MacroTileWidth for calculations. [how] Remove all unused references to MicroTile and change them to MacroTile. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Fixing DIG FIFO ErrorLeo Chen1-2/+1
[Why & How] DIG_FIFO_READ_START_LEVEL should only be set to default value (7) by software. Removed all instances of resetting the register to 0 Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Leo Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Update MBLK calculation for SubVPAlvin Lee2-8/+54
[Description] Update MBLK calculation according to hardware doc. For DCC case we were not allocation enough MALL due to an inaccurate MBLK calculation. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Revert "Fallback to SW cursor if SubVP + cursor too big"Aurabindo Pillai1-5/+0
This reverts commit a4f1b04216023ff0f4cd89328b59ee6890248130 since returning false in case of SubVP results in no cursor being visible on desktop as there is no sw cursor fallback path on all platforms. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: Skip reset error status for psp v13_0_0Candice Li1-1/+2
No need to reset error status since only umc ras supported on psp v13_0_0. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: add HDP remap functionality to nbio 7.7Alex Deucher1-0/+9
Was missing before and would have resulted in a write to a non-existant register. Normally APUs don't use HDP, but other asics could use this code and APUs do use the HDP when used in passthrough. Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: change the alignment size of TMR BO to 1MYang Wang2-1/+2
align TMR BO size TO tmr size is not necessary, modify the size to 1M to avoid re-create BO fail when serious VRAM fragmentation. v2: add new macro PSP_TMR_ALIGNMENT for TMR BO alignment size Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: Enable full reset when RAS is supported on gc v11_0_0Candice Li1-0/+1
Enable full reset for RAS supported configuration on gc v11_0_0. v2: simplify the code. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: use dirty framebuffer helperHamza Mahfooz1-0/+2
Currently, we aren't handling DRM_IOCTL_MODE_DIRTYFB. So, use drm_atomic_helper_dirtyfb() as the dirty callback in the amdgpu_fb_funcs struct. Signed-off-by: Hamza Mahfooz <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: Don't enable LTR if not supportedLijo Lazar3-3/+24
As per PCIE Base Spec r4.0 Section 6.18 'Software must not enable LTR in an Endpoint unless the Root Complex and all intermediate Switches indicate support for LTR.' This fixes the Unsupported Request error reported through AER during ASPM enablement. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216455 The error was unnoticed before and got visible because of the commit referenced below. This doesn't fix anything in the commit below, rather fixes the issue in amdgpu exposed by the commit. The reference is only to associate this commit with below one so that both go together. Fixes: 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") Reported-by: Gustaw Smolarczyk <[email protected]> Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Cc: [email protected] Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/pm: disable BACO entry/exit completely on several sienna cichlid cardsGuchun Chen1-0/+11
To avoid hardware intermittent failures. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/mediatek: Fix wrong dither settingsAllen-KH Cheng1-1/+1
The width and height arguments in the cmdq packet for mtk_dither_config() are inverted. We fix the incorrect width and height for dither settings in mtk_dither_config(). Fixes: 73d3724745db ("drm/mediatek: Adjust to the alphabetic order for mediatek-drm") Co-developed-by: Yongqiang Niu <[email protected]> Signed-off-by: Yongqiang Niu <[email protected]> Signed-off-by: Allen-KH Cheng <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Link: https://patchwork.kernel.org/project/linux-mediatek/patch/[email protected]/ Signed-off-by: Chun-Kuang Hu <[email protected]>
2022-09-12Merge tag 'hyperv-fixes-signed-20220912' of ↵Linus Torvalds1-6/+4
git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux Pull hyperv fixes from Wei Liu: - Fix an error handling issue in DRM driver (Christophe JAILLET) - Fix some issues in framebuffer driver (Vitaly Kuznetsov) - Two typo fixes (Jason Wang, Shaomin Deng) - Drop unnecessary casting in kvp tool (Zhou Jie) * tag 'hyperv-fixes-signed-20220912' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux: Drivers: hv: Never allocate anything besides framebuffer from framebuffer memory region Drivers: hv: Always reserve framebuffer region for Gen1 VMs PCI: Move PCI_VENDOR_ID_MICROSOFT/PCI_DEVICE_ID_HYPERV_VIDEO definitions to pci_ids.h tools: hv: kvp: remove unnecessary (void*) conversions Drivers: hv: remove duplicate word in a comment tools: hv: Remove an extraneous "the" drm/hyperv: Fix an error handling path in hyperv_vmbus_probe()
2022-09-12Revert "drm/i915/display: Re-add check for low voltage sku for max dp source ↵Ville Syrjälä1-29/+3
rate" This reverts commit d5929835080a60f9119d024fa42f315913942f76. With the Parade PS8461E MUX workaround (WaEdpLinkRateDataReload) implemented we can get finally rid of the is_low_voltage_sku() check that incorrectly prevents many machines from using the 8.1Gpbs link rate. Cc: Jason A. Donenfeld <[email protected]> Cc: Ankit Nautiyal <[email protected]> Cc: Jani Nikula <[email protected]> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5272 Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6323 Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6205 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Tested-by: Aaron Ma <[email protected]> Tested-by: Jason A. Donenfeld <[email protected]> Reviewed-by: Jani Nikula <[email protected]> (cherry picked from commit 483e3d87a37e804588ac8224aadd20a84593cafd) Signed-off-by: Rodrigo Vivi <[email protected]>
2022-09-12drm/i915/gt: Fix perf limit reasons bit positionsAshutosh Dixit1-8/+8
Perf limit reasons bit positions were off by one. Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces") Cc: [email protected] # v5.18+ Signed-off-by: Ashutosh Dixit <[email protected]> Acked-by: Andi Shyti <[email protected]> Reviewed-by: Sujaritha Sundaresan <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Joonas Lahtinen <[email protected]> (cherry picked from commit 60017f34fc334d1bb25476b0b0996b4073e76c90) Signed-off-by: Rodrigo Vivi <[email protected]>
2022-09-12drm/i915/guc: Cancel GuC engine busyness worker synchronouslyUmesh Nerlige Ramappa1-1/+6
The worker is canceled in gt_park path, but earlier it was assumed that gt_park path cannot sleep and the cancel is asynchronous. This caused a race with suspend flow where the worker runs after suspend and causes an unclaimed register access warning. Cancel the worker synchronously since the gt_park is indeed allowed to sleep. v2: Fix author name and sign-off mismatch Signed-off-by: Umesh Nerlige Ramappa <[email protected]> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4419 Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to pmu") Reviewed-by: Ashutosh Dixit <[email protected]> Signed-off-by: John Harrison <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Joonas Lahtinen <[email protected]> (cherry picked from commit 31335aa8e08be3fe10c50aecd2f11aba77544a78) Signed-off-by: Rodrigo Vivi <[email protected]>
2022-09-12drm/i915: Set correct domains values at _i915_vma_move_to_activeNirmoy Das1-1/+2
Fix regression introduced by commit: "drm/i915: Individualize fences before adding to dma_resv obj" which sets obj->read_domains to 0 for both read and write paths. Also set obj->write_domain to 0 on read path which was removed by the commit. References: https://gitlab.freedesktop.org/drm/intel/-/issues/6639 Fixes: 420a07b841d0 ("drm/i915: Individualize fences before adding to dma_resv obj") Signed-off-by: Nirmoy Das <[email protected]> Cc: <[email protected]> # v5.16+ Cc: Matthew Auld <[email protected]> Cc: Andrzej Hajda <[email protected]> Reviewed-by: Andrzej Hajda <[email protected]> Signed-off-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit 04f7eb3d4582a0a4da67c86e55fda7de2df86d91) Signed-off-by: Rodrigo Vivi <[email protected]>
2022-09-12drm/i915/vdsc: Set VDSC PIC_HEIGHT before using for DP DSCAnkit Nautiyal3-1/+3
Currently, pic_height of vdsc_cfg structure is being used to calculate slice_height, before it is set for DP. So taking out the lines to set pic_height from the helper intel_dp_dsc_compute_params() to individual encoders, and setting pic_height, before it is used to calculate slice_height for DP. Fixes: 5a6d866f8e1b ("drm/i915: Get slice height before computing rc params") Cc: Manasi Navare <[email protected]> Cc: Vandita Kulkarni <[email protected]> Cc: Matt Roper <[email protected]> Signed-off-by: Ankit Nautiyal <[email protected]> Reviewed-by: Vandita Kulkarni <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit e72df53dcb01ec58e0410da353551adf94c8d0f1) Signed-off-by: Rodrigo Vivi <[email protected]>
2022-09-10Merge tag 'drm-intel-fixes-2022-09-08' of ↵Dave Airlie7-11/+94
git://anongit.freedesktop.org/drm/drm-intel into drm-fixes - Fix MIPI sequence block copy from BIOS' table. (Ville) - Fix PCODE min freq setup when GuC's SLPC is in use. (Rodrigo) - Implement Workaround for eDP. (Ville) - Fix has_flat_ccs selection for DG1. (Matt) Signed-off-by: Dave Airlie <[email protected]> From: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]