aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm
AgeCommit message (Collapse)AuthorFilesLines
2018-07-27Merge tag 'exynos-drm-next-for-v4.19' of ↵Dave Airlie24-548/+324
git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next Cleanups - Change g2d driver to component based driver . g2d driver was last customed sub driver so this patch series changes it to component based driver, which also makes gem handling to be more simplify. - Cleanup of Exynos DRM suspend/resume . Register exynos drm core suspend/resume functions to prepare/complete callbacks of dev_pm_ops instead of suspend/resume callbacks to ensure exynos_drm_suspend() is called before any suspend callback from the real devices to avoid some issues on boards with complex pipelines. . Also Add pm_runtime_furce_suspend/resume as SYSTEM_SLEEP_PM_OPS to ensure that resources of each devices will be released for the system PM suspend/resume cycle. - Remove local value not used. Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-07-27Merge branch 'for-upstream/malidp-fixes' of git://linux-arm.org/linux-ld ↵Dave Airlie2-1/+11
into drm-next I have a couple of small patches for malidp to be applied in drm-next. They have arisen from the decision to switch the writeback connectors to always connected. Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-07-27Merge tag 'imx-drm-next-2018-07-20' of ↵Dave Airlie4-10/+10
git://git.pengutronix.de/git/pza/linux into drm-next drm/imx: cleanup and csi improvements - Remove the unused struct imx_drm_crtc and the unused pipes field from imx_drm_device and replace drm_dev_unref with drm_dev_put. - Extend CSI configuration to support RGB888 and BGR888 capture, as well as 16-bit RGB565 capture via a parallel bus. - Add CPMEM support for negative interlace offsets, which is necessary to support writing captured bottom-top interlaced fields to memory with interleaved lines. Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-07-27Merge tag 'imx-drm-fixes-2018-07-20' of ↵Dave Airlie1-3/+6
git://git.pengutronix.de/git/pza/linux into drm-fixes drm/imx: imx-drm ldb and ipu-v3 csi fixes - Disable the LVDS Display Bridge (LDB) on driver bind. This is necessary to guarantee correct LVDS signals in case the bootloader left the LVDS output active. - Remove false positive warning about disabled second LVDS channel in dual-channel mode. In this mode, the second LVDS channel can not be used separately. If the second channel is correctly described as disabled in the device tree, the driver warned about this anyway. - Fix the CSI confiuration to not only enable interlaced capture mode for V4L2_FIELD_SEQ_BT and V4L2_FIELD_SEQ_TB, but also for the V4L2_FIELD_ALTERNATE interlacing mode. Before, it incorrectly tried to capture progressive frames in that case. Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-07-26drm/msm: rework vblank event handling in dpu_crtcRajesh Yadav1-1/+14
The vblank on/off calls were missing in dpu_crtc leading to "driver forgot to call drm_crtc_vblank_off()" warning while entering suspend state. Also handle the state update completion event for a crtc being disabled in current atomic commit. This patch depends on https://www.spinics.net/lists/dri-devel/msg182402.html Signed-off-by: Rajesh Yadav <[email protected]> Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-26drm/msm: Add SDM845 DPU supportJeykumar Sankaran64-15/+31913
SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a top level wrapper consisting of Display Processing Unit (DPU) and display peripheral modules such as Display Serial Interface (DSI) and DisplayPort (DP). MDSS functions essentially as a back-end composition engine. It blends video and graphic images stored in the frame buffers and scans out the composed image to a display sink (over DSI/DP). The following diagram represents hardware blocks for a simple pipeline (two planes are present on a given crtc which is connected to a DSI connector): MDSS +---------------------------------+ | +-----------------------------+ | | | DPU | | | | +--------+ +--------+ | | | | | SSPP | | SSPP | | | | | +----+---+ +----+---+ | | | | | | | | | | +----v-----------v---+ | | | | | Layer Mixer (LM) | | | | | +--------------------+ | | | | +--------------------+ | | | | | PingPong (PP) | | | | | +--------------------+ | | | | +--------------------+ | | | | | INTERFACE (VIDEO) | | | | | +---+----------------+ | | | +------|----------------------+ | | | | | +------|---------------------+ | | | | DISPLAY PERIPHERALS | | | | +---v-+ +-----+ | | | | | DSI | | DP | | | | | +-----+ +-----+ | | | +----------------------------+ | +---------------------------------+ The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs) depends on SoC capabilities. Overview of DPU sub-blocks: --------------------------- * Source Surface Processor (SSPP): Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are capable of performing format conversion, scaling and quality improvement for source surfaces. * Layer Mixer (LM): Blend source surfaces together (in requested zorder) * PingPong (PP): This block controls frame done interrupt output, EOL and EOF generation, overflow/underflow control. * Display interface (INTF): Timing generator and interface connecting the display peripherals. DRM components mapping to DPU architecture: ------------------------------------------ PLANEs maps to SSPPs CRTC maps to LMs Encoder maps to PPs, INTFs Data flow setup: --------------- MDSS hardware can support various data flows (e.g.): - Dual pipe: Output from two LMs combined to single display. - Split display: Output from two LMs connected to two separate interfaces. The hardware capabilities determine the number of concurrent data paths possible. Any control path (i.e. pipeline w/i DPU) can be routed to any of the hardware data paths. A given control path can be triggered, flushed and controlled independently. Changes in v3: - Move msm_media_info.h from uapi to dpu/ subdir - Remove preclose callback dpu (it's handled in core) - Fix kbuild warnings with parent_ops - Remove unused functions from dpu_core_irq - Rename mdss_phys to mdss - Rename mdp_phys address space to mdp - Drop _phys from vbif and regdma binding names Signed-off-by: Abhinav Kumar <[email protected]> Signed-off-by: Archit Taneja <[email protected]> Signed-off-by: Chandan Uddaraju <[email protected]> Signed-off-by: Jeykumar Sankaran <[email protected]> Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rajesh Yadav <[email protected]> Signed-off-by: Sravanthi Kollukuduru <[email protected]> Signed-off-by: Sean Paul <[email protected]> [robclark minor rebase] Signed-off-by: Rob Clark <[email protected]>
2018-07-26drm/msm: Add pm_suspend/resume callbacks to msm_kmsJeykumar Sankaran2-0/+13
Used by the dpu driver for custom suspend/resume. Changes in v3: - None Signed-off-by: Jeykumar Sankaran <[email protected]> [seanpaul split this out of the megapatch] Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-26drm/msm: Add .commit() callback to msm_kms functionsJeykumar Sankaran2-0/+6
Called right before wait_for_commit_done() to perform kickoff for active crtcs. Changes in v3: - None Signed-off-by: Jeykumar Sankaran <[email protected]> [seanpaul split this out of the megapatch] Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-26drm/msm: #define MAX_<OBJECT> in msm_drv.hJeykumar Sankaran1-5/+11
dpu uses these elsewhere in the driver (in addition to increasing MAX_PLANES, that'll come later), so pull them out into #define. Changes in v3: - None Signed-off-by: Jeykumar Sankaran <[email protected]> [seanpaul pulled this out of the dpu megapatch] Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-26drm/msm: Use labels for unwinding in the error pathJeykumar Sankaran1-22/+22
This simplifies cleanup, to make sure nothing drops out in case of error. Changes in v3: - None Signed-off-by: Jeykumar Sankaran <[email protected]> [seanpaul split out of dpu megapatch and renamed labels] Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-26drm/msm: #define MDP version numbersJeykumar Sankaran1-4/+7
Useful for incoming DPU support Changes in v3: - None Signed-off-by: Jeykumar Sankaran <[email protected]> [seanpaul split this from the dpu megapatch] Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-26drm/msm: Clean up dangling atomic_wqSean Paul2-5/+0
I missed this during the atomic conversion Changes in v3: - None Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-26drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factorAbhinav Kumar1-2/+5
Make the pclk_rate u64 to accommodate higher pixel clock rates. Changes in v3: - Converted pclk_rate to u32 (Archit) - Rebase on dsi cleanup set in msm-next Cc: Sibi Sankar <[email protected]> Cc: Archit Taneja <[email protected]> Signed-off-by: Abhinav Kumar <[email protected]> Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-26drm/msm: enable zpos normalizationJeykumar Sankaran1-0/+3
Enable drm core zpos normalization for planes. Changes in v3: - None Signed-off-by: Jeykumar Sankaran <[email protected]> Reviewed-by: Sean Paul <[email protected]> Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-26drm/msm/mdp5: subclass msm_mdss for mdp5Rajesh Yadav3-84/+109
SoCs having mdp5 or dpu have identical tree like device hierarchy where MDSS top level wrapper manages common power resources for all child devices. Subclass msm_mdss so that msm_mdss includes common defines and mdp5/dpu mdss derivations to include any extensions. Add mdss helper interface (msm_mdss_funcs) to msm_mdss base for mdp5/dpu mdss specific implementation calls. This change subclasses msm_mdss for mdp5, dpu specific changes will be done separately. Changes in v3: - Added Archit's R-b Reviewed-by: Archit Taneja <[email protected]> Reviewed-by: Sean Paul <[email protected]> Signed-off-by: Rajesh Yadav <[email protected]> [seanpaul rebased on msm-next and resolved conflicts] Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-26drm/msm: Move wait_for_vblanks into mdp complete_commit() hooksSean Paul3-2/+4
DPU doesn't use this, so push it into the mdp drivers. Changes in v3: - None Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rajesh Yadav <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-26drm/msm/dsi: set encoder mode for DRM bridge explicitlyAbhinav Kumar1-2/+4
Currently, DRM bridge for DPU relies on the default video mode setting to set the encoder mode. Add an explicit call to set the encoder mode for bridges. Changes in v3: - None Reviewed-by: Archit Taneja <[email protected]> Signed-off-by: Abhinav Kumar <[email protected]> Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-26drm/msm/dsi: initialize postdiv_lock before use for 10nm pllRajesh Yadav1-0/+2
postdiv_lock spinlock was used before initialization for 10nm pll. It causes following spin_bug: "BUG: spinlock bad magic on CPU#0". Initialize spinlock before its usage. Changes in v3: - Added Archit's R-b Reviewed-by: Archit Taneja <[email protected]> Signed-off-by: Rajesh Yadav <[email protected]> Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-26drm/msm/dsi: Use one connector for dual DSI modeChandan Uddaraju3-86/+30
Current DSI driver uses two connectors for dual DSI case even though we only have one panel. Fix this by implementing one connector/bridge for dual DSI use case. Use master DSI controllers to register one connector/bridge. Changes in v3: - None Reviewed-by: Archit Taneja <[email protected]> Signed-off-by: Chandan Uddaraju <[email protected]> [seanpaul removed unused local var causing a build warning] Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-26drm/msm/dsi: adjust dsi timing for dual dsi modeChandan Uddaraju4-20/+64
For dual dsi mode, the horizontal timing needs to be divided by half since both the dsi controllers will be driving this panel. Adjust the pixel clock and DSI timing accordingly. Changes in v3: - Added Archit's R-b - Rebase on dsi cleanup set in msm-next Cc: Sibi Sankar <[email protected]> Reviewed-by: Archit Taneja <[email protected]> Signed-off-by: Chandan Uddaraju <[email protected]> Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-25drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.Clint Taylor4-5/+33
On GLK NUC platforms the HDMI retiming buffer needs additional disabled time to correctly sync to a faster incoming signal. When measured on a scope the highspeed lines of the HDMI clock turn off for ~400uS during a normal resolution change. The HDMI retimer on the GLK NUC appears to require at least a full frame of quiet time before a new faster clock can be correctly sync'd. Wait 100ms due to msleep inaccuracies while waiting for a completed frame. Add a quirk to the driver for GLK boards that use ITE66317 HDMI retimers. V2: Add more devices to the quirk list V3: Delay increased to 100ms, check to confirm crtc type is HDMI. V4: crtc type check extended to include _DDI and whitespace fixes v5: Fix white spaces, remove the macro for delay. Revert the crtc type check introduced in v4. Cc: Imre Deak <[email protected]> Cc: <[email protected]> # v4.14+ Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105887 Signed-off-by: Clint Taylor <[email protected]> Tested-by: Daniel Scheller <[email protected]> Signed-off-by: Radhakrishna Sripada <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit 90c3e2198777aaa355b6994a31a79c636c8d4306) Signed-off-by: Rodrigo Vivi <[email protected]>
2018-07-25gpu: drm: amdgpu: Replace mdelay with msleep in cik_pcie_gen3_enable()Jia-Ju Bai1-1/+1
cik_pcie_gen3_enable() is only called by cik_common_hw_init(), which is never called in atomic context. cik_pcie_gen3_enable() calls mdelay() to busily wait, which is not necessary. mdelay() can be replaced with msleep(). This is found by a static analysis tool named DCNS written by myself. Signed-off-by: Jia-Ju Bai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-25drm/amdgpu/gmc9: clarify GPUVM fault error messageAlex Deucher1-1/+1
The address printed is the actual address, not the page. Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-25drm/scheduler: remove sched field from the entityNayan Deshmukh5-17/+16
The scheduler of the entity is decided by the run queue on which it is queued. This patch avoids us the effort required to maintain a sync between rq and sched field when we start shifting entites among different rqs. Signed-off-by: Nayan Deshmukh <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-25drm/scheduler: modify API to avoid redundancyNayan Deshmukh12-35/+27
entity has a scheduler field and we don't need the sched argument in any of the functions where entity is provided. Signed-off-by: Nayan Deshmukh <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-25drm/amdgpu: reduce the number of placements for a BOChristian König2-1/+4
Make struct amdgpu_bo a bit smaller. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-25drm/amdgpu: consistenly name amdgpu_bo_ functionsChristian König10-38/+39
Just rename functions, no functional change. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-25drm/amdgpu: expose only the first UVD instance for nowChristian König2-15/+7
Going to completely rework the context to ring mapping with Nayan's GSoC work, but for now just stopping to expose the second UVD instance should do it. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-25drm/amdgpu: clean up coding style a bitChristian König1-10/+10
No need to bitcast a boolean and even if we should use "!!" instead. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-25drm/vc4: Reset ->{x, y}_scaling[1] when dealing with uniplanar formatsBoris Brezillon1-0/+3
This is needed to ensure ->is_unity is correct when the plane was previously configured to output a multi-planar format with scaling enabled, and is then being reconfigured to output a uniplanar format. Fixes: fc04023fafec ("drm/vc4: Add support for YUV planes.") Cc: <[email protected]> Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-07-25drm/atomic: Initialize variables in drm_atomic_helper_async_check() to make ↵Boris Brezillon1-2/+3
gcc happy drm_atomic_helper_async_check() declares the plane, old_plane_state and new_plane_state variables to iterate over all planes of the atomic state and make sure only one plane is enabled. Unfortunately gcc is not smart enough to figure out that the check on n_planes is enough to guarantee that plane, new_plane_state and old_plane_state are initialized. Explicitly initialize those variables to NULL to make gcc happy. Fixes: fef9df8b5945 ("drm/atomic: initial support for asynchronous plane update") Cc: <[email protected]> Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Sean Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-07-25drm/atomic: Check old_plane_state->crtc in drm_atomic_helper_async_check()Boris Brezillon1-1/+2
Async plane update is supposed to work only when updating the FB or FB position of an already enabled plane. That does not apply to requests where the plane was previously disabled or assigned to a different CTRC. Check old_plane_state->crtc value to make sure async plane update is allowed. Fixes: fef9df8b5945 ("drm/atomic: initial support for asynchronous plane update") Cc: <[email protected]> Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-07-25drm: Add support for pps and compression mode command packetvkorjani1-0/+2
After enabling DSC we need to send compression mode command packet and pps data packet, for which 2 new data types are added 07h Compression Mode Data Type Write , short write, 2 parameters 0Ah PPS Long Write (word count determines number of bytes) This patch adds support to send these packets. Cc: David Airlie <[email protected]> Cc: Jean-Christophe Plagniol-Villard <[email protected]> Cc: Tomi Valkeinen <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Changes in v3: - None Signed-off-by: vkorjani <[email protected]> [seanpaul removed pps_write_buffer fn, added types to packet_format helpers] Signed-off-by: Sean Paul <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-25drm/msm/mdp5: negative x/y in cursor moveCarsten Behling1-8/+43
modesetting X11 driver may provide negative x/y cordinates in mdp5_crtc_cursor_move call when rotation is enabled. Cursor buffer can overlap down to its negative width/height. ROI has to be recalculated for negative x/y indicating using the lower/right corner of the cursor buffer and hotspot must be set in MDP5_LM_CURSOR_XY_SRC_Y MDP5_LM_CURSOR_XY_SRC_X. Signed-off-by: Carsten Behling <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-25drm/msm/dsi: replace version checks with helper functionsSibi Sankar1-212/+29
Replace version checks with the helper functions bound to cfg_handler for DSI v2, DSI 6G 1.x and DSI 6G v2.0+ controllers Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-25drm/msm/dsi: add implementation for helper functionsSibi Sankar3-11/+278
Add dsi host helper function implementation for DSI v2 DSI 6G 1.x and DSI 6G v2.0+ controllers Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-25drm/msm/dsi: add dsi host helper functions supportSibi Sankar2-0/+13
Add dsi host helper functions support for DSI v2 and DSI 6G 1.x controllers that are under version checks Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-25drm/msm/mdp5: fix missing CTL flushRob Clark1-1/+11
f9cb8d8d836e fixed various race conditions with CTL flush, in particular flushing and sending the START signal before encoder state was updated. But it did this a little too well in some cases that don't trigger encoder->enable(), and CTL[n].FLUSH would never be set. When page flips happen it would paper over the bug, since the first plag flip would flush out the state to the hardware. The issue could be reproduced with, for example, modetest (without the '-v' argument). Fixes: f9cb8d8d836e drm/msm/mdp5: rework CTL START signal handling Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Sean Paul <[email protected]>
2018-07-25drm/msm/gpu: Increase the pm runtime autosuspend for 5xxJordan Crouse3-2/+15
Experimentation shows that resuming power quickly after suspending ends up forcing a system hang for unknown reasons on 5xx targets. To avoid cycling the power too much (especially during init) turn up the autosuspend time for a5xx to 250ms and use pm_runtime_put_autosuspend() when applicable. Signed-off-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-25drm/msm/adreno: Add power management functions for system sleepDaniel Mack1-0/+1
When a msm8016 based system is woken up from suspend, the firmware in the adreno device hangs. [ 83.903416] qcom-iommu-ctx 1f09000.iommu-ctx: Unhandled context fault: fsr=0x202, iova=0x0000000000000000, fsynr=0x2, cb=1 [ 85.853633] msm 1a00000.mdss: A306: hangcheck detected gpu lockup rb 0! [ 85.853661] msm 1a00000.mdss: A306: completed fence: 370 [ 85.859073] msm 1a00000.mdss: A306: submitted fence: 372 [ 85.865113] msm 1a00000.mdss: A306: hangcheck recover! Fix this by adding pm_runtime_force_suspend/pm_runtime_force_resume as sleep ops. Signed-off-by: Daniel Mack <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-25drm/msm: call drm_atomic_helper_suspend() and drm_atomic_helper_resume()Daniel Mack2-0/+10
To make suspend and resume work on msm8916 platforms, call into the generic helpers and preserve the state across suspends. Signed-off-by: Daniel Mack <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2018-07-24drm/amd/display: DC 3.1.58Harry Wentland1-1/+1
Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-24drm/amd/display: separate dc_debug into dc_debug_options and dc_debug dataJun Lei6-15/+18
[why] confusing as to which part of debug is informational, and which part causes behavioral change Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-24drm/amd/display: Decouple aux from i2cBhawanpreet Lakha14-14/+1549
[Why] Aux engine is created from i2caux layer. We want to remove this layer and use the engine directly. [How] Decouple aux engine from i2caux. Move aux engine related code to dce folder and use dc resource pool to manage the engine. And use the engine functions directly Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-24drm/amd/display: DPP CM ICSC AYCRCB8888 format supportvikrant mhaske2-1/+5
[why] Diags has POR to run the video workload using AYCRCB8888 through DCN; capture it through DWB and send it to VCN hardware to encode [how] added the code to support this format so that DPP ICSC will be able to convert it from YUV444 to internal RGB and DWB OCSC will be able to convert from internal RGB to YUV420 Signed-off-by: vikrant mhaske <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-24drm/amd/display: On dce100, set clocks to 0 on suspendDavid Francis1-3/+16
[Why] When a dce100 asic was suspended, the clocks were not set to 0. Upon resume, the new clock was compared to the existing clock, they were found to be the same, and so the clock was not set. This resulted in a pernicious blackscreen. [How] In atomic commit, check to see if there are any active pipes. If no, set clocks to 0 Signed-off-by: David Francis <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-24drm/amd/display: allow diags to skip initial link trainingTony Cheng4-3/+9
[why] diag specify what the full config and is only concerned about pass/fail at the end having inter-op code like verifiying we can actually train at reported link rate slows down diag test and add complexity we don't need [how] add dc_debug option to skip capability link trianing also remove hbr in function name as verify is not specific to hbr Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Ken Chalmers <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-24drm/amd/display: Remove unnecessary warningMikita Lipski1-4/+0
[why] The warning message floods the dmesg log on Tonga even though it is expected to have a pix_clk set to zero, when the pipe is not active. [how] remove the assert Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-24drm/amdgpu: move the amdgpu_fbdev_set_suspend() further upShirish S1-3/+3
This patch moves amdgpu_fbdev_set_suspend() to the beginning of suspend sequence. This is to ensure fbcon does not to write to the VRAM after GPU is powerd down. Signed-off-by: Shirish S <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-24drm/amdgpu: Don't warn on destroying a pinned BOMichel Dänzer1-1/+1
The warning turned out to be not so useful, as BO destruction tends to be deferred to a workqueue. Also, we should be preventing any damage from this now, so not really important anymore to fix code doing this. Acked-by: Alex Deucher <[email protected]> Tested-by: Mike Lothian <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.