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2020-05-22drm/amd/powerpay: Disable gfxoff when setting manual mode on picasso and ravenchen gong1-0/+9
[Problem description] 1. Boot up picasso platform, launches desktop, Don't do anything (APU enter into "gfxoff" state) 2. Remote login to platform using SSH, then type the command line: sudo su -c "echo manual > /sys/class/drm/card0/device/power_dpm_force_performance_level" sudo su -c "echo 2 > /sys/class/drm/card0/device/pp_dpm_sclk" (fix SCLK to 1400MHz) 3. Move the mouse around in Window 4. Phenomenon : The screen frozen Tester will switch sclk level during glmark2 run time. APU will enter "gfxoff" state intermittently during glmark2 run time. The system got hanged if fix GFXCLK to 1400MHz when APU is in "gfxoff" state. [Debug] 1. Fix SCLK to X MHz 1400: screen frozen, screen black, then OS will reboot. 1300: screen frozen. 1200: screen frozen, screen black. 1100: screen frozen, screen black, then OS will reboot. 1000: screen frozen, screen black. 900: screen frozen, screen black, then OS will reboot. 800: Situation Nomal, issue disappear. 700: Situation Nomal, issue disappear. 2. SBIOS setting: AMD CBS --> SMU Debug Options -->SMU Debug --> "GFX DLDO Psm Margin Control": 50 : Situation Nomal, issue disappear. 45 : Situation Nomal, issue disappear. 40 : Situation Nomal, issue disappear. 35 : Situation Nomal, issue disappear. 30 : screen black. 25 : screen frozen, then blurred screen. 20 : screen frozen. 15 : screen black. 10 : screen frozen. 5 : screen frozen, then blurred screen. 3. Disable GFXOFF feature Situation Nomal, issue disappear. [Why] Through a period of time debugging with Sys Eng team and SMU team, Sys Eng team said this is voltage/frequency marginal issue not a F/W or H/W bug. This experiment proves that default targetPsm [for f=1400MHz] is not sufficient when GFXOFF is enabled on Picasso. SMU team think it is an odd test conditions to force sclk="1400MHz" when GPU is in "gfxoff" state，then wake up the GFX. SCLK should be in the "lowest frequency" when gfxoff. [How] Disable gfxoff when setting manual mode. Enable gfxoff when setting other mode(exiting manual mode) again. By the way, from the user point of view, now that user switch to manual mode and force SCLK Frequency, he don't want SCLK be controlled by workload.It becomes meaningless to "switch to manual mode" if APU enter "gfxoff" due to lack of workload at this point. Tips: Same issue observed on Raven. Signed-off-by: chen gong <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-22drm/amdgpu: fix pm sysfs node handling (v2)Alex Deucher1-4/+4
Fix typos that prevented them from showing up. v2: switch other files in addition to pp_clk_voltage Fixes: 4e01847c38f7a5 ("drm/amdgpu: optimize amdgpu device attribute code") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1150 Signed-off-by: Alex Deucher <[email protected]> Acked-by: Evan Quan <[email protected]>
2020-05-22drm/amdgpu: move gpu_info parsing after common early initAlex Deucher1-4/+4
We need to get the silicon revision id before we parse the firmware in order to load the correct gpu info firmware for raven2 variants. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1103 Acked-by: Christian König <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-22drm/amdgpu: move discovery gfx config fetchingAlex Deucher1-4/+3
Move it into the fw_info function since it's logically part of the same functionality. Acked-by: Christian König <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-05-22drm/msm/dpu: dpu_setup_dspp_pcc() can be statickbuild test robot1-1/+1
Fixes: 4259ff7ae509 ("drm/msm/dpu: add support for pcc color block in dpu driver") Signed-off-by: kbuild test robot <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-05-22drm/msm/a6xx: a6xx_hfi_send_start() can be statickbuild test robot1-2/+2
Fixes: 8167e6fa76c8 ("drm/msm/a6xx: HFI v2 for A640 and A650") Signed-off-by: kbuild test robot <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-05-22Merge branch 'linux-5.8' of git://github.com/skeggsb/linux into drm-nextDave Airlie76-622/+1198
- HD audio fixes on recent systems - vGPU detection (fail probe if we're on one, for now) - Interlaced mode fixes (mostly avoidance on Turing, which doesn't support it) - SVM improvements/fixes - NVIDIA format modifier support - Misc other fixes. Signed-off-by: Dave Airlie <[email protected]> From: Ben Skeggs <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/ <CACAvsv6DcRFMDVEftdL7LxNtxuSQQ=qnfqdHXO0K=BmJ8Q2-+g@mail.gmail.com
2020-05-22Merge tag 'mediatek-drm-next-5.8' of ↵Dave Airlie6-11/+127
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next Mediatek DRM Next for Linux 5.8 This include dpi pin mode swap, config mipi_tx current and impedance, and some fixup. Signed-off-by: Dave Airlie <[email protected]> From: Chun-Kuang Hu <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-22drm/nouveau/dispnv50: fix runtime pm imbalance on errorDinghao Liu1-1/+3
pm_runtime_get_sync() increments the runtime PM usage counter even the call returns an error code. Thus a pairing decrement is needed on the error handling path to keep the counter balanced. Signed-off-by: Dinghao Liu <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau: fix runtime pm imbalance on errorDinghao Liu1-1/+1
pm_runtime_get_sync() increments the runtime PM usage counter even the call returns an error code. Thus a pairing decrement is needed on the error handling path to keep the counter balanced. Signed-off-by: Dinghao Liu <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau: fix runtime pm imbalance on errorDinghao Liu1-1/+3
pm_runtime_get_sync() increments the runtime PM usage counter even the call returns an error code. Thus a pairing decrement is needed on the error handling path to keep the counter balanced. Signed-off-by: Dinghao Liu <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/debugfs: fix runtime pm imbalance on errorDinghao Liu1-1/+4
pm_runtime_get_sync() increments the runtime PM usage counter even the call returns an error code. Thus a pairing decrement is needed on the error handling path to keep the counter balanced. Signed-off-by: Dinghao Liu <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/nouveau/hmm: fix migrate zero page to GPURalph Campbell1-9/+66
When calling OpenCL clEnqueueSVMMigrateMem() on a region of memory that is backed by pte_none() or zero pages, migrate_vma_setup() will fill the source PFN array with an entry indicating the source page is zero. Use this to optimize migration to device private memory by allocating GPU memory and zero filling it instead of failing to migrate the page. Signed-off-by: Ralph Campbell <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/nouveau/hmm: fix nouveau_dmem_chunk allocationsRalph Campbell1-192/+112
In nouveau_dmem_init(), a number of struct nouveau_dmem_chunk are allocated and put on the dmem->chunk_empty list. Then in nouveau_dmem_pages_alloc(), a nouveau_dmem_chunk is removed from the list and GPU memory is allocated. However, the nouveau_dmem_chunk is never removed from the chunk_empty list nor placed on the chunk_free or chunk_full lists. This results in only one chunk ever being actually used (2MB) and quickly leads to migration to device private memory failures. Fix this by having just one list of free device private pages and if no pages are free, allocate a chunk of device private pages and GPU memory. Signed-off-by: Ralph Campbell <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms/nv50-: Share DP SST mode_valid() handling with MSTLyude Paul5-20/+75
Currently, the nv50_mstc_mode_valid() function is happy to take any and all modes, even the ones we can't actually support sometimes like interlaced modes. Luckily, the only difference between the mode validation that needs to be performed for MST vs. SST is that eventually we'll need to check the minimum PBN against the MSTB's full PBN capabilities (remember-we don't care about the current bw state here). Otherwise, all of the other code can be shared. So, we move all of the common mode validation in nouveau_connector_mode_valid() into a separate helper, nv50_dp_mode_valid(), and use that from both nv50_mstc_mode_valid() and nouveau_connector_mode_valid(). Note that we allow for returning the calculated clock that nv50_dp_mode_valid() came up with, since we'll eventually want to use that for PBN calculation in nv50_mstc_mode_valid(). Signed-off-by: Lyude Paul <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms/nv50-: Move 8BPC limit for MST into nv50_mstc_get_modes()Lyude Paul1-11/+14
This just limits the BPC for MST connectors to a maximum of 8 from nv50_mstc_get_modes(), instead of doing so during nv50_msto_atomic_check(). This doesn't introduce any functional changes yet (other then userspace now lying about the max bpc, but we can't support that yet anyway so meh). But, we'll need this in a moment so that we can share mode validation between SST and MST which will fix some real world issues. Signed-off-by: Lyude Paul <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms/gv100-: Add support for interlaced modesLyude Paul2-4/+6
We advertise being able to set interlaced modes, so let's actually make sure to do that. Otherwise, we'll end up hanging the display engine due to trying to set a mode with timings adjusted for interlacing without telling the hardware it's actually an interlaced mode. Signed-off-by: Lyude Paul <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms/nv50-: Probe SOR and PIOR caps for DP interlacing supportLyude Paul15-3/+118
Right now, we make the mistake of allowing interlacing on all connectors. Nvidia hardware does not always support interlacing with DP though, so we need to make sure that we don't allow interlaced modes to be set in such situations as otherwise we'll end up accidentally hanging the display HW. This fixes some hangs with Turing, which would be caused by attempting to set an interlaced mode on hardware that doesn't support it. This patch likely fixes other hardware hanging in the same way as well. Note that we say we probe PIOR caps, but they don't actually have any interlacing caps. So, the get_caps() function for PIORs just sets interlacing support to true. Changes since v1: * Actually probe caps correctly this time, both on EVO and NVDisplay. Changes since v2: * Fix probing for < GF119 * Use vfunc table, in prep for adding more caps in the future. Signed-off-by: Lyude Paul <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms/nv50-: Initialize core channel in nouveau_display_create()Lyude Paul1-1/+4
We'll need the core channel initialized and ready by the time that we start creating modesetting objects, so that we can call the NV507D_GET_CAPABILITIES method to make the hardware expose it's modesetting capabilities for later probing. So, when loading the driver prepare the core channel from within nouveau_display_create(). Everywhere else, we initialize the core channel during resume. Signed-off-by: Lyude Paul <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/disp/hda/gv100-: NV_PDISP_SF_AUDIO_CNTRL0 register movedBen Skeggs5-2/+35
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/disp/hda/gf119-: select HDA device entry based on bound headBen Skeggs1-3/+4
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/disp/hda/gf119-: add HAL for programming device entry in SFBen Skeggs8-2/+17
Register has moved on GV100. Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/disp/hda/gt215-: pass head to nvkm_ior.hda.eld()Ben Skeggs4-6/+6
We're going to use the bound head to select HDA device entry. Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/disp/nv50-: increase timeout on pio channel free() pollingBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms: Fix regression by audio component transitionTakashi Iwai1-6/+10
Since the commit 742db30c4ee6 ("drm/nouveau: Add HD-audio component notifier support"), the nouveau driver notifies and pokes the HD-audio HPD and ELD via audio component, but this seems broken. The culprit is the naive assumption that crtc->index corresponds to the HDA pin. Actually this rather corresponds to the MST dev_id (alias "pipe" in the audio component framework) while the actual port number is given from the output ior id number. This patch corrects the assignment of port and dev_id arguments in the audio component ops to recover from the HDMI/DP audio regression. Fixes: 742db30c4ee6 ("drm/nouveau: Add HD-audio component notifier support") BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=207223 Cc: <[email protected]> Signed-off-by: Takashi Iwai <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/device: use regular PRI accessors in chipset detectionBen Skeggs1-18/+13
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/device: detect vGPUsKarol Herbst1-3/+12
Using ENODEV as this prevents probe failed errors in dmesg. v2: move check further down Signed-off-by: Karol Herbst <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/device: detect if changing endianness failedKarol Herbst1-5/+21
v2: relax the checks a little Signed-off-by: Karol Herbst <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/device: rework mmio mapping code to get rid of second mapKarol Herbst1-12/+15
Fixes warnings on GPUs with smaller a smaller mmio region like vGPUs. Signed-off-by: Karol Herbst <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/mmu: Remove unneeded semicolonZheng Bin2-2/+2
Fixes coccicheck warning: drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h:307:2-3: Unneeded semicolon drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c:583:2-3: Unneeded semicolon Reported-by: Hulk Robot <[email protected]> Signed-off-by: Zheng Bin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau: Use generic helper to check _PR3 presenceKai-Heng Feng1-34/+10
Replace nouveau_pr3_present() in favor of a more generic one, pci_pr3_present(). Also the presence of upstream bridge _PR3 doesn't need to go hand in hand with device's _DSM, so check _PR3 before _DSM. Signed-off-by: Kai-Heng Feng <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/acr: Use kmemdup instead of kmalloc and memcpyZou Wei1-8/+4
Fixes coccicheck warning: drivers/gpu/drm/nouveau/nvkm/subdev/acr/hsfw.c:103:23-30: WARNING opportunity for kmemdup drivers/gpu/drm/nouveau/nvkm/subdev/acr/hsfw.c:113:22-29: WARNING opportunity for kmemdup Fixes: 22dcda45a3d1 ("drm/nouveau/acr: implement new subdev to replace "secure boot"") Reported-by: Hulk Robot <[email protected]> Signed-off-by: Zou Wei <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/core/memory: remove redundant assignments to variable retColin Ian King1-1/+1
The variable ret is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/svm: map pages after migrationRalph Campbell4-17/+95
When memory is migrated to the GPU, it is likely to be accessed by GPU code soon afterwards. Instead of waiting for a GPU fault, map the migrated memory into the GPU page tables with the same access permissions as the source CPU page table entries. This preserves copy on write semantics. Signed-off-by: Ralph Campbell <[email protected]> Cc: Christoph Hellwig <[email protected]> Cc: Jason Gunthorpe <[email protected]> Cc: "Jérôme Glisse" <[email protected]> Cc: Ben Skeggs <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/disp/gv100-: expose capabilities classBen Skeggs6-0/+69
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/bios: move ACPI _ROM handlingBen Skeggs3-76/+47
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau: remove open-coded version of remove_conflicting_pci_framebuffers()Ben Skeggs1-28/+3
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/gr/gk20a: move MODULE_FIRMWARE firmware definitionsBen Skeggs2-11/+11
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/ibus: use nvkm_subdev_new_()Ben Skeggs6-30/+6
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/core: add nvkm_subdev_new_() for bare subdevsBen Skeggs2-0/+13
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms: Support NVIDIA format modifiersJames Jones3-9/+104
Allow setting the block layout of a nouveau FB object using DRM format modifiers. When specified, the format modifier block layout and kind overrides the GEM buffer's implicit layout and kind. The specified format modifier is validated against the list of modifiers supported by the target display hardware. v2: Used Tesla family instead of NV50 chipset compare v4: Do not cache kind, tile_mode in nouveau_framebuffer v5: Resolved against nouveau_framebuffer cleanup Signed-off-by: James Jones <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms: Check framebuffer size against boJames Jones1-0/+98
Make sure framebuffer dimensions and tiling parameters will not result in accesses beyond the end of the GEM buffer they are bound to. v3: Return EINVAL when creating FB against BO with unsupported tiling v5: Resolved against nouveau_framebuffer cleanup Signed-off-by: James Jones <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms: Add format mod prop to base/ovly/nvdispJames Jones6-4/+112
Advertise support for the full list of format modifiers supported by each class of NVIDIA desktop GPU display hardware. Stash the array of modifiers in the nouveau_display struct for use when validating userspace framebuffer creation requests, which will be supportd in a subsequent change. Signed-off-by: James Jones <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/acr: ensure falcon providing acr functions is bootstrapped firstBen Skeggs1-0/+5
Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms: Remove struct nouveau_framebufferThomas Zimmermann4-38/+28
After its cleanup, struct nouveau_framebuffer is only a wrapper around struct drm_framebuffer. Use the latter directly. Signed-off-by: Thomas Zimmermann <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms: Remove field nvbo from struct nouveau_framebufferThomas Zimmermann7-84/+75
The buffer object stored in nvbo is also available GEM object in obj[0] of struct drm_framebuffer. Therefore remove nvbo in favor obj[0] and replace all references accordingly. This may require an additional cast. With this change we can already replace nouveau_user_framebuffer_destroy() and nouveau_user_framebuffer_create_handle() with generic GEM helpers. Calls to nouveau_framebuffer_new() receive a GEM object. Signed-off-by: Thomas Zimmermann <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms: Move struct nouveau_framebuffer.vma to struct nouveau_fbdevThomas Zimmermann5-14/+14
The vma field of struct nouveau_framebuffer is a special field for the the accelerated fbdev console. Hence there's at most one single instance for the active console. Moving it into struct nouveau_fbdev makes struct nouveau_framebuffer slightly smaller and brings it closer to struct drm_framebuffer. Signed-off-by: Thomas Zimmermann <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau/kms: Remove unused fields from struct nouveau_framebufferThomas Zimmermann1-5/+0
Signed-off-by: Thomas Zimmermann <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22drm/nouveau: fix out-of-tree module buildBen Skeggs1-4/+6
The $(srctree) addition a while back busted building the out-of-tree version of the module, and I've been hacking it up ever since. This allows us to work around the issue. Signed-off-by: Ben Skeggs <[email protected]>
2020-05-22Merge tag 'amd-drm-fixes-5.7-2020-05-21' of ↵Dave Airlie18-95/+126
git://people.freedesktop.org/~agd5f/linux into drm-fixes amd-drm-fixes-5.7-2020-05-21: amdgpu: - DP fix - Floating point fix - Fix cursor stutter issue Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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