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2017-11-02Backmerge tag 'v4.14-rc7' into drm-nextDave Airlie27-140/+135
Linux 4.14-rc7 Requested by Ben Skeggs for nouveau to avoid major conflicts, and things were getting a bit conflicty already, esp around amdgpu reverts.
2017-11-02Merge tag 'drm-hisilicon-next-2017-11-01' of github.com:xin3liang/linux into ↵Dave Airlie1-0/+3
drm-next For 4.15 * tag 'drm-hisilicon-next-2017-11-01' of github.com:xin3liang/linux: drm/hisilicon: Ensure LDI regs are properly configured.
2017-11-02Merge tag 'drm-msm-next-2017-11-01' of ↵Dave Airlie42-702/+1945
git://people.freedesktop.org/~robclark/linux into drm-next + preemption support for a5xx[1][2] + display fixes for 8x96 (snapdragon 820) including fixes for 4k scanout (hwpipe assignment re-work to handle multiple hwpipe assigned to plane for wide scanout) + async cursor plane updates and fixes + refactor adreno_bind/hwinit.. still defer fw loading until device open, but move clk/irq/etc to probe/bind time to fix issues when fw isn't present in filesys + clk/dt bindings cleanups w/ backward compat via msm_clk_get() (dt docs part ack'ed by Rob Herring) + fw loading re-work with helper to handle either /lib/firmware/qcom/$fw or /lib/firmware/$fw.. background, we've started landing fw for some of generations in linux-firmware, but there is a preference to put fw files under 'qcom' subdirectory, which is not what was done on android or for people who copied fw from android. So now we first look in qcom subdir and then fallback to the original location. + bunch of GPU debugging enhancements, to dump full cmdline of processes that trigger faults, and to add a new debugfs to capture cmdstream of just submits that triggered faults.. both quite useful for piglit ;-) * tag 'drm-msm-next-2017-11-01' of git://people.freedesktop.org/~robclark/linux: (38 commits) drm/msm: use %z format modifier for printing size_t drm/msm/mdp5: Don't use async plane update path if plane visibility changes drm/msm/mdp5: mdp5_crtc: Restore cursor state only if LM cursors are enabled drm/msm/mdp5: Update mdp5_pipe_assign to spit out both planes drm/msm/mdp5: Prepare mdp5_pipe_assign for some rework drm/msm: remove mdp5_cursor_plane_funcs drm/msm: update cursors asynchronously through atomic drm/msm/atomic: switch to drm_atomic_helper_check drm/msm/mdp5: restore cursor state when enabling crtc drm/msm/mdp5: don't use autosuspend drm/msm/mdp5: ignore planes that are not visible drm/msm: dump submits which triggered gpu hang drm/msm: preserve IOVAs in submit's bo table drm/msm/rd: allow adding addition msg to top of dump drm/msm: split rd debugfs file drm/msm: add special _get_vaddr_active() for cmdstream dumps drm/msm: show task cmdline in gpu recovery messages drm/msm: dump a rd GPUADDR header for all buffers in the command drm/msm: Removed unused struct_mutex_task drm/msm: Implement preemption for A5XX targets ...
2017-11-01drm/msm: use %z format modifier for printing size_tArnd Bergmann1-1/+1
The return type of ARRAY_SIZE() is size_t, so we have to use %zu instead of %lu to avoid this warning: drivers/gpu/drm/msm/msm_gpu.c: In function 'msm_gpu_init': drivers/gpu/drm/msm/msm_gpu.c:742:31: error: format '%lu' expects argument of type 'long unsigned int', but argument 7 has type 'unsigned int' [-Werror=format=] The warning it otherwise harmless as size_t is always the same size as unsigned long in all supported architectures, but gcc doesn't know that. Fixes: c2fceabca6d5 ("drm/msm: Support multiple ringbuffers") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-11-01drm/hisilicon: Ensure LDI regs are properly configured.Peter Griffin1-0/+3
This patch fixes the following soft lockup: BUG: soft lockup - CPU#0 stuck for 23s! [weston:307] On weston idle-timeout the IP is powered down and reset asserted. On weston resume we get a massive vblank IRQ storm due to the LDI registers having lost some state. This state loss is caused by ade_crtc_atomic_begin() not calling ade_ldi_set_mode(). With this patch applied resuming from Weston idle-timeout works well. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: John Stultz <john.stultz@linaro.org> Cc: stable@vger.kernel.org Reviewed-by: Xinliang Liu <xinliang.liu@linaro.org> Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org>
2017-10-28drm/msm/mdp5: Don't use async plane update path if plane visibility changesArchit Taneja1-0/+25
When a plane moves out of bounds (i.e, outside the crtc clip region), the plane state's "visible" parameter changes to false. When this happens, we (a) release the hwpipe resources away from it, and (b) unstage the corresponding hwpipe(s) from the Layer Mixers in the CRTC. (a) requires use to acquire the global atomic state and assign a new hwpipe. (b) requires us to re-configure the Layer Mixer, which is done in the CRTC. We don't want to do these things in the async plane update path, so return an error if the new state's "visible" isn't the same as the current state's "visible". Cc: Gustavo Padovan <gustavo.padovan@collabora.com> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm/mdp5: mdp5_crtc: Restore cursor state only if LM cursors are enabledArchit Taneja1-29/+37
MDP5 on newer SoCs support cursor planes (i.e, cursor SSPPs). They are a separate entity unlike the cursors within LM. Do not try to restore the MDP5 LM cursor registers, or the corresponding CTL bits if we are not using LM cursors. Also, since we've introduced a new variable 'lm_cursor_enabled', we can now use it to avoid creating a different sets of crtc_funcs for CRTCs with LM cursors and CRTCs with cursor planes. Fixes: "drm/msm/mdp5: restore cursor state when enabling crtc" Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm/mdp5: Update mdp5_pipe_assign to spit out both planesArchit Taneja3-20/+57
We currently call mdp5_pipe_assign() twice to assign the left and right hwpipes for our drm_plane. When merging 2 hwpipes, there are a few constraints that we need to keep in mind: - Only the same types of SSPPs are preferred. I.e, a RGB pipe should be paired with another RGB pipe, VIG with VIG etc. - The hwpipe staged on the left should have a higher priority than the hwpipe staged on the right. The priorities are as follows: VIG0 > VIG1 > VIG2 > VIG3 RGB0 > RGB1 > RGB2 > RGB3 DMA0 > DMA1 We can't apply these constraints easily if mdp5_pipe_assign() is called twice. Update mdp5_pipe_assign() to find both hwpipes in one go, and add the extra constraints needed. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm/mdp5: Prepare mdp5_pipe_assign for some reworkArchit Taneja3-27/+27
mdp5_pipe_assign currently returns the hwpipe pointer for the drm_plane. Return it indirectly by setting a pointer passed as an argument. This is needed because we want the func to find out the right hwpipe too. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: remove mdp5_cursor_plane_funcsGustavo Padovan1-22/+3
After converting legacy cursor updates to atomic async commits mdp5_cursor_plane_funcs just duplicates mdp5_plane_funcs now. Cc: Rob Clark <robdclark@gmail.com> Cc: Archit Taneja <architt@codeaurora.org> Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com> Tested-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: update cursors asynchronously through atomicGustavo Padovan2-88/+75
Add support to async updates of cursors by using the new atomic interface for that. Basically what this commit does is do what mdp5_update_cursor_plane_legacy() did but through atomic. v5: call drm_atomic_helper_async_check() from the check hook v4: add missing atomic async commit call to msm_atomic_commit(Archit Taneja) v3: move size checks back to drivers (Ville Syrjälä) v2: move fb setting to core and use new state (Eric Anholt) Cc: Rob Clark <robdclark@gmail.com> Cc: Archit Taneja <architt@codeaurora.org> Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com> Tested-by: Archit Taneja <architt@codeaurora.org> (v4) [added comment about not hitting async update path if hwpipes are re-assigned or global state is touched] Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm/atomic: switch to drm_atomic_helper_checkRob Clark3-32/+1
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm/mdp5: restore cursor state when enabling crtcRob Clark1-32/+68
Since we enabled runtime PM, we cannot count on cursor registers to retain their values. This can result in situations where we think the cursor is enabled when we enable the CRTC but it is trying to scan out null (and the rest of cursor position/size is lost), resulting in faults and generally angering the hw when coming out of DPMS with a cursor enabled. stable backport note: reverting 774e39ee3572 is also a suitable fix Fixes: 774e39ee3572 drm/msm/mdp5: Set up runtime PM for MDSS Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Archit Taneja <architt@codeaurora.org>
2017-10-28drm/msm/mdp5: don't use autosuspendRob Clark5-13/+13
It's only likely to paper over bugs. Unlike the gpu, where we want to keep things alive a bit longer in expectation of the next frame's submit, when the display is shut down we can power off immediately. Signed-off-by: Rob Clark <robdclark@gmail.com> Acked-by: Archit Taneja <architt@codeaurora.org>
2017-10-28drm/msm/mdp5: ignore planes that are not visibleRob Clark1-0/+8
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: dump submits which triggered gpu hangRob Clark1-20/+27
Note we need to move update_fences() to after msm_rd_dump_submit(), otherwise the bo's referenced by the submit may no longer be valid. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: preserve IOVAs in submit's bo tableRob Clark1-5/+6
We need this if we want to dump the submit after cleanup (ie. from hang or fault). But in the backoff/unpin case we want to clear them. So add a flag so we can skip clearing the IOVAs in at cleanup. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm/rd: allow adding addition msg to top of dumpRob Clark3-4/+16
For faults or hangs, it is nice to be able to include a bit more information. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: split rd debugfs fileRob Clark3-29/+79
Split into two instances, the existing $debugfs/rd which continues to dump all submits, and $debugfs/hangrd which will be used to dump just submits that cause gpu hangs (and eventually faults, but that will require some iommu framework enhancements). Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: add special _get_vaddr_active() for cmdstream dumpsRob Clark3-3/+22
Prep work for adding a debugfs file that dumps just submits which trigger hangs/faults. In this case the bo may already be in the MADV_DONTNEED state, but will be still on the active list (since the submit hasn't completed yet). So the normal check that the bo is in the WILLNEED state does not apply. (But of course the bo should definitely not be in the PURGED state!) Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: show task cmdline in gpu recovery messagesRob Clark1-12/+43
Now that freedreno gallium driver defaults to using submit_queue task (render reordering), just showing task->comm is not so useful (ie. it is always "flush_queue:0"), so also dump the cmdline. This should also be more useful for piglit/shader_runner. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: dump a rd GPUADDR header for all buffers in the commandJordan Crouse1-15/+15
Currently the rd dump avoids any buffers marked as WRITE under the assumption that the contents are not interesting. While it is true that the contents are uninteresting we should still print the iova and size for all buffers so that any listening replay tools can correctly construct the submission. Print the header for all buffers but only dump the contents for buffers marked as READ. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: Removed unused struct_mutex_taskJordan Crouse2-8/+0
Recent changes to locking have rendered struct_mutex_task unused. Unused since 0e08270a1f01. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: Implement preemption for A5XX targetsJordan Crouse10-20/+599
Implement preemption for A5XX targets - this allows multiple ringbuffers for different priorities with automatic preemption of a lower priority ringbuffer if a higher one is ready. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: Make the value of RB_CNTL (almost) genericJordan Crouse2-5/+12
We use a global ringbuffer size and block size for all targets and at least for 5XX preemption we need to know the value the RB_CNTL in several locations so it makes sense to calculate it once and use it everywhere. The only monkey wrench is that we need to disable the RPTR shadow for A430 targets but that only needs to be done once and doesn't affect A5XX so we can or in the value at init time. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: Shadow current pointer in the ring until command is completeJordan Crouse3-6/+16
Add a shadow pointer to track the current command being written into the ring. Don't commit it as 'cur' until the command is submitted. Because 'cur' is used to construct the software copy of the wptr this ensures that somebody peeking in on the ring doesn't assume that a command is inflight while it is being written. This isn't a huge deal with a single ring (though technically the hangcheck could assume the system is prematurely busy when it isn't) but it will be rather important for preemption where the decision to preempt is based on a non-empty ringbuffer. Without a shadow an aggressive preemption scheme could assume that the ringbuffer is non empty and switch to it before the CPU is done writing the command and boom. Even though preemption won't be supported for all targets because of the way the code is organized it is simpler to make this generic for all targets. The extra load for non-preemption targets should be minimal. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: Add a parameter query for the number of ringbuffersJordan Crouse1-0/+3
In order to manage ringbuffer priority to its fullest userspace should know how many ringbuffers it has to work with. Add a parameter to return the number of active rings. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: Support multiple ringbuffersJordan Crouse18-210/+363
Add the infrastructure to support the idea of multiple ringbuffers. Assign each ringbuffer an id and use that as an index for the various ring specific operations. The biggest delta is to support legacy fences. Each fence gets its own sequence number but the legacy functions expect to use a unique integer. To handle this we return a unique identifier for each submission but map it to a specific ring/sequence under the covers. Newer users use a dma_fence pointer anyway so they don't care about the actual sequence ID or ring. The actual mechanics for multiple ringbuffers are very target specific so this code just allows for the possibility but still only defines one ringbuffer for each target family. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: Move memptrs to msm_gpuJordan Crouse7-72/+58
When we move to multiple ringbuffers we're going to store the data in the memptrs on a per-ring basis. In order to prepare for that move the current memptrs from the adreno namespace into msm_gpu. This is way cleaner and immediately lets us kill off some sub functions so there is much less cost later when we do move to per-ring structs. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: Add per-instance submit queuesJordan Crouse7-16/+228
Currently the behavior of a command stream is provided by the user application during submission and the application is expected to internally maintain the settings for each 'context' or 'rendering queue' and specify the correct ones. This works okay for simple cases but as applications become more complex we will want to set context specific flags and do various permission checks to allow certain contexts to enable additional privileges. Add kernel-side submit queues to be analogous to 'contexts' or 'rendering queues' on the application side. Each file descriptor instance will maintain its own list of queues. Queues cannot be shared between file descriptors. For backwards compatibility context id '0' is defined as a default context specifying no priority and no special flags. This is intended to be the usual configuration for 99% of applications so that a garden variety application can function correctly without creating a queue. Only those applications requiring the specific benefit of different queues need create one. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm/mdp5: disable vblanks when crtc is offRob Clark1-0/+6
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm/mdp4: disable vblanks when crtc is offRob Clark1-0/+7
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm/hdmi: convert to msm_clk_get()Rob Clark5-11/+9
We already have, as a result of upstreaming the gpu bindings, msm_clk_get() which will try to get the clock both without and with a "_clk" suffix. Use this in HDMI code so we can drop the "_clk" suffix in bindings while maintaing backwards compatibility. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Sean Paul <seanpaul@chromium.org>
2017-10-28drm/msm/edp: convert to msm_clk_get()Rob Clark1-11/+11
We already have, as a result of upstreaming the gpu bindings, msm_clk_get() which will try to get the clock both without and with a "_clk" suffix. Use this in eDP code so we can drop the "_clk" suffix in bindings while maintaing backwards compatibility. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Sean Paul <seanpaul@chromium.org>
2017-10-28drm/msm/dsi: convert to msm_clk_get()Rob Clark3-20/+20
We already have, as a result of upstreaming the gpu bindings, msm_clk_get() which will try to get the clock both without and with a "_clk" suffix. Use this in DSI code so we can drop the "_clk" suffix in bindings while maintaing backwards compatibility. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Sean Paul <seanpaul@chromium.org>
2017-10-28drm/msm/mdp5: always print mdp5 versionRob Clark1-1/+1
This is useful to see in the log, without requiring drm.debug. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm/adreno: deal with linux-firmware fw pathsRob Clark3-8/+103
When firmware was added to linux-firmware, it was put in a qcom sub- directory, unlike what we'd been using before. For a300_pfp.fw and a300_pm4.fw symlinks were created, but we'd prefer not to have to do this in the future. So add support to look in both places when loading firmware. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm/adreno: split out helper to load fwRob Clark4-18/+34
Prep work for the next patch. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm/adreno: load gpu at probe/bind timeRob Clark4-65/+73
Previously, in an effort to defer initializing the gpu until firmware was available (ie. rootfs mounted), the gpu was not loaded at when the subdevice was bound. Which resulted that clks/etc were requested in a place that devm couldn't really help unwind if something failed. Instead move request_firmware() to gpu->hw_init() and construct the gpu earlier in adreno_bind(). To avoid the rest of the driver needing to be aware of a gpu that hasn't managed to load firmware and hw_init() yet, stash the gpu ptr in the adreno device's drvdata, and don't set priv->gpu() until hw_init() succeeds. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm/hdmi: Remove mmagic_iface_clk from the 8x96 PHY clocksArchit Taneja1-1/+0
This was used as a placeholder. It was never really input to the MDSS/HDMI clocks. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-28drm/msm: fix _NO_IMPLICIT fencing caseRob Clark2-17/+18
We need to call reservation_object_reserve_shared() in both cases, but this wasn't happening in the _NO_IMPLICIT submit case. Fixes: f0a42bb ("drm/msm: submit support for in-fences") Reported-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-10-27Merge tag 'drm-intel-fixes-2017-10-26' of ↵Dave Airlie5-65/+15
git://anongit.freedesktop.org/drm/drm-intel into drm-fixes One fix for stable: - fix perf enable/disable ioctls for 32bits (Lionel) Plus GVT fixes: - Fix per_ctx_bb check (Zhenyu) - Fix GPU hang of Linux guest (Xion) - Refine MMIO_RING_F to check for presence of VCS2 ring (Zhi) * tag 'drm-intel-fixes-2017-10-26' of git://anongit.freedesktop.org/drm/drm-intel: drm/i915/gvt: Adding ACTHD mmio read handler drm/i915/gvt: Extract mmio_read_from_hw() common function drm/i915/gvt: Refine MMIO_RING_F() drm/i915/gvt: properly check per_ctx bb valid state
2017-10-26drm/i915/gvt: Adding ACTHD mmio read handlerXiong Zhang1-2/+3
When a workload is too heavy to finish it in gpu hang check timer intervals(1.5), gpu hang check function will check ACTHD register value to decide whether gpu is real dead or not. On real hw, ACTHD is updated by HW when workload is running, then host kernel won't think it is gpu hang. while guest kernel always read a constant ACTHD value as GVT doesn't supply ACTHD emulate handler, then guest kernel detects a fake gpu hang. To remove such guest fake gpu hang, this patch supply ACTHD mmio read handler which read real HW ACTHD register directly. Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/b4c9a097-3e62-124e-6856-b0c37764df7b@intel.com
2017-10-27drm/i915/gvt: Extract mmio_read_from_hw() common functionXiong Zhang1-16/+5
The mmio read handler for ring timestmap / instdone register are same as reading hw value directly. Extract it as common function to reduce code duplications. Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
2017-10-27drm/i915/gvt: Refine MMIO_RING_F()Zhi Wang2-45/+2
Inspect if the host has VCS2 ring by host i915 macro in MMIO_RING_F(). Also this helps on reducing some LOCs. Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
2017-10-27drm/i915/gvt: properly check per_ctx bb valid stateZhenyu Wang3-2/+5
Need to check valid state for per_ctx bb and bypass batch buffer combine for scan if necessary. Otherwise adding invalid MI batch buffer start cmd for per_ctx bb will cause scan failure, which is taken as -EFAULT now so vGPU would be put in failsafe. This trys to fix that by checking per_ctx bb valid state. Also remove old invalid WARNING that indirect ctx bb shouldn't depend on valid per_ctx bb. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
2017-10-26Merge branch 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie11-82/+94
into drm-next Just a few fixes for 4.15. * 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux: drm/amd/amdgpu: Remove workaround for suspend/resume in uvd7 drm/amdgpu: don't flush the TLB before initializing GART drm/amdgpu: minor cleanup for amdgpu_ttm_bind drm/amdgpu/psp: prevent page fault by checking write_frame address(v4) drm/amd/powerplay: retrieve the real-time coreClock values drm/amd/powerplay: fix performance drop on Vega10 drm/amd/powerplay: add one smc message for Vega10 drm/amd/powerplay: fix amd_powerplay_reset() amdgpu: add padding to the fence to handle ioctl. drm/amdgpu:fix wb_clear drm/amdgpu:fix vf_error_put drm/amdgpu/sriov:now must reinit psp drm/amdgpu: merge bios post checking functions
2017-10-25drm/amd/amdgpu: Remove workaround for suspend/resume in uvd7Tom St Denis1-11/+5
The workaround is not required anymor and would result in hangs during suspend/resume cycles if the uvd block were busy. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-25drm/amdgpu: don't flush the TLB before initializing GARTChristian König1-6/+7
No point in doing this. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-10-25drm/amdgpu: minor cleanup for amdgpu_ttm_bindChristian König1-1/+2
Filter the placement mask before using it. In theory it could be that we have other flags set here as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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