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2023-10-10drm/panel/panel-tpo-tpg110: fix a possible null pointer dereferenceMa Ke1-0/+2
In tpg110_get_modes(), the return value of drm_mode_duplicate() is assigned to mode, which will lead to a NULL pointer dereference on failure of drm_mode_duplicate(). Add a check to avoid npd. Signed-off-by: Ma Ke <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Neil Armstrong <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-10drm/panel: fix a possible null pointer dereferenceMa Ke1-0/+2
In versatile_panel_get_modes(), the return value of drm_mode_duplicate() is assigned to mode, which will lead to a NULL pointer dereference on failure of drm_mode_duplicate(). Add a check to avoid npd. Signed-off-by: Ma Ke <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Neil Armstrong <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-10drm/i915: Fix VLV color state readoutVille Syrjälä1-0/+1
VLV was missed when the color.get_config() hook was added. Remedy that. Not really sure what the final plan here was since a bunch of color related readout was left in intel_display.c anyway, but that's for anothr day to figure out... Cc: Jani Nikula <[email protected]> Fixes: 9af09dfcdfa1 ("drm/i915/color: move pre-SKL gamma and CSC enable read to intel_color") Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2023-10-09drm/i915/guc: Enable WA 14018913170Daniele Ceraolo Spurio3-0/+8
The GuC handles the WA, the KMD just needs to set the flag to enable it on the appropriate platforms. Signed-off-by: John Harrison <[email protected]> Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Reviewed-by: Vinay Belgaumkar <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-09drm/amdgpu: fix SI failure due to doorbells allocationIcenowy Zheng1-0/+4
SI hardware does not have doorbells at all, however currently the code will try to do the allocation and thus fail, makes SI AMDGPU not usable. Fix this failure by skipping doorbells allocation when doorbells count is zero. Fixes: 54c30d2a8def ("drm/amdgpu: create kernel doorbell pages") Reviewed-by: Shashank Sharma <[email protected]> Signed-off-by: Icenowy Zheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: add missing NULL checkChristian König1-1/+1
bo->tbo.resource can easily be NULL here. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2902 Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> CC: [email protected]
2023-10-09drm/amd/display: Don't set dpms_off for seamless bootDaniel Miess1-0/+3
[Why] eDPs fail to light up with seamless boot enabled [How] When seamless boot is enabled don't configure dpms_off in disable_vbios_mode_if_required. Reviewed-by: Charlene Liu <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Acked-by: Tom Chung <[email protected]> Signed-off-by: Daniel Miess <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: fix SI failure due to doorbells allocationIcenowy Zheng1-0/+4
SI hardware does not have doorbells at all, however currently the code will try to do the allocation and thus fail, makes SI AMDGPU not usable. Fix this failure by skipping doorbells allocation when doorbells count is zero. Fixes: 54c30d2a8def ("drm/amdgpu: create kernel doorbell pages") Reviewed-by: Shashank Sharma <[email protected]> Signed-off-by: Icenowy Zheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu/discovery: enable DCN 3.5.0 supportAaron Liu1-0/+1
Enable DCN 3.5.0 support. Signed-off-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdkfd: get doorbell's absolute offset based on the db_sizeArvind Yadav5-10/+24
Here, Adding db_size in byte to find the doorbell's absolute offset for both 32-bit and 64-bit doorbell sizes. So that doorbell offset will be aligned based on the doorbell size. v2: - Addressed the review comment from Felix. v3: - Adding doorbell_size as parameter to get db absolute offset. v4: Squash the two patches into one. Cc: Christian Koenig <[email protected]> Cc: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Shashank Sharma <[email protected]> Signed-off-by: Arvind Yadav <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: add missing NULL checkChristian König1-1/+1
bo->tbo.resource can easily be NULL here. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2902 Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> CC: [email protected]
2023-10-09drm/amd/display: 3.2.255Aric Cyr1-1/+1
This version brings along following fixes: - Refactor DPG test pattern logic for ODM cases - Refactor HWSS into component folder - Revert "drm/amd/display: Add a check for idle power optimization" - Revert "drm/amd/display: remove duplicated edp relink to fastboot - Update cursor limits based on SW cursor fallback limits - Update stream mask - Update pmfw_driver_if new structure - Modify SMU message logs - Don't set dpms_off for seamless boot Known issue: DWB (Writeback functionality) is broken. Fix will be available in DC 3.2.256 Acked-by: Tom Chung <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Disable virtual linksStylon Wang1-1/+1
[Why] This could work around the issue with DP tunneling producing a NULL pointer dereference. [How] Disable the virtual links. Reviewed-by: Tom Chung <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Disable SubVP if test pattern is enabledGeorge Shen1-1/+14
[Why] Enabling DPG causes HUBP to stay in blank constantly. If DPG is enabled while an MCLK switch is taking place with SubVP, it will cause the MCLK to never complete. This is because SubVP MCLK switch relies a HUBP VLine interrupt, which will never occur when HUBP is constantly in blank. [How] Disable SubVP when test pattern is enabled. Reviewed-by: Alvin Lee <[email protected]> Reviewed-by: Nevenko Stupar <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Refactor DPG test pattern logic for ODM casesGeorge Shen6-93/+175
[Why] Current DPG test pattern logic does not account for ODM configuration changes after test pattern has already been programmed. For example, if ODM2:1 is enabled after test pattern is already being output, the second pipe is not programmed to output test pattern, causing half the screen to be black. [How] Move DPG test pattern parameter calculations into separate function. Whenever ODM pipe configuration changes, re-calculate DPG test pattern parameters and program DPG if test pattern is currently enabled. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Don't set dpms_off for seamless bootDaniel Miess1-0/+3
[Why] eDPs fail to light up with seamless boot enabled [How] When seamless boot is enabled don't configure dpms_off in disable_vbios_mode_if_required. Reviewed-by: Charlene Liu <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Acked-by: Tom Chung <[email protected]> Signed-off-by: Daniel Miess <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Refactor HWSS into component folderMounika Adhuri94-116/+300
[why] Rename hw_sequencer to hwseq. Move all hwseq files to unique folder hwss. [how] creating hwss repo in dc, and moved the dcnxx_hwseq.c and .h files into corresponding new folders inside the hwss and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by: Martin Leung <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Mounika Adhuri <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Revert "drm/amd/display: Add a check for idle power ↵Sung Joon Kim3-21/+1
optimization" Revert commit 434cf7af492f ("drm/amd/display: Add a check for idle power optimization") Because it cause Freesync and S4 regression Reviewed-by: Aric Cyr <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: add hub->ctx_distance in setup_vmid_configYifan Zhang17-17/+18
add hub->ctx_distance when read CONTEXT1_CNTL, align w/ write back operation. v2: fix coding style errors reported by checkpatch.pl (Christian) Signed-off-by: Yifan Zhang <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Don't use fsleep for PSR exit waitsNicholas Kazlauskas2-2/+4
[Why] These functions can be called from high IRQ levels and the OS will hang if it tries to use a usleep_highres or a msleep. [How] Replace the fsleep with a udelay. Reviewed-by: Aric Cyr <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Update cursor limits based on SW cursor fallback limitsAlvin Lee4-37/+47
[Why&How] For determining the cursor size limit, use the same checks that are used for determining SW cursor fallback instead of only using SubVP Reviewed-by: Aric Cyr <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Update dml ssb from pmfw clock tableMuhammad Ahmed3-27/+3
[why] Need to use real clock table [How] Update the clock table Reviewed-by: Charlene Liu <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Muhammad Ahmed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Update stream maskDuncan Ma1-0/+7
[Why] Whenever stream changes because of new pipe arrangements such as ODM. The new stream mask is not reflected in DMCUB. The mismatch in stream mask is blocking ips entry in some scenarios. [How] Whenever stream arrangement changes, update stream mask and notify DMCUB. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Duncan Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Revert "drm/amd/display: remove duplicated edp relink to ↵Aric Cyr1-0/+59
fastboot" Revert commit 984abb5384b0 ("drm/amd/display: remove duplicated edp relink to fastboot") Because it cause 4k EDP not light up on boot Reviewed-by: Tom Chung <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Modify Vmin default valueMax Tseng2-2/+8
Fine tune the Vmin clock value Reviewed-by: Robin Chen <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Max Tseng <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Update pmfw_driver_if new structureCharlene Liu2-76/+174
[why] pmfw header file updated, need align with data structure. [How] Update the data structure. Reviewed-by: Sung joon Kim <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: VSIF v3 set Max Refresh RateMuhammad Ansari1-7/+2
[WHY] FreeSync spec requires PB8 and PB12 to be set to nominal refresh rate regardless of fixed rate or variable [HOW] Removed the condition that checks and overwrites max refresh rate and set PB8/PB12 to be set to max refresh rate always Reviewed-by: Anthony Koo <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Muhammad Ansari <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Modify SMU message logsSung Joon Kim4-6/+9
[why] It's important to make sure SMU messages are logged by default to improve debugging for power optimization use cases. [how] Change logs to warnings when SMU message returns non-success id. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: Fix potential null pointer derefernceStanley.Yang1-1/+2
The amdgpu_ras_get_context may return NULL if device not support ras feature, so add check before using. Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: enable S/G display for for recent APUs by defaultYifan Zhang1-33/+15
With S/G display becomes stable, enable S/G display for recent APUs by default rather than white list. v2: explicitly disable sg on pre-CZ chips (Alex) v3: add parens for every clause (Alex) Co-authored-by: Alex Deucher <[email protected]> Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09Documentation/amdgpu: Add FRU attribute detailsLijo Lazar1-0/+19
Add documentation for the newly added manufacturer and fru_id attributes in sysfs. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: Add more FRU field informationLijo Lazar2-3/+51
Add support to read Manufacturer Name and FRU File Id fields. Also add sysfs device attributes for external usage. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: Refactor FRU product informationLijo Lazar9-36/+42
Keep FRU related information together in a separate structure. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: enable FRU device for SMU v13.0.6Yang Wang1-19/+29
v1: enable GFX v9.4.3 FRU device to query board information. v2: use MP1 version to identify different asic Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: update ib start and size alignmentBoyuan Zhang2-12/+13
Update IB starting address alignment and size alignment with correct values for decode and encode IPs. Decode IB starting address alignment: 256 bytes Decode IB size alignment: 64 bytes Encode IB starting address alignment: 256 bytes Encode IB size alignment: 4 bytes Also bump amdgpu driver version for this update. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: add check in validate_only in dml2Gabe Teeger2-0/+4
[what] does_configuration_meet_sw_policies check was not done in the validate_only portion of dml2, so some unsupported modes were passing bw validation, only to fail the same check later in validate_and_build. now we add the check to validate_only. Also add line in dcn35_resource to ensure that value set for enable_windowed_mpo_odm gets passed to dml. [why] Immediate black screen during video playback at 4k144hz. The debugger showed that we were failing validation in dml on every updateplanes(). Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Gabe Teeger <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Port replay vblank logic to DML2Daniel Miess1-3/+22
Update DML2 with replay vblank logic found in DML1. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Daniel Miess <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Modify Pipe Selection for Policy for ODMSaaem Rizvi1-14/+126
[Why] There are certain cases during a transition to ODM that might cause corruption on the display. This occurs when we choose certain pipes in a particular state. [How] We now will store the pipe indexes of the any pipes that might be problematic to switch to during an ODM transition, and only use them as a last resort. Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Saaem Rizvi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: correct dml2 input and dlg_refclkCharlene Liu2-6/+9
dc->dml2_options.use_native_pstate_optimization flag will make driver use dcn32 legacy_svp_drr related tuning. Set this to false fixed the stutter underflow issue also based on HW suggest disable ODM by default and let DML choose it. Reviewed-by: Zhan Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Fix Chroma Surface height/width initializationSung Joon Kim1-2/+2
[why] Surface height/width for Chroma has another variable that it should be intialized to, chroma_size. Fixing this will help pass DML2.0 validation for YCbCr420 tests, DCHB006.109,129, DCHB014.011,012. [how] Assign SurfaceHeight/WidthC to chroma_size.height/width Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Move stereo timing check to helperTaimur Hassan3-8/+19
Rework dml2_map_dc_pipes to keep the logic clean. Reviewed-by: Chaitanya Dhere <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Split pipe for stereo timingsTaimur Hassan1-0/+11
[Why & How] DML2 did not carry over DML1 logic that splits pipe for stero timings. Pipe splitting is needed in this case to pass stereo tests. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Use fixed DET Buffer SizeSung Joon Kim3-10/+16
[why] Regression from DML1.0 where we use differen DET buffer sizes for each pipe. From the spec, we need to use DET buffer size of 384 kb for each pipe [how] Ensure to use 384 kb DET buffer sizes for each available pipe. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Handle multiple streams sourcing same surfaceSung Joon Kim3-32/+53
[why] There are cases where more than 1 stream can be mapped to the same surface. DML2.0 does not seem to handle these cases. [how] Make sure to account for the stream id when deriving the plane id. By doing this, each plane id will be unique based on the stream id. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Add z8_marks in dmlCharlene Liu5-0/+9
Add z8 watermarks to struct for later ASIC use. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Add DCN35 DML2 supportQingqing Zhuo5-7/+110
Enable DML2 for DCN35. Changes since V1: - Remove hard coded values Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Roman Li <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Introduce DML2Qingqing Zhuo36-4/+19572
DC is transitioning from DML to DML2, and this commit introduces all the required changes for some of the already available ASICs and adds the required code infra to support new ASICs under DML2. DML2 is also a generated code that provides better mode verification and programming models for software/hardware, and it enables a better way to create validation tools. This version is more like a middle step to the complete transition to the DML2 version. Changes since V1: - Alex: Fix typos Changes since V2: - Update DC includes Changes since V3: - Fix 32 bit compilation issues on x86 Changes since V4: - Avoid compilation of DML2 on some not supported 32-bit architecture - Update commit message Co-developed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Co-developed-by: Roman Li <[email protected]> Signed-off-by: Roman Li <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Move dml code under CONFIG_DRM_AMD_DC_FP guardRodrigo Siqueira1-1/+2
For some reason, the dml code is not guarded under CONFIG_DRM_AMD_DC_FP in the Makefile. This commit moves the dml code under the DC_FP guard. Reviewed-by: Qingqing Zhuo <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Move bw_fixed from DML folderRodrigo Siqueira3-10/+8
bw_fixed does not need any FPU operation, and it is used on DCE and DCN. For this reason, this commit moves bw_fixed to the basic folder outside DML. Reviewed-by: Qingqing Zhuo <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Move custom_float from DML folderRodrigo Siqueira3-59/+36
The custom_float file does not have any FPU operation, so it should be inside DML. This commit moves the file to the basic folder. Reviewed-by: Qingqing Zhuo <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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