aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm
AgeCommit message (Collapse)AuthorFilesLines
2023-10-13Revert "drm/amd/display: Hande writeback request from userspace"Alex Hung2-162/+0
This reverts commit cd1a4bc22821eea9a98f1beddd1a8d789989a720. [WHY & HOW] The writeback series cause a regression in thunderbolt display. Signed-off-by: Alex Hung <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13Revert "drm/amd/display: Add writeback enable/disable in dc"Alex Hung2-37/+0
This reverts commit c6d3c7b6309726fbe93cf595d6de326fb8295a64. [WHY & HOW] The writeback series cause a regression in thunderbolt display. Signed-off-by: Alex Hung <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13Revert "drm/amd/display: Fix writeback_info never got updated"Alex Hung1-4/+9
This reverts commit 8a307777c36e15f38c9f23778babcd368144c7d8. [WHY & HOW] The writeback series cause a regression in thunderbolt display. Signed-off-by: Alex Hung <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13Revert "drm/amd/display: Validate hw_points_num before using it"Alex Hung1-3/+0
This reverts commit 58c3b3341cea4f75dc8c003b89f8a6dd8ec55e50. [WHY & HOW] The writeback series cause a regression in thunderbolt display. Signed-off-by: Alex Hung <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13Revert "drm/amd/display: Fix writeback_info is not removed"Alex Hung1-4/+3
This reverts commit 5b89d2ccc8466e0445a4994cb288fc009b565de5. [WHY & HOW] The writeback series cause a regression in thunderbolt display. Signed-off-by: Alex Hung <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13Revert "drm/amd/display: Add writeback enable field (wb_enabled)"Alex Hung2-9/+0
This reverts commit f6893fcb10c7b24526454e465f6ec2563ef044cc. [WHY & HOW] The writeback series cause a regression in thunderbolt display. Signed-off-by: Alex Hung <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13Revert "drm/amd/display: Setup for mmhubbub3_warmup_mcif with big buffer"Alex Hung1-6/+0
This reverts commit 428542d9177286c01ef7a3dbd026eb00567e06b1. [WHY & HOW] The writeback series cause a regression in thunderbolt display. Signed-off-by: Alex Hung <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13Revert "drm/amd/display: Add new set_fc_enable to struct dwbc_funcs"Alex Hung3-29/+0
This reverts commit b79a00a4d4f8fc827ca0fc19e259913a81252f6b. [WHY & HOW] The writeback series cause a regression in thunderbolt display. Signed-off-by: Alex Hung <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13Revert "drm/amd/display: Disable DWB frame capture to emulate oneshot"Alex Hung3-44/+1
This reverts commit 77a66faaccc0455fe30e326e9a997aec8d0abed4. [WHY & HOW] The writeback series cause a regression in thunderbolt display. Signed-off-by: Alex Hung <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/display: Revert "drm/amd/display: Use drm_connector in ↵Alex Hung3-19/+11
create_validate_stream_for_sink" This reverts commit c4c182b5488e8d4a48be3327aab14d778cdfe5e7. After this was commit PCON and USB4 issues were observed. A new fix will be submitted instead. Signed-off-by: Alex Hung <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: Expose ras version & schema infoAsad Kamal2-3/+51
Expose ras table version & schema info to sysfs v2: Updated schema to get poison support info from ras context, removed asic specific checks Signed-off-by: Asad Kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: Read PSPv13 OS version from registerLijo Lazar1-1/+12
PSP OS updates the version information in register. On APUs with PSPv13, PSP OS will already be loaded with SBIOS. Hence use the version register instead of using information in driver binary header. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/display: add missing NULL check for DML2Bob Zhou1-1/+1
Recently, the driver introduce DML2 for future ASIC support. But, some ASIC's hubbub pointer is null before calling. It cause the below null pointer issue, so add null check to fix it. BUG: kernel NULL pointer dereference, address: 0000000000000000 RIP: 0010:dc_create_resource_pool+0xc1/0x2c0 [amdgpu] Call Trace: <TASK> ? show_regs.cold+0x1a/0x1f ? __die_body+0x20/0x70 ? __die+0x2b/0x37 ? page_fault_oops+0x136/0x2c0 ? do_user_addr_fault+0x303/0x660 ? exc_page_fault+0x77/0x170 ? asm_exc_page_fault+0x27/0x30 ? dc_create_resource_pool+0xc1/0x2c0 [amdgpu] ? dc_create_resource_pool+0x243/0x2c0 [amdgpu] dc_create+0x23f/0x6b0 [amdgpu] ? dmi_matches+0xa3/0x200 amdgpu_dm_init+0x2bd/0x22a0 [amdgpu] Fixes: 7966f319c66d ("drm/amd/display: Introduce DML2") Signed-off-by: Bob Zhou <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu/umsch: enable doorbell for umschLang Yu2-2/+3
Program vcn_doorbell_range with vcn_ring0_1. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Veerabadhran Gopalakrishnan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/display: make dc_set_power_state() return type `void` againMario Limonciello3-17/+8
As dc_set_power_state() no longer allocates memory, it's not necessary to have return types and check return code as it can't fail anymore. Change it back to `void`. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/display: Destroy DC context while keeping DML and DML2Mario Limonciello2-37/+12
If there is memory pressure at suspend time then dynamically allocating a large structure as part of DC suspend code will fail. Instead re-use the same structures and clear all members except those that should be maintained. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2362 Acked-by: Alex Deucher <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/display: Catch errors from drm_atomic_helper_suspend()Mario Limonciello1-0/+2
drm_atomic_helper_suspend() can return PTR_ERR(), in which case the error gets stored into `dm->cached_state`. This can cause failures during resume. Catch the error during suspend and fail the suspend instead. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2362 Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd: Split up UVD suspend into prepare and suspend stepsMario Limonciello7-4/+49
amdgpu_uvd_suspend() allocates memory and copies objects into that allocated memory. This fails under memory pressure. Instead move majority of this code into a prepare step when swap can still be allocated. Reviewed-by: Christian König <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd: Add concept of running prepare_suspend() sequence for IP blocksMario Limonciello2-1/+12
If any IP blocks allocate memory during their hw_fini() sequence this can cause the suspend to fail under memory pressure. Introduce a new phase that IP blocks can use to allocate memory before suspend starts so that it can potentially be evicted into swap instead. Reviewed-by: Christian König <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd: Evict resources during PM ops prepare() callbackMario Limonciello3-8/+34
Linux PM core has a prepare() callback run before suspend. If the system is under high memory pressure, the resources may need to be evicted into swap instead. If the storage backing for swap is offlined during the suspend() step then such a call may fail. So move this step into prepare() to move evict majority of resources and update all non-pmops callers to call the same callback. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2362 Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: enable GFX IP v11.5.0 CG and PG supportLi Ma3-3/+23
Add CG support for GFX/MC/HDP/ATHUB/IH/BIF. Add PG support for GFX. Signed-off-by: Li Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: add support to power up/down UMSCH by SMULang Yu2-0/+27
Power up/down UMSCH by SMU. Signed-off-by: Lang Yu <[email protected]> Acked-by: Leo Liu <[email protected]> Acked-by: Veerabadhran Gopalakrishnan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: add power up/down UMSCH ppt callbackLang Yu3-1/+24
Add ppt callback to power up/down UMSCH. v2: squash in updates (Alex) Signed-off-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: add support to powerup VPE by SMULang Yu3-0/+31
Powerup VPE by SMU. Signed-off-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu/discovery: add SMU 14 supportLi Ma3-0/+12
add smu 14 into the IP discovery list. Signed-off-by: Li Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/swsmu: add smu14 ip supportKenneth Feng10-3/+3110
Add initial swSMU support for smu 14 series ASIC. v2: squash in build fixes and updates (Li Ma) fix warnings (Alex) v3: squash in updates (Alex) v4: squash in updates (Alex) v5: squash in avg/current power updates (Alex) Signed-off-by: Li Ma <[email protected]> Signed-off-by: Kenneth Feng <[email protected]> Signed-off-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/swsmu: add smu v14_0_0 pmfw if fileLi Ma1-0/+156
Add initial smu v14_0_0 pmfw if file v2: squash in updates (Alex) Signed-off-by: Li Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/swsmu: add smu v14_0_0 ppsmc fileLi Ma1-0/+142
Add initial smu v14_0_0 ppsmc file v2: squash in updates (Alex) v3: squash in updates (Alex) Signed-off-by: Li Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu/swsmu: add smu v14_0_0 driver if fileLi Ma1-0/+281
Add initial smu v14_0_0 driver if file v2: squash in updates (Alex) v3: update interface (Alex) Signed-off-by: Li Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu/umsch: power on/off UMSCH by DLDOLang Yu1-0/+26
VCN 4.0.5 uses DLDO. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Veerabadhran Gopalakrishnan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu/umsch: fix psp frontdoor loadingLang Yu3-88/+72
These changes are missed in rebase. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Veerabadhran Gopalakrishnan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: Increase IP discovery region sizeLijo Lazar1-1/+1
IP discovery region has increased to > 8K on some SOCs.Maximum reserve size is upto 12K, but not used. For now increase to 10K. Signed-off-by: Lijo Lazar <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/pm: Use gpu_metrics_v1_4 for SMUv13.0.6Asad Kamal1-24/+41
Use gpu_metrics_v1_4 for SMUv13.0.6 to fill gpu metric info v3: Removed filling gpu metric instantaneous pcie bw Signed-off-by: Asad Kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/pm: Add gpu_metrics_v1_4Asad Kamal2-0/+79
Add new gpu_metrics_v1_4 to acquire XGMI data transfer, pcie bandwidth & Clock lock status v2: Add pcie error counter to gpu metric table v1_4 Signed-off-by: Asad Kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/pm: Update metric table for smu v13_0_6Asad Kamal1-1/+5
Update pmfw metric table to include xgmi transfer data and pci instantaneous bandwidth for smu v13_0_6 v2: Updated metric table version v3: Removed inst pcie bw with alignment to metrics table version 8 Signed-off-by: Asad Kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: Return -EINVAL when MMSCH init status incorrectLin.Cao1-1/+4
Return -EINVAL when MMSCH init fail which can be handle by function amdgpu_device_reset_sriov correctly. Signed-off-by: Lin.Cao <[email protected]> Reviewed-by: Jingwen Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/pm: wait for completion of the EnableGfxImu commandTim Huang1-2/+10
Wait for completion of sending the EnableGfxImu message when using the PSP FW loading. Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu/vpe: fix insert_nop opsLang Yu1-4/+5
Avoid infinite loop when count is 0. This is missed in rebase. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: Address member 'gart_placement' not described in ↵Srinivasan Shanmugam1-0/+1
'amdgpu_gmc_gart_location' Fixes the below: drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c:274: warning: Function parameter or member 'gart_placement' not described in 'amdgpu_gmc_gart_location' Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Cc: "Pan, Xinhui" <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu/vpe: align with mcbp changesLang Yu1-1/+1
MCBP is decided by adev->gfx.mcbp now. This is missed in rebase. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu/vpe: remove IB end boundary requirementLang Yu1-19/+1
Remove IB end boundary requirement, VPE has no such limitions, use existing amdgpu_ring_generic_pad_ib() instead. This is missed in rebase. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: Improve MES responsiveness during oversubscriptionJay Cornwall1-0/+1
When MES is oversubscribed it may not frequently check for new command submissions from driver if the scheduling load is high. Response latency as high as 5 seconds has been observed. Enable a flag which adds a check for new commands between scheduling quantums. Signed-off-by: Jay Cornwall <[email protected]> Cc: Alexandru Tudor <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/bridge: megachips-stdpxxxx-ge-b850v3-fw: switch to drm_do_get_edid()Ian Ray1-48/+9
Migrate away from custom EDID parsing and validity checks. Note: This is a follow-up to the original RFC by Jani [1]. The first submission in this series should have been marked v2. [1] https://patchwork.freedesktop.org/patch/msgid/[email protected] Co-developed-by: Jani Nikula <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Signed-off-by: Ian Ray <[email protected]> Reviewed-by: Robert Foss <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-13drm/i915/dsb: Re-instate DSB for LUT updatesVille Syrjälä1-3/+0
With all the known issues sorted out we can start to use DSB to load the LUTs. Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-13drm/i915/dsb: Correct DSB command buffer cache coherency settingsVille Syrjälä1-4/+11
The display engine does not snoop the caches so we should mark the DSB command buffer as I915_CACHE_NONE. i915_gem_object_create_internal() always gives us I915_CACHE_LLC on LLC platforms. And to make things 100% correct we should also clflush at the end, if necessary. Note that currently this is a non-issue as we always write the command buffer through a WC mapping, so a cache flush is not actually needed. But we might actually want to consider a WB mapping since we also end up reading from the command buffer (in the indexed reg write handling). Either that or we should do something else to avoid those reads (might actually be even more sensible on DGFX since we end up reading over PCIe). But we should measure the overhead first... Anyways, no real harm in adding the belts and suspenders here so that the code will work correctly regardless of how we map the buffer. If we do get a WC mapping (as we request) i915_gem_object_flush_map() will be a nop. Well, apart form a wmb() which may just flush the WC buffer a bit earlier than would otherwise happen (at the latest the mmio accesses would trigger the WC flush). Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Uma Shankar <[email protected]>
2023-10-13drm/i915/dsb: Allocate command buffer from local memoryVille Syrjälä1-1/+6
Using system memory for the DSB command buffer doesn't appear to work. On DG2 it seems like the hardware internally replaces the actual memory reads with zeroes, and so we end up executing a bunch of NOOPs instead of whatever commands we put in the buffer. To determine that I measured the time it takes to execute the instructions, and the results are always more or less consistent with executing a buffer full of NOOPs from local memory. Another theory I considered was some kind of cache coherency issue. Looks like i915_gem_object_pin_map_unlocked() will in fact give you a WB mapping for system memory on DGFX regardless of what mapping mode was requested (WC in case of the DSB code). But clflush did not change the behaviour at all, so that theory seems moot. On DG1 it looks like the hardware might actually be fetching data from system memory as the logs indicate that we just get underruns. But that is equally bad, so doesn't look like we can really use system memory on DG1 either. Thus always allocate the DSB command buffer from local memory on discrete GPUs. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Uma Shankar <[email protected]>
2023-10-13drm/i915/lnl: Remove watchdog timers for PSRMika Kahola1-3/+7
Watchdog timers for Lunarlake HW were removed for PSR/PSR2 The patch removes the use of these timers from the driver code. BSpec: 69895 v2: Reword commit message (Ville) Drop HPD mask from LNL (Ville) Revise masking logic (Jouni) v3: Revise commit message (Ville) Revert HPD mask removal as irrelevant for this patch (Ville) Signed-off-by: Mika Kahola <[email protected]> Reviewed-by: Jouni Högander <[email protected]> Signed-off-by: Jouni Högander <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-13pwm: Manage owner assignment implicitly for driversUwe Kleine-König1-1/+0
Instead of requiring each driver to care for assigning the owner member of struct pwm_ops, handle that implicitly using a macro. Note that the owner member has to be moved to struct pwm_chip, as the ops structure usually lives in read-only memory and so cannot be modified. The upside is that new low level drivers cannot forget the assignment and save one line each. The pwm-crc driver didn't assign .owner, that's not a problem in practice though as the driver cannot be compiled as a module. Acked-by: Andy Shevchenko <[email protected]> # Intel LPSS Reviewed-by: Florian Fainelli <[email protected]> # pwm-{bcm,brcm}*.c Acked-by: Jernej Skrabec <[email protected]> # sun4i Acked-by: Andi Shyti <[email protected]> Acked-by: Nobuhiro Iwamatsu <[email protected]> # pwm-visconti Acked-by: Heiko Stuebner <[email protected]> # pwm-rockchip Acked-by: Michael Walle <[email protected]> # pwm-sl28cpld Acked-by: Neil Armstrong <[email protected]> # pwm-meson Reviewed-by: Linus Walleij <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Uwe Kleine-König <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2023-10-13Merge tag 'amd-drm-fixes-6.6-2023-10-11' of ↵Dave Airlie3-1/+8
https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-6.6-2023-10-11: amdgpu: - Seemless boot fix - Fix TTM BO resource check - SI fix for doorbell handling Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-13Merge tag 'drm-msm-fixes-2023-10-07' of ↵Dave Airlie5-23/+42
https://gitlab.freedesktop.org/drm/msm into drm-fixes Fixes for v6.6-rc5 - fix to not reset the PHY everytime we start link training but only do it if link training fails. Without this, the PLL unlocked interrupt fires causing "Unexpected DP AUX IRQ 0x01000000 when not busy" spam in the logs since last 2-3 cycles - correct the highest bank bit to match downstream device tree for msm8998 - skip the video mode wait if the timing engine is not enabled. This was introduced after pre_enable flag for DSI video mode panels where we would end up waiting for the video mode done interrupt even before enabling timing engine causing error spam and long bootup times. - check the correct return code of irq_of_parse_and_map() in DSI code - avoid overflow issues in the dpu bandwidth calculation . This was exposed for high resolution displays and a critical fix to avoid atomic_check failure - minor fix to add new lines in DP print messages. - Fix to fail atomic_check() if the resolution exceeds max mdp clk. This leads to underflow otherwise if we try to allow that frame. Signed-off-by: Dave Airlie <[email protected]> From: Rob Clark <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGv-HNxQ=VBtZ8geGzYJum9jtManEdbvhcjo_WWF_J9Ziw@mail.gmail.com
Powered by cgit, Gruvboxed by Blaster4385.