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2020-10-26drm/amd/display: adding reading OEM init_data to dcn3Martin Leung1-0/+16
why: missing OEM data to control graphics card functions how: load it into init_data. copied over from dcn2 implementation. copied destruction sequence as well. Signed-off-by: Martin Leung <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: DCN2.1 Disable 48MHz Powerdown Debug OptionSung Lee1-1/+1
[WHY & HOW] Currently disable 48mhz debug option only disables on boot. Need to put option check in update_clocks as well to make it affect more areas. Signed-off-by: Sung Lee <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: 3.2.107Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Add an option to limit max DSC target bpp per sinkNikola Cornij5-13/+27
[Why] Can be used for debug purposes [How] Add max target bpp override field and related handling Signed-off-by: Nikola Cornij <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: [FW Promotion] Release 0.0.37Anthony Koo1-2/+2
| [Header Changes] | - Add GPINT to change timestamping mode for traces Signed-off-by: Anthony Koo <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Define PSR ERROR Status bit VSC_SDPReza Amini1-1/+2
[why] So we can track VSC SDP errors from display [how] Define the bit, and use it in driver logic Signed-off-by: Reza Amini <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Raise DPG height during timing synchronizationTaimur Hassan5-1/+41
[Why] Underflow counter increases in AGM when performing some mode switches due to timing sync, which is a known hardware issue. [How] Temporarily raise DPG height during timing sync so that underflow is not reported. Signed-off-by: Taimur Hassan <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Set WM set A to 0 if full pstate not supportedAlvin Lee1-1/+1
[Why] If full pstate is not supported, we should set WM set A to 0 to prevent any hangs [How] If pstate is not supported, set watermark set A to 0 Signed-off-by: Alvin Lee <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Reverting "Add connector to the state if DSC debugfs is set"Eryk Brol1-42/+0
This reverts commit c44a22b3128d143a66421004b728eed688c21ee6. Reason for revert: Patch introduces performance issues and might cause memory consistency problems with multiple connectors. Signed-off-by: Eryk Brol <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Source minimum HBlank supportAshley Thomas14-7/+49
[Why] Some sink devices wish to have access to the minimum HBlank supported by the ASIC. [How] Make the ASIC minimum HBlank available in Source Device information address 0x340. Signed-off-by: Ashley Thomas <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: enable odm + full screen mpo on dcn21Dmytro Laktyushkin4-8/+52
[WHY & HOW] Enable ODM Combine + Fullscreen MPO on DCN2.1 For lower power consumption in video use cases. Signed-off-by: Dmytro Laktyushkin <[email protected]> Signed-off-by: Sung Lee <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: add dcn21 bw validationDmytro Laktyushkin3-2/+122
[Why&How] Create a separate dcn21_fast_validate_bw function for dcn21. Signed-off-by: Dmytro Laktyushkin <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/display: Add Bounding Box State for Low DF PState but High Voltage StateSung Lee1-18/+53
[WHY] DF PState and Voltage State are coupled such that one cannot be raised without raising the other. This uses more power than is necessary in high bandwidth scenarios. [HOW] Add logic to create a new bounding box state that allows for DF PState to be low while Voltage State is high. Watermarks vlevel calculation logic was also udpated to assume state 1 contains the new optimized state. Signed-off-by: Sung Lee <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amdgpu: nuke amdgpu_vm_bo_split_mapping v2Christian König1-103/+79
Merge the functionality mostly into amdgpu_vm_bo_update_mapping. This way we can even handle small contiguous system pages without to much extra CPU overhead. v2: fix typo, keep the cursor as it is for now Signed-off-by: Christian König <[email protected]> Reviewed-by: Madhav Chauhan <[email protected]> (v1) Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amdgpu: increase the reserved VM size to 2MBChristian König1-2/+2
Ideally this should be a multiple of the VM block size. 2MB should at least fit for Vega/Navi. Signed-off-by: Christian König <[email protected]> Reviewed-by: Madhav Chauhan <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amd/pm: update driver if version for dimgrey_cavefishTao Zhou1-1/+1
Per PMFW 59.9.0. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amdgpu: added support for psp fw attestationJohn Clements7-20/+250
loaded fw can be queried from sys fs interface Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/amdgpu: enable IP discovery for vangoghXiaomeng Hou1-4/+0
enable IP discovery for vangogh. Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Xiaomeng Hou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-26drm/ttm: merge ttm_dma_tt back into ttm_ttChristian König14-125/+103
It makes no difference to kmalloc if the structure is 48 or 64 bytes in size. Signed-off-by: Christian König <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/396950/
2020-10-26drm/ttm: make num_pages uint32_tChristian König3-8/+8
We can still allocate 16TiB with that. Signed-off-by: Christian König <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/396946/
2020-10-26drm/ttm: move swapin out of page alloc backendChristian König3-16/+8
This is not related to allocating the backing store in any way. Signed-off-by: Christian König <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/396947/
2020-10-26drm/ttm: nuke ttm_tt_set_(un)populated againChristian König6-13/+7
Neither page allocation backend nor the driver should mess with that. Signed-off-by: Christian König <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Madhav Chauhan <[email protected]> Link: https://patchwork.freedesktop.org/patch/396948/
2020-10-26drm/v3d: Fix double free in v3d_submit_cl_ioctl()Dan Carpenter1-1/+0
Originally this error path used to leak "bin" but then we accidentally applied two separate commits to fix it and ended up with a double free. Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20201026094905.GA1634423@mwanda
2020-10-26drm/sun4i: frontend: Fix the scaler phase on A33Maxime Ripard1-1/+1
The A33 has a different phase parameter in the Allwinner BSP on the channel1 than the one currently applied. Fix this. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-26drm/sun4i: frontend: Reuse the ch0 phase for RGB formatsMaxime Ripard1-3/+5
When using the scaler on the A10-like frontend with single-planar formats, the current code will setup the channel 0 filter (used for the R or Y component) with a different phase parameter than the channel 1 filter (used for the G/B or U/V components). This creates a bleed out that keeps repeating on of the last line of the RGB plane across the rest of the display. The Allwinner BSP either applies the same phase parameter over both channels or use a separate one, the condition being whether the input format is YUV420 or not. Since YUV420 is both subsampled and multi-planar, and since YUYV is subsampled but single-planar, we can rule out the subsampling and assume that the condition is actually whether the format is single or multi-planar. And it looks like applying the same phase parameter over both channels for single-planar formats fixes our issue, while we keep the multi-planar formats working properly. Reported-by: Taras Galchenko <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-26drm/sun4i: frontend: Rework a bit the phase dataMaxime Ripard2-31/+9
The scaler filter phase setup in the allwinner kernel has two different cases for setting up the scaler filter, the first one using different phase parameters for the two channels, and the second one reusing the first channel parameters on the second channel. The allwinner kernel has a third option where the horizontal phase of the second channel will be set to a different value than the vertical one (and seems like it's the same value than one used on the first channel). However, that code path seems to never be taken, so we can ignore it for now, and it's essentially what we're doing so far as well. Since we will have always the same values across each components of the filter setup for a given channel, we can simplify a bit our frontend structure by only storing the phase value we want to apply to a given channel. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-26Merge remote-tracking branch 'drm-misc/drm-misc-next-fixes' into drm-misc-fixesMaxime Ripard1-8/+17
We have a few leftovers from the merge window period in drm-misc-next-fixes, let's bring them into drm-misc-fixes Signed-off-by: Maxime Ripard <[email protected]>
2020-10-26drm/imx: dw_hdmi-imx: remove empty encoder_disable callbackPhilipp Zabel1-5/+0
This has not been required since commit 75229eca569f ("drm: Make drm_encoder_helper_funcs optional"). Signed-off-by: Philipp Zabel <[email protected]>
2020-10-26drm/imx: drop explicit drm_mode_config_cleanupPhilipp Zabel1-5/+5
Use drmm_mode_config_init() and drop the explicit calls to drm_mode_config_cleanup(). Signed-off-by: Philipp Zabel <[email protected]> Acked-by: Daniel Vetter <[email protected]>
2020-10-26drm/imx: imx-tve: remove redundant enable trackingPhilipp Zabel1-12/+4
The DRM core already takes care that encoder enable and disable calls are balanced. Signed-off-by: Philipp Zabel <[email protected]>
2020-10-26drm/imx: imx-tve: use regmap fast_io spinlockPhilipp Zabel1-21/+1
Replace the custom spinlock with the fast_io spinlock provided by regmap. Signed-off-by: Philipp Zabel <[email protected]>
2020-10-26drm/imx: dw_hdmi-imx: use imx_drm_encoder_parse_ofPhilipp Zabel1-9/+3
This is the same code and comment that is already shared by imx-ldb, imx-tve, and parallel-display in imx_drm_encoder_parse_of(). Signed-off-by: Philipp Zabel <[email protected]> Reviewed-by: Sam Ravnborg <[email protected]>
2020-10-24Merge tag 'armsoc-drivers' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms. A bulk of this is smaller fixes or cleanups, but some of the new material this time around is: - Support for Nvidia Tegra234 SoC - Ring accelerator support for TI AM65x - PRUSS driver for TI platforms - Renesas support for R-Car V3U SoC - Reset support for Cortex-M4 processor on i.MX8MQ There are also new socinfo entries for a handful of different SoCs and platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (131 commits) drm/mediatek: reduce clear event soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api soc: mediatek: cmdq: add jump function soc: mediatek: cmdq: add write_s_mask value function soc: mediatek: cmdq: add write_s value function soc: mediatek: cmdq: add read_s function soc: mediatek: cmdq: add write_s_mask function soc: mediatek: cmdq: add write_s function soc: mediatek: cmdq: add address shift in jump soc: mediatek: mtk-infracfg: Fix kerneldoc soc: amlogic: pm-domains: use always-on flag reset: sti: reset-syscfg: fix struct description warnings reset: imx7: add the cm4 reset for i.MX8MQ dt-bindings: reset: imx8mq: add m4 reset reset: Fix and extend kerneldoc reset: reset-zynqmp: Added support for Versal platform dt-bindings: reset: Updated binding for Versal reset driver reset: imx7: Support module build soc: fsl: qe: Remove unnessesary check in ucc_set_tdm_rxtx_clk soc: fsl: qman: convert to use be32_add_cpu() ...
2020-10-23drm/i915/dg1: invert HPD pinsClinton A Taylor2-0/+13
HPD pins are inverted for DG1 platform. Bspec: 49956 Cc: José Roberto de Souza <[email protected]> Cc: Matt Roper <[email protected]> Signed-off-by: Clinton A Taylor <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-23drm/i915/dg1: add hpd interrupt handlingLucas De Marchi3-7/+51
DG1 has one more combo phy port, no TC and all irq handling goes through SDE, like for MCC. v2: Also change intel_hpd_pin_default() to include DG1 mapping v3, v4: Rebase on hpd refactor Cc: Ville Syrjälä <[email protected]> Cc: Anshuman Gupta <[email protected]> Cc: José Roberto de Souza <[email protected]> Cc: Imre Deak <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-23drm/i915/tgl/psr: Fix glitches when doing frontbuffer modificationsJosé Roberto de Souza1-1/+15
Writes to CURSURFLIVE in TGL are causing IOMMU errors and visual glitches that are often reproduced when executing CPU intensive workloads while a eDP 4K panel is attached. Manually exiting PSR causes the frontbuffer to be updated without glitches and the IOMMU errors are also gone but this comes at the cost of less time with PSR active. So using this workaround until this issue is root caused and a better fix is found. The current code is already ready to enable PSR after this exit if there is not other frontbuffer modifications. Adding a new if block in psr_force_hw_tracking_exit() instead of reuse the else/gen8- block because the plan is to revert this workaround as soon as a better solution is found. Cc: Gwan-gyeong Mun <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Tested-by: Gwan-gyeong Mun <[email protected]> Reviewed-by: Gwan-gyeong Mun <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-10-23Merge tag 'drm-next-2020-10-23' of git://anongit.freedesktop.org/drm/drmLinus Torvalds29-85/+522
Pull more drm fixes from Dave Airlie: "This should be the last round of things for rc1, a bunch of i915 fixes, some amdgpu, more font OOB fixes and one ttm fix just found reading code: fbcon/fonts: - Two patches to prevent OOB access ttm: - fix for evicition value range check amdgpu: - Sienna Cichlid fixes - MST manager resource leak fix - GPU reset fix amdkfd: - Luxmark fix for Navi1x i915: - Tweak initial DPCD backlight.enabled value (Sean) - Initialize reserved MOCS indices (Ayaz) - Mark initial fb obj as WT on eLLC machines to avoid rcu lockup (Ville) - Support parsing of oversize batches (Chris) - Delay execlists processing for TGL (Chris) - Use the active reference on the vma during error capture (Chris) - Widen CSB pointer (Chris) - Wait for CSB entries on TGL (Chris) - Fix unwind for scratch page allocation (Chris) - Exclude low patches of stolen memory (Chris) - Force VT'd workarounds when running as a guest OS (Chris) - Drop runtime-pm assert from vpgu io accessors (Chris)" * tag 'drm-next-2020-10-23' of git://anongit.freedesktop.org/drm/drm: (31 commits) drm/amdgpu: correct the cu and rb info for sienna cichlid drm/amd/pm: remove the average clock value in sysfs drm/amd/pm: fix pp_dpm_fclk Revert drm/amdgpu: disable sienna chichlid UMC RAS drm/amd/pm: fix pcie information for sienna cichlid drm/amdkfd: Use same SQ prefetch setting as amdgpu drm/amd/swsmu: correct wrong feature bit mapping drm/amd/psp: Fix sysfs: cannot create duplicate filename drm/amd/display: Avoid MST manager resource leak. drm/amd/display: Revert "drm/amd/display: Fix a list corruption" drm/amdgpu: update golden setting for sienna_cichlid drm/amd/swsmu: add missing feature map for sienna_cichlid drm/amdgpu: correct the gpu reset handling for job != NULL case drm/amdgpu: add rlc iram and dram firmware support drm/amdgpu: add function to program pbb mode for sienna cichlid drm/i915: Drop runtime-pm assert from vgpu io accessors drm/i915: Force VT'd workarounds when running as a guest OS drm/i915: Exclude low pages (128KiB) of stolen from use drm/i915/gt: Onion unwind for scratch page allocation failure drm/ttm: fix eviction valuable range check. ...
2020-10-23drm/amd/display: Fixed panic during seamless boot.David Galiffi1-1/+2
[why] get_pixel_clk_frequency_100hz is undefined in clock_source_funcs. [how] set function pointer: ".get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz" Signed-off-by: David Galiffi <[email protected]> Reviewed-by: Bhawanpreet Lakha <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: Fix size calculation when init onchip memoryxinhui pan1-2/+2
Size is page count here. Reviewed-by: Christian König <[email protected]> Signed-off-by: xinhui pan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu_dm: fix a typoMauro Carvalho Chehab2-4/+4
dm_comressor_info -> dm_compressor_info The kernel-doc markup is right, but the struct itself and their references contain a typo. Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: fix some kernel-doc markupsMauro Carvalho Chehab2-2/+2
Some functions have different names between their prototypes and the kernel-doc markup. Acked-by: Christian König <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23amdgpu: fix a few kernel-doc markup issuesMauro Carvalho Chehab1-3/+5
A kernel-doc markup can't be mixed with a random comment, as it causes parsing problems. While here, change an invalid kernel-doc markup into a common comment. Acked-by: Christian König <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: During compute disable GFXOFF for Sienna_CichlidHarish Kasiviswanathan1-0/+7
Workaround to fix the soft hang observed in certain compute applications. Acked-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: don't map BO in reserved regionMadhav Chauhan1-0/+10
2MB area is reserved at top inside VM. Suggested-by: Christian König <[email protected]> Signed-off-by: Madhav Chauhan <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu/display: add MALL support (v2)Bhawanpreet Lakha7-1/+110
Enable Memory Access at Last Level (MALL) feature for display. v2: squash in 64 bit division fixes Signed-off-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: add support to configure MALL for sienna_cichlid (v2)Likun Gao3-2/+6
Enable Memory Access at Last Level (MALL) feature for sienna_cichlid. v2: drop module option. We need to add UAPI so userspace can request MALL per buffer. Reviewed-by: Christian König <[email protected]> Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: add GC 10.3 NOALLOC registersAlex Deucher3-0/+36
This adds the NOALLOC registers. Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: remove unneeded breakTom Rix7-43/+0
A break is not needed if it is preceded by a return or break Reviewed-by: Harry Wentland <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: add DID for navi10 blockchain SKUTianci.Yin1-0/+1
Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-23drm/amdgpu: disable DCN and VCN for navi10 blockchain SKU(v3)Tianci.Yin1-2/+12
The blockchain SKU has no display and video support, remove them. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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