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path: root/drivers/gpu/drm
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2021-08-09drm/amd/display: add authentication_complete in hdcp outputWenjing Liu7-79/+93
[why] DM needs to be notified when hdcp module has completed authentication attempt. Reviewed-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: Add AUX I2C tracing.Ashley Thomas1-9/+183
[Why] Developers can find it useful if the driver can produce AUX traces without special equipment. [How] Add AUX tracing. Reviewed-by: Zhan Liu <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Ashley Thomas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: Correct comment styleRoy Chan1-1/+1
Acked-by: Anson Jacob <[email protected]> Signed-off-by: Roy Chan <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: fix incorrect CM/TF programming sequence in dwbRoy Chan1-26/+64
[How] the programming sequeune was for old asic. the correct programming sequeunce should be similar to the one used in mpc. the fix is copied from the mpc programming sequeunce. Reviewed-by: Anthony Koo <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Roy Chan <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: refactor the cursor programing codesRoy Chan1-41/+65
Acked-by: Anson Jacob <[email protected]> Signed-off-by: Roy Chan <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: refactor the codes to centralize the stream/pipe checking logicRoy Chan1-21/+41
Acked-by: Anson Jacob <[email protected]> Signed-off-by: Roy Chan <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: fix missing writeback disablement if plane is removedRoy Chan2-7/+19
[Why] If the plane has been removed, the writeback disablement logic doesn't run [How] fix the logic order Acked-by: Anson Jacob <[email protected]> Signed-off-by: Roy Chan <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/display: Remove invalid assert for ODM + MPC caseEric Bernstein1-1/+0
Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Eric Bernstein <[email protected]> Cc: [email protected] Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amd/amdgpu: skip locking delayed work if not initialized.YuBiao Wang1-1/+2
When init failed in early init stage, amdgpu_object has not been initialized, so hasn't the ttm delayed queue functions. Signed-off-by: YuBiao Wang <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/amdgpu: Extend full access wait time in guestVictor Zhao1-4/+12
- Extend wait time and add retry, currently 6s * 2times - Change timing algorithm Signed-off-by: Victor Zhao <[email protected]> Signed-off-by: Peng Ju Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-08-09drm/mediatek: Test component initialization earlier in the function ↵Dafna Hirschfeld1-8/+8
mtk_drm_crtc_create The initialization is currently tested in a later stage in the function for no reason. In addition, the test '!comp' will never fail since comp is set with the '&' operator. Instead, test if a comp was not initialized by testing "!comp->dev". Signed-off-by: Dafna Hirschfeld <[email protected]> Signed-off-by: Chun-Kuang Hu <[email protected]>
2021-08-09drm/mediatek: Add support for main DDP path on MT8167Fabien Parent1-0/+38
Add the main (DSI) drm display path for MT8167. Signed-off-by: Fabien Parent <[email protected]> Signed-off-by: Chun-Kuang Hu <[email protected]>
2021-08-09drm/mediatek: Implement mmap as GEM object functionThomas Zimmermann3-46/+14
Moving the driver-specific mmap code into a GEM object function allows for using DRM helpers for various mmap callbacks. The respective mediatek functions are being removed. The file_operations structure fops is now being created by the helper macro DEFINE_DRM_GEM_FOPS(). Signed-off-by: Thomas Zimmermann <[email protected]> Signed-off-by: Chun-Kuang Hu <[email protected]>
2021-08-09drm/i915/gvt: Fix cached atomics setting for Windows VMZhenyu Wang2-0/+3
We've seen recent regression with host and windows VM running simultaneously that cause gpu hang or even crash. Finally bisect to commit 58586680ffad ("drm/i915: Disable atomics in L3 for gen9"), which seems cached atomics behavior difference caused regression issue. This tries to add new scratch register handler and add those in mmio save/restore list for context switch. No gpu hang produced with this one. Cc: [email protected] # 5.12+ Cc: "Xu, Terrence" <[email protected]> Cc: "Bloomfield, Jon" <[email protected]> Cc: "Ekstrand, Jason" <[email protected]> Reviewed-by: Colin Xu <[email protected]> Fixes: 58586680ffad ("drm/i915: Disable atomics in L3 for gen9") Signed-off-by: Zhenyu Wang <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-09drm/xlnx/zynqmp_disp: Fix incorrectly named enum 'zynqmp_disp_layer_id'Lee Jones1-1/+1
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/xlnx/zynqmp_disp.c:101: warning: expecting prototype for enum zynqmp_disp_id. Prototype was for enum zynqmp_disp_layer_id instead Signed-off-by: Lee Jones <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-09drm: xlnx: zynqmp_dpsub: Expose plane ordering to userspaceLaurent Pinchart1-0/+1
While the DPSUB has a fixed plane order, it still makes sense to expose it to userspace to avoid hardcoding assumptions. Do so by adding an immutable zpos property to planes. Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-09drm: xlnx: zynqmp_dpsub: Add global alpha supportLaurent Pinchart1-2/+7
The graphics plane has a global alpha setting. Expose it through the plane's alpha property. Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-09drm: xlnx: zynqmp_dpsub: Fix graphics layer blendingLaurent Pinchart1-1/+11
To display the graphics layer, the global alpha needs to be enabled. Enable it when the graphics plane is enabled (with full opacity), and disable it otherwise. Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-09drm: xlnx: zynqmp_dpsub: Pass disp structure to all internal functionsLaurent Pinchart1-145/+121
The internal functions dealing with the audio/video buffer manager, the blender, and the audio mixer, all receive pointers to the respective objects. Those objects are embedded in the zynqmp_disp structure, and a very small. Treating them as separate objects would require expanding them with back-pointers to the zynqmp_disp in order to access fields such as the device pointer for debug messages, and this isn't worth it. Instead, merge those structures with the zynqmp_disp structure, and pass the zynqmp_disp pointer to all internal functions. Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-09drm: xlnx: zynqmp: Add zynqmp_disp_layer_is_video() to simplify the codeQuanyang Wang1-17/+22
Add a new function zynqmp_disp_layer_is_video() to simplify the code that judges if a layer is the video layer. Acked-by: Paul Cercueil <[email protected]> Signed-off-by: Quanyang Wang <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> [Renamed is_layer_vid() to zynqmp_disp_layer_is_video()]] Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-09drm: xlnx: zynqmp: release reset to DP controller before accessing DP registersQuanyang Wang1-10/+12
When insmod zynqmp-dpsub.ko after rmmod it, system will hang with the error log as below: root@xilinx-zynqmp:~# insmod zynqmp-dpsub.ko [ 88.391289] [drm] Initialized zynqmp-dpsub 1.0.0 20130509 for fd4a0000.display on minor 0 [ 88.529906] Console: switching to colour frame buffer device 128x48 [ 88.549402] zynqmp-dpsub fd4a0000.display: [drm] fb0: zynqmp-dpsubdrm frame buffer device [ 88.571624] zynqmp-dpsub fd4a0000.display: ZynqMP DisplayPort Subsystem driver probed root@xilinx-zynqmp:~# rmmod zynqmp_dpsub [ 94.023404] Console: switching to colour dummy device 80x25 root@xilinx-zynqmp:~# insmod zynqmp-dpsub.ko <hang here> This is because that in zynqmp_dp_probe it tries to access some DP registers while the DP controller is still in the reset state. When running "rmmod zynqmp_dpsub", zynqmp_dp_reset(dp, true) in zynqmp_dp_phy_exit is called to force the DP controller into the reset state. Then insmod will call zynqmp_dp_probe to program the DP registers, but at this moment the DP controller hasn't been brought out of the reset state yet since the function zynqmp_dp_reset(dp, false) is called later and this will result the system hang. Releasing the reset to DP controller before any read/write operation to it will fix this issue. And for symmetry, move zynqmp_dp_reset() call from zynqmp_dp_phy_exit() to zynqmp_dp_remove(). Signed-off-by: Quanyang Wang <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-09drm: xlnx: zynqmp_dpsub: Update dependencies for ZynqMP DPDylan Yip1-0/+2
ZynqMP DP requires the ZynqMP PHY and DPDMA to operate properly. So depend on both the PHY and DPDMA. Signed-off-by: Dylan Yip <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-09drm: xlnx: zynqmp_dpsub: Call pm_runtime_get_sync before setting pixel clockQuanyang Wang1-1/+2
The Runtime PM subsystem will force the device "fd4a0000.zynqmp-display" to enter suspend state while booting if the following conditions are met: - the usage counter is zero (pm_runtime_get_sync hasn't been called yet) - no 'active' children (no zynqmp-dp-snd-xx node under dpsub node) - no other device in the same power domain (dpdma node has no "power-domains = <&zynqmp_firmware PD_DP>" property) So there is a scenario as below: 1) DP device enters suspend state <- call zynqmp_gpd_power_off 2) zynqmp_disp_crtc_setup_clock <- configurate register VPLL_FRAC_CFG 3) pm_runtime_get_sync <- call zynqmp_gpd_power_on and clear previous VPLL_FRAC_CFG configuration 4) clk_prepare_enable(disp->pclk) <- enable failed since VPLL_FRAC_CFG configuration is corrupted From above, we can see that pm_runtime_get_sync may clear register VPLL_FRAC_CFG configuration and result the failure of clk enabling. Putting pm_runtime_get_sync at the very beginning of the function zynqmp_disp_crtc_atomic_enable can resolve this issue. Signed-off-by: Quanyang Wang <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]>
2021-08-08drm/vkms: Use offset-adjusted shadow-plane mappings and outputThomas Zimmermann4-3/+4
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in vkms. Also provide use the offset-adjusted data address for the writeback job's output buffers. Output framebuffers with non-zero offsets now have their content written to the correct location. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/vbox: Use offset-adjusted shadow-plane mappingsThomas Zimmermann1-1/+1
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in vbox. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/udl: Use offset-adjusted shadow-plane mappingThomas Zimmermann1-2/+2
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in udl. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/simpledrm: Use offset-adjusted shadow-plane mappingThomas Zimmermann1-2/+2
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in simpledrm. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/gm12u320: Use offset-adjusted shadow-plane mappingsThomas Zimmermann1-2/+2
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in gm12u320. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/cirrus: Use offset-adjusted shadow-plane mappingsThomas Zimmermann1-2/+2
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in cirrus. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Use offset-adjusted shadow-plane mappingsThomas Zimmermann1-2/+2
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in mgag200. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/hyperv: Use offset-adjusted shadow-plane mappingsThomas Zimmermann1-2/+2
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in hyperv. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/gud: Get offset-adjusted mapping from drm_gem_fb_vmap()Thomas Zimmermann1-2/+3
Pass the data parameter to drm_gem_fb_vmap() to retrieve pointers to the data. This address is different from the mapping addresses for framebuffers with non-zero offsets. Replaces gud's internal computation. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/ast: Use offset-adjusted shadow-plane mappingsThomas Zimmermann1-1/+1
For framebuffers with non-zero offset fields, shadow-plane helpers provide a pointer to the first byte of the contained data. Use it in ast. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/gem: Provide offset-adjusted framebuffer BO mappingsThomas Zimmermann4-4/+19
Add an additional argument to drm_gem_fb_vmap() to return each BO's mapping adjusted by the respective offset. Update all callers. The newly returned values point to the first byite of the data stored in the framebuffer BOs. Drivers that access the BO data should use it. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Compute PLL values during atomic checkThomas Zimmermann2-18/+22
PLL setup can fail if the display mode's clock is not supported by any PLL configuration. Compute the PLL values during atomic check, so that atomic commits can fail at the appropriate time. If successful, use the values in the atomic-update phase. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Introduce custom CRTC stateThomas Zimmermann2-0/+55
Inherit from struct drm_crtc_state by embeding it and providing the rsp callbacks for simple-kms helpers. No functional changes. The new state struct mgag200_crtc_state will hold PLL values for modeset operations. v2: * move the simple-kms changes into a separate patch (Sam) Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/simple-kms: Support custom CRTC stateThomas Zimmermann1-3/+36
Simple KMS helpers already support custom state for planes. Extend the helpers to support custom CRTC state as well. Drivers can set the reset, duplicate and destroy callbacks for the display pipeline's CRTC state and inherit from struct drm_crtc_state by embedding an instance. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Abstract pixel PLL via struct mgag200_pllThomas Zimmermann4-903/+1019
Move all PLL compute and update functions into mgag200_pll.c. No functional changes to the rsp algorithms. Introduce struct mgag200_pll and mgag200_pll_funcs. The data strutures abstract the details of each revision's PLL. Perform calls to compute and update functionality via function pointers. Init the PLL once as part of the driver initialization. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Declare PLL clock constants static constThomas Zimmermann1-44/+31
Move the PLL constants to the RO data section by declaring them as static const. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Split PLL compute function for G200SE by revThomas Zimmermann1-70/+96
The compute function for G200SE pixel PLLs handles two revisions with different algorithms. Split it accordingly to make it readable. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Split PLL compute functions by device typeThomas Zimmermann1-110/+146
Several PLL functions compute values for different device types. Split them up to make the code more readable. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Store values (not bits) in struct mgag200_pll_valuesThomas Zimmermann1-62/+91
The fields in struct mgag200_pll_values currently hold the bits of each register. Store the PLL values instead and let the PLL-update code figure out the bits for each register. Until now, the compute function either stored plain values or register bits in struct mgag200_pll_values. The rsp update function used the values as-is. This made it very hard to correctly interpret the stored values (e.g., for logging or debugging). With the cleanup, the stored values now have a clear meaning. v2: * add a bit more context in the commit message (Sam) Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Introduce separate variable for PLL S parameterThomas Zimmermann1-20/+16
The S parameter is controls the loop filter bandwidth when programming the PLL. It's currently stored as part of P (i.e., the clock divider.) Add a separate variable for S prepares the PLL code for further refactoring. The value of s is currently 0, so it has not yet an effect on the programming. v2: * add a note on the current value of s to commit message Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Split PLL setup into compute and update functionsThomas Zimmermann2-52/+198
The _set_plls() functions compute a pixel clock's PLL values and program the hardware accordingly. This happens during atomic commits. For atomic modesetting, it's better to separate computation and programming from each other. This will allow to compute the PLL value during atomic checks and catch unsupported modes early. Split the PLL setup into a compute and an update functions, and call them one after the other. Computed PLL values are store in struct mgag200_pll_values. There are four parameters for the PLL, m, n, p and s. Every compute function stores a value for each of these parameters, and the rsp update function makes the register bits from them. The values stored by the compute function are either plain values or register bits. An additional change is required to always store plain values. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Remove P_ARRAY_SIZEThomas Zimmermann1-4/+3
Replace P_ARRAY_SIZE by array pre-initializing and ARRAY_SIZE(). No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Return errno codes from PLL compute functionsThomas Zimmermann1-2/+2
Return -EINVAL if there's no PLL configuration for the given pixel clock. The returned errors are currently ignored by the caller, but the errno codes will become useful when the compute functions run during atomic checks. v2: * give a rational for this change (Sam) Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-08drm/mgag200: Select clock in PLL update functionsThomas Zimmermann3-12/+33
Put the clock-selection code into each of the PLL-update functions to make them select the correct pixel clock. Instead of copying the code, introduce a new helper WREG_MISC_MASKED, which does masked writes into <MISC>. Use it from each individual PLL update function. The pixel clock for video output was not actually set before programming the clock's values. It worked because the device had the correct clock pre-set. v2: * don't duplicate <MISC> update code (Sam) Signed-off-by: Thomas Zimmermann <[email protected]> Fixes: db05f8d3dc87 ("drm/mgag200: Split MISC register update into PLL selection, SYNC and I/O") Acked-by: Sam Ravnborg <[email protected]> Cc: Sam Ravnborg <[email protected]> Cc: Emil Velikov <[email protected]> Cc: Dave Airlie <[email protected]> Cc: [email protected] Cc: <[email protected]> # v5.9+ Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-08-07drm/msm/dpu: make dpu_hw_ctl_clear_all_blendstages clear necessary LMsDmitry Baryshkov1-4/+6
dpu_hw_ctl_clear_all_blendstages() clears settings for the few first LMs instead of mixers actually used for the CTL. Change it to clear necessary data, using provided mixer ids. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2021-08-07drm/msm/dpu: add support for alpha blending propertiesDmitry Baryshkov2-16/+37
Add support for alpha blending properties. Setup the plane blend state according to those properties. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2021-08-07drm/msm/dp: update is_connected status base on sink count at dp_pm_resume()Kuogee Hsieh1-3/+14
Currently at dp_pm_resume() is_connected state is decided base on hpd connection status only. This will put is_connected in wrongly "true" state at the scenario that dongle attached to DUT but without hmdi cable connecting to it. Fix this problem by adding read sink count from dongle and decided is_connected state base on both sink count and hpd connection status. Changes in v2: -- remove dp_get_sink_count() cand call drm_dp_read_sink_count() Changes in v3: -- delete status local variable from dp_pm_resume() Changes in v4: -- delete un necessary comment at dp_pm_resume() Fixes: d9aa6571b28ba ("drm/msm/dp: check sink_count before update is_connected status") Signed-off-by: Kuogee Hsieh <[email protected]> Link: https://lore.kernel.org/r/[email protected] Tested-by: Stephen Boyd <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
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