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path: root/drivers/gpu/drm
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2016-02-26drm/sti: add debugfs entries for GDP planesVincent Abriou1-0/+236
Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: add debugfs entries for CURSOR planeVincent Abriou1-0/+79
Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: add debugfs entries for HDA connectorVincent Abriou1-1/+104
Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: add debugfs entries for DVO connectorVincent Abriou1-0/+70
Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: add debugfs entries for HDMI connectorVincent Abriou2-4/+175
Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: add hdmi_mode property for HDMI connectorVincent Abriou2-2/+43
Configures the framer of the HDMI connection. By default starts in HDMI mode and can be swtich to DVI. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: add colorspace property to the HDMI connectorVincent Abriou2-1/+79
Make the value of the colorspace of the HDMI infoframe configurable. HDMI colorspace could be: RGB, YUV422 or YUV444 Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: add HDMI vendor specific infoframeVincent Abriou1-9/+73
Vendor specific infoframe is mandatory for 4K2K resolution. Without this, the HDMI protocol compliance fails. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: reset infoframe transmission when HDMI is stoppedVincent Abriou1-0/+43
Clear all infoframe registers when the HDMI link is stopped. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: HDMI infoframe transmission mode not take into accountVincent Abriou1-1/+1
Set the infoframe transmission mode according to the type of the infoframe. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: reset HD DACS when HDA connector is createdVincent Abriou1-0/+3
Make sure the HD DACS are disabled when the HDA connector is created. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: fix dvo data_enable signalBich Hemon1-16/+35
Modify AWG algorithm in order to handle more than 1023 lines Signed-off-by: Bich Hemon <bich.hemon@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: adjust delay for DVOBich Hemon1-1/+4
Modify delay to display last pixel column on DVO Signed-off-by: Bich Hemon <bich.hemon@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: add missing encoder cleanup for DVO connectorVincent Abriou1-0/+4
Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: fix panel detection for DVO connectorVincent Abriou1-3/+5
The DVO connector is tag as disconnect because of a wrong management of the panel detection. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: do not clip RGB/YUV component value at connector sideVincent Abriou1-8/+6
Disable the clipping mode for hdmi, dvo and hda connectors. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: adapt YUV colorspace in display pipelineBich Hemon2-28/+64
Use BT601 for SD/ED resolution and BT709 for HD resolution Signed-off-by: Bich Hemon <bich.hemon@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: implement atomic_check for the planesVincent Abriou3-168/+270
Atomic update should never fail. Thus all checks must be done in the atomic_check function for each plane (gdp, hqvdp and cursor). Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: force cursor CLUT fetchFabien Dessenne1-7/+4
It may happen that the cursor is displayed with wrong colors which can be explained by a CLUT wrongly fetched at the first display. Fetching the CLUT at each commit (=move) ensures that the right colors are used, at least from the first cursor move. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: GDP cropping fails when we remove 2 pixels horizontallyVincent Abriou1-4/+5
GDP source width should be equal to the destination width to get rid of this issue. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: fallback for GDP scalingBich Hemon1-5/+31
When a GDP gets a scale request (which it does not support), it accepts it but crops or clamps and outputs a warning message. Signed-off-by: Bich Hemon <bich.hemon@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: GDP planes only support RGB formatsBich Hemon1-17/+0
Only RGB formats supported by GDP planes Signed-off-by: Bich Hemon <bich.hemon@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: clarify the skip frame/field messageFabien Dessenne1-2/+2
When a frame or a field is skipped, output a Warning message instead of an Error message. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: awg_utils code cleanupBich Hemon1-21/+12
data_en is a local variable that doesn't need to be set as awg_generate_instr can be called directly with the requested value. Signed-off-by: Bich Hemon <bich.hemon@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: update VTG timing programmingVincent Abriou3-88/+173
This update eases to understand the VTG programming. It also sets a VTG output id for each supported connectors. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
2016-02-26drm/sti: set DRIVER_ATOMIC for stibenjamin.gaignard@linaro.org1-1/+1
sti now support of atomic modesetting so set the flag to enable it. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: fix cursor coordinatesbenjamin.gaignard@linaro.org1-1/+1
fix x/y typo while setting cursor coordinates Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: set CRTC modesetting parametersbenjamin.gaignard@linaro.org1-0/+1
Set CRTC modesetting parameters to avoid warnings in atomic mode. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-26drm/sti: fix potential crash in gdpbenjamin.gaignard@linaro.org1-6/+7
In some cases last_close() could be called before sti_gdp_disable() and make kernel crash because mixer structure has been destroy. Let's gdp keep a reference on vtg to fix that (like it is already done in HQVDP) Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Vincent Abriou <vincent.abriou@st.com>
2016-02-25drm/fsl-dcu: fix register initializationStefan Agner1-2/+2
The layer enumeration start with 0 (0-15 for LS1021a and 0-63 for Vybrid) whereas the register enumeration start from 1 (1-10 for LS1021a and 1-9 for Vybrid). The loop started off from 0 for both iterations and initialized the number of layers inclusive, which is one layer too many. All extensively written registers seem to be unassigned, it seems that the write to those registers did not do any harm in practice. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: use mode flags for hsync/vsync polarityStefan Agner2-3/+9
The current default configuration is as follows: - Invert VSYNC signal (active LOW) - Invert HSYNC signal (active LOW) The mode flags allow to specify the required polarity per mode. Furthermore, none of the current driver settings is actually a standard polarity. This patch applies the current driver default polarities as explicit flags to the display which has been introduced with the driver (NEC WQVGA "nec,nl4827hc19-05b"). The driver now also parses the flags field and applies the configuration accordingly, by using the following values as standard polarities: (e.g. when no flags are specified): - VSYNC signal not inverted (active HIGH) - HSYNC signal not inverted (active HIGH) Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: fix alpha blendingStefan Agner2-12/+23
Fix alpha blending by enabling alpha blending for the whole frame if a color mode with alpha channel is selected (DRM_FORMAT_ARGB*). Also support color modes without alpha channel (DRM_FORMAT_XRGB*) by just not enabling alpha blending on layer level. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: mask all interrupts on initializationStefan Agner1-4/+1
The state of the interrupt mask register on initialization is unknown, e.g. U-Boot could already used the DCU. So depending on the boot loader, the outcome of the interrupt mask register could be different. A defined state is much more preferable. Also, there is no value in keeping interrupts enabled which we don't need. Therefor, mask all interrupts on initialization. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: handle initialization errors properlyStefan Agner1-4/+20
If initialization fails (e.g. due to missing panel node or deferred probe) make sure to roll-back all operations and return the error code. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: avoid memory leak on errorsStefan Agner2-1/+7
Improve error handling during CRTC initialization. Especially avoid memory leaks in the primary plane initialization error path. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: remove regmap return value checksStefan Agner3-188/+99
It is not common to do regmap return value checks, especially not for memory mapped device. We can rule out most error returns since the conditions are static and we know they are ok (e.g. offset aligned to register stride). Also without proper error handling they are not really valuable for the user. Hence remove most of them. The check in the interrupt handler is worth keeping since a volatile register won't be readable in case register caching is still enabled. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm/fsl-dcu: specify volatile registersStefan Agner1-1/+11
Since we are using cached registers, we need to specify volatile registers explicitly to avoid reading their value from the cache. This allows to read the correct interrupt status in fsl_dcu_drm_irq and clear the asserted bits only. Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25drm: fsl-dcu: Fix no fb check bugMeng Yi1-0/+3
For state->fb or state->crtc may be NULL in fsl_dcu_drm_plane_atomic_check function, if so, return 0. Signed-off-by: Meng Yi <meng.yi@nxp.com> Signed-off-by: Jianwei Wang <jianwei.wang.chn@gmail.com> Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-23drm: rcar-du: Add tri-planar memory formats supportLaurent Pinchart2-10/+52
Those formats are supported on Gen3 only. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: Add probe deferral debug messagesLaurent Pinchart1-1/+8
Print a message when the HDMI I2C slave encoder can't be found to help debugging probe deferral issues. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: lvds: Add R-Car Gen3 supportKoji Matsuoka4-48/+123
The LVDS encoder differs slightly in Gen3 SoCs in its PLL configuration. Add support for the Gen3 LVDS PLL parameters and startup procedure. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: lvds: Rename PLLEN bit to PLLONLaurent Pinchart2-2/+2
The bit is named PLLON in the datasheet, rename it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: lvds: Fix PLL frequency-related configurationLaurent Pinchart1-3/+3
The frequency checks don't match the datasheet, fix them. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: lvds: Avoid duplication of clock clamp codeLaurent Pinchart4-10/+18
Replace the duplicate code by a single central function. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: Add R8A7795 device supportLaurent Pinchart8-39/+140
Document the R8A7795-specific DT bindings and support them in the driver. The HDMI and LVDS outputs are currently not supported. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: Output the DISP signal on the ODDF pinLaurent Pinchart2-1/+13
The ODDF signal, output by default on the ODDF pin, isn't used on any board supported in the kernel. As the Gen3 Salvator-X board uses the ODDF pin as a DISP signal, hardcode that configuration in the driver. Use of the ODDF signal will be implemented later through proper DT-based configuration of the DU pins. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: Output the DISP signal on the DISP pinLaurent Pinchart1-1/+1
The DE signal is currently configured to be identical to the DISP signal and is used for the same purpose. To make it clearer that the DISP pin outputs the DISP signal, select it explicitly. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: Support up to 4 CRTCsKoji Matsuoka3-2/+3
The Gen3 R8A7795 DU has 4 CRTCs, support them all. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: Drop LVDS double dependency on OFLaurent Pinchart1-1/+0
LVDS support depends on DRM_RCAR_DU which already depends on OF. Drop the explicit dependency. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: Enable compilation on ARM64Koji Matsuoka1-1/+2
The R8A7795 SoC is ARM64-based and include a DU. Enable driver compilation on ARM64. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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