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2020-01-15drm/vmwgfx: Don't use the HB port if memory encryption is activeThomas Hellstrom1-2/+5
With memory encryption active, the hypervisor typically can't read the guest memory using the HB port, since it is encrypted using a key known only to the guest. In that case fall back to processing 4 bytes at a time using the ordinary backdoor port. The other option would be to use unencrypted bounce buffers for the hypervisor to read out from or write into, but given the limited message sizes it appears more efficient to just fall back to the ordinary backdoor port. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
2020-01-15Merge tag 'drm-intel-next-2020-01-14' of ↵Dave Airlie143-7008/+9021
git://anongit.freedesktop.org/drm/drm-intel into drm-next Final drm/i915 features for v5.6: - DP MST fixes (José) - Fix intel_bw_state memory leak (Pankaj Bharadiya) - Switch context id allocation to xarray (Tvrtko) - ICL/EHL/TGL workarounds (Matt Roper, Tvrtko) - Debugfs for LMEM details (Lukasz Fiedorowicz) - Prefer platform acronyms over codenames in symbols (Lucas) - Tiled and port sync mode fixes for fbdev and DP (Manasi) - DSI panel and backlight enable GPIO fixes (Hans de Goede) - Relax audio min CDCLK requirements on non-GLK (Kai Vehmanen) - Plane alignment and dimension check fixes (Imre) - Fix state checks for PSR (José) - Remove ICL+ clock gating programming (José) - Static checker fixes around bool usage (Ma Feng) - Bring back tests for self-contained headers in i915 (Masahiro Yamada) - Fix DP MST disable sequence (Ville) - Start converting i915 to the new drm device based logging macros (Wambui Karuga) - Add DSI VBT I2C sequence execution (Vivek Kasireddy) - Start using function pointers and ops structs in uc code (Michal) - Fix PMU names to not use colons or dashes (Tvrtko) - TGL media decompression support (DK, Imre) - Split i915_gem_gtt.[ch] to more manageable chunks (Matthew Auld) - Create dumb buffers in LMEM where available (Ram) - Extend mmap support for LMEM (Abdiel) - Selftest updates (Chris) - Hack bump up CDCLK on TGL to avoid underruns (Stan) - Use intel_encoder and intel_connector more instead of drm counterparts (Ville) - Build error fixes (Zhang Xiaoxu) - Fixes related to GPU and engine initialization/resume (Chris) - Support for prefaulting discontiguous objects (Abdiel) - Support discontiguous LMEM object maps (Chris) - Various GEM and GT improvements and fixes (Chris) - Merge pinctrl dependencies branch for the DSI GPIO updates (Jani) - Backmerge drm-next for new logging macros (Jani) Signed-off-by: Dave Airlie <[email protected]> From: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-01-15Merge branch 'linux-5.6' of git://github.com/skeggsb/linux into drm-nextDave Airlie208-7774/+8123
- Rewrite of the ACR (formerly "secure boot") code, both to support Turing, support multiple FW revisions, and to make life easier when having to debug HW/FW bring-up in the future - Support for TU10x graphics engine, TU11x not available yet as FW isn't ready - Proper page 'kind' mappings for Turing - 10-bit LUT support - GP10B (Tegra) fixes - Misc other fixes Signed-off-by: Dave Airlie <[email protected]> From: Ben Skeggs <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/ <CACAvsv5GKasg9-hEUwp9+aHVJg+nbQ0LukXyudgj6=YKu96jWQ@mail.gmail.com
2020-01-15Merge tag 'mediatek-drm-next-5.6' of ↵Dave Airlie12-235/+481
https://github.com/ckhu-mediatek/linux.git-tags into drm-next Mediatek DRM Next for Linux 5.6 This fix non-smooth cursor problem, add cmdq support, add ctm property support and some refinement. Signed-off-by: Dave Airlie <[email protected]> From: CK Hu <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/1578972526.14594.8.camel@mtksdaap41
2020-01-15Merge tag 'drm/tegra/for-5.6-rc1' of ↵Dave Airlie13-344/+501
git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v5.6-rc1 This contains a small set of mostly fixes and some minor improvements. Signed-off-by: Dave Airlie <[email protected]> From: Thierry Reding <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-01-15drm/nouveau/gr/tu10x: initial supportBen Skeggs12-11/+313
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/acr/tu10x: initial supportBen Skeggs6-0/+229
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/core: remove previous versioned fw loaderBen Skeggs4-32/+16
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/secboot: removeBen Skeggs33-4189/+1
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/acr: implement new subdev to replace "secure boot"Ben Skeggs30-47/+2207
ACR is responsible for managing the firmware for LS (Low Secure) falcons, this was previously handled in the driver by SECBOOT. This rewrite started from some test code that attempted to replicate the procedure RM uses in order to debug early Turing ACR firmwares that were provided by NVIDIA for development. Compared with SECBOOT, the code is structured into more individual steps, with the aim of making the process easier to follow/debug, whilst making it possible to support newer firmware versions that may have a different binary format or API interface. The HS (High Secure) binary(s) are now booted earlier in device init, to match the behaviour of RM, whereas SECBOOT would delay this until we try to boot the first LS falcon. There's also additional debugging features available, with the intention of making it easier to solve issues during FW/HW bring-up in the future. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/fb/gp102-: unlock VPR as part of FB initBen Skeggs10-121/+226
We perform memory allocations long before we hit the code in SECBOOT that would unlock the VPR, which could potentially result in memory allocation within the locked region. Run the scrubber binary right after VRAM init to ensure we don't. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/core/memory: add macros to read/write blocks from objectsBen Skeggs1-0/+16
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/secboot: move code to boot LS falcons to subdevsBen Skeggs24-517/+77
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/msgq: rename msgq-related nvkm_msgqueue_queue to ↵Ben Skeggs4-77/+71
nvkm_falcon_msgq Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/msgq: pass explicit message queue pointer to recv()Ben Skeggs9-49/+4
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/msgq: move handling of init message to subdevsBen Skeggs19-265/+202
When the PMU/SEC2 LS FWs have booted, they'll send a message to the host with various information, including the configuration of message/command queues that are available. Move the handling for this to the relevant subdevs. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/msgq: drop nvkm_msgqueue argument to functionsBen Skeggs1-26/+19
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/msgq: switch to falcon queue printk macrosBen Skeggs1-8/+6
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/msgq: simplify msg_queue_pop() error handlingBen Skeggs1-18/+7
We always want at least requested size, make anything less a more direct error condition. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/msgq: remove error handling for msg_queue_open(), it can't failBen Skeggs1-7/+2
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/cmdq: move command generation to subdevsBen Skeggs16-276/+300
This moves the code to generate commands for the ACR unit of the PMU/SEC2 LS firmwares to those subdevs. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/cmdq: rename cmdq-related nvkm_msqqueue_queue to ↵Ben Skeggs2-41/+38
nvkm_falcon_cmdq Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/cmdq: implement a more explicit send() interfaceBen Skeggs5-79/+40
Takes the command queue pointer directly instead of requiring a function to lookup based on an queue type, as well as an explicit timeout value. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/cmdq: drop nvkm_msgqueue argument to functionsBen Skeggs1-22/+18
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/cmdq: switch to falcon queue printk macrosBen Skeggs1-5/+5
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/cmdq: cmd_queue_close always commits, simplify itBen Skeggs1-9/+3
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/cmdq: cmd_queue_push can't fail, remove error handling for itBen Skeggs1-15/+3
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/cmdq: split the condition for queue readiness vs pmu acr ↵Ben Skeggs7-15/+31
readiness This is to allow for proper separation of the LS interface code from the queue handling code. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/qmgr: rename remaining nvkm_msgqueue bits to nvkm_falcon_qmgrBen Skeggs4-30/+32
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/qmgr: support syncronous command submission from common codeBen Skeggs6-34/+31
Functions implementing FW commands had to implement this themselves, let's move that to common code and plumb the return code from callbacks through. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/qmgr: allow arbtrary priv + return code for callbacksBen Skeggs7-38/+65
Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. Arbitrary private data passed to callbacks is to allow for something other than struct nvkm_msgqueue to be passed into the callback (like the pointer to the subdev itself, for example), and the return code will be used where we'd like to detect failure from synchronous messages. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/qmgr: move sequence tracking from nvkm_msgqueue to ↵Ben Skeggs6-53/+55
nvkm_falcon_qmgr Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/msgq: explicitly create message queue from subdevsBen Skeggs9-56/+64
Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. This is an incremental step towards that goal. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/cmdq: explicitly create command queue(s) from subdevsBen Skeggs11-21/+95
Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. This is an incremental step towards that goal. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn/qmgr: explicitly create queue manager from subdevsBen Skeggs8-3/+52
Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. This is an incremental step towards that goal. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn: split msgqueue into multiple piecesBen Skeggs6-410/+474
To make things clearer while modifying the interfaces, split msgqueue into Queue Manager, Command Queue, and Message Queue. There should be no code changes here, these will be done incrementally. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn: add printk macrosBen Skeggs1-0/+9
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn: reset sec2/gsp falcons harderBen Skeggs4-2/+13
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn: specify queue register offsets from subdevBen Skeggs7-26/+29
Also fixes the values for Turing, even though we don't use it yet. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn: specify debug/production register offset from subdevBen Skeggs6-26/+8
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn: specify EMEM address from subdevBen Skeggs5-8/+9
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn: move bind_context WAR out of common codeBen Skeggs5-39/+45
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/flcn: specify FBIF offset from subdevBen Skeggs9-15/+11
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/nvenc: add a stub implementation for the GPUs where it should be ↵Ben Skeggs7-6/+185
supported Mostly so we don't lose info hidden in falcon. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/nvdec/gm107-: add missing engine instancesBen Skeggs1-0/+8
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/nvdec/gm107: rename from gp102 implementationBen Skeggs4-21/+21
NVDEC is available from GM107, and we currently only have a stub implementation anyway, let's make it explicit. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/nvdec: initialise SW state for falcon from constructorBen Skeggs5-25/+23
This will allow us to register the falcon with ACR, and further customise its behaviour by providing the nvkm_falcon_func structure directly. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/nvdec: select implementation based on available fwBen Skeggs4-7/+46
This will allow for further customisation of the subdev depending on what firmware is available. Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/sec2: move interrupt handler to hw-specific moduleBen Skeggs4-21/+31
Signed-off-by: Ben Skeggs <[email protected]>
2020-01-15drm/nouveau/sec2: use falcon funcsBen Skeggs2-9/+6
Signed-off-by: Ben Skeggs <[email protected]>
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