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path: root/drivers/gpu/drm/tegra/dc.h
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2020-07-17drm/tegra: plane: Support horizontal reflectionDmitry Osipenko1-0/+1
Support horizontal reflection mode which will allow to support 180° rotation mode when combined with the vertical reflection. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-07-17drm/tegra: plane: Rename bottom_up to reflect_yDmitry Osipenko1-1/+1
This makes the naming consistent with the DRM core. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2019-10-28drm/tegra: Move IOMMU group into host1x clientThierry Reding1-2/+0
Handling of the IOMMU group attachment is common to all clients, so move the group into the client to simplify code. Signed-off-by: Thierry Reding <[email protected]>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-4/+1
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Enrico Weigelt <[email protected]> Reviewed-by: Kate Stewart <[email protected]> Reviewed-by: Allison Randal <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-09-26drm/tegra: dc: Add Tegra194 supportThierry Reding1-1/+1
The display controllers found on Tegra194 are almost identical to those found on Tegra186. Signed-off-by: Thierry Reding <[email protected]>
2018-05-17drm/tegra: dc: Rename supports_blending to has_legacy_blendingDmitry Osipenko1-1/+1
Older Tegra chips do support blending as well. Rename the SoC info entry .supports_blending to .has_legacy_blending to eliminate the confusion. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2018-05-17drm/tegra: dc: Enable plane scaling filtersDmitry Osipenko1-0/+7
Currently resized plane produces a "pixelated" image which doesn't look nice, especially in a case of a video overlay. Enable scaling filters that significantly improve image quality of a scaled overlay. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2018-05-04drm/tegra: dc: Balance IOMMU group refcountingDmitry Osipenko1-1/+1
Remove unneeded iommu_group_get() and add missing iommu_group_put(), correcting IOMMU group refcount. This is a minor correction / cleanup that doesn't really fix anything because Tegra's IOMMU driver are built-in and hence groups refcounting can't hold IOMMU driver from unloading. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2018-03-15drm/tegra: plane: Support format modifiersThierry Reding1-0/+1
Pass the list of valid format modifiers to planes upon initialization and implement the ->format_mod_supported() callback so that userspace can query for the valid combinations of formats and modifiers. Signed-off-by: Thierry Reding <[email protected]>
2017-12-21drm/tegra: dc: Implement legacy blendingThierry Reding1-0/+12
This implements alpha blending on legacy display controllers (Tegra20, Tegra30 and Tegra114). While it's theoretically possible to support the zpos property to enable userspace to specify the Z-order of each plane individually, this is not currently supported and the same fixed Z- order as previously defined is used. Reverts commit 71835caa00e8 ("drm/tegra: fb: Force alpha formats") since the opaque formats are now supported. Reported-by: Dmitry Osipenko <[email protected]> Fixes: 7772fdaef939 ("drm/tegra: Support ARGB and ABGR formats") Signed-off-by: Thierry Reding <[email protected]>
2017-12-21drm/tegra: dc: Link DC1 to DC0 on Tegra20Dmitry Osipenko1-1/+1
Hardware reset isn't actually broken on Tegra20, but there is a dependency on the first display controller to be taken out of reset for the second to be enabled successfully. Model this dependency using a PM device link. Signed-off-by: Dmitry Osipenko <[email protected]> [[email protected]: minor cleanups, extend commit message] Signed-off-by: Thierry Reding <[email protected]>
2017-12-21drm/tegra: Implement zpos propertyThierry Reding1-0/+2
Implement the standard zpos property for planes on Tegra124 and later. Earlier generations have a different blending unit that needs different programming. Signed-off-by: Thierry Reding <[email protected]>
2017-12-21drm/tegra: dc: Remove redundant spinlockThierry Reding1-1/+0
The spinlock is only used to serialize accesses to the DC_CMD_INT_MASK register. However, this register is accesses either with interrupts masked (in tegra_crtc_atomic_enable()) or protected by the vbl_lock and vblank_time_lock spinlocks of the DRM device. Therefore, these accesses don't need any extra serialization and the lock can be removed. Signed-off-by: Thierry Reding <[email protected]>
2017-12-21drm/tegra: dc: Support more formatsThierry Reding1-2/+18
Also, split up formats into per-SoC lists because not all generations support all of them. Note that the list is now exhaustive for all RGB formats, but not for YUV and indexed formats. Signed-off-by: Thierry Reding <[email protected]>
2017-12-13drm/tegra: sor: Add Tegra186 supportThierry Reding1-2/+3
The SOR found on Tegra186 is very similar to the one found on Tegra210 and earlier. However, due to some changes in the display architecture, some programming sequences have changed and some register have moved around. Signed-off-by: Thierry Reding <[email protected]>
2017-12-13drm/tegra: Support ARGB and ABGR formatsThierry Reding1-0/+2
These formats can easily be supported on all generations of Tegra. Note that the XRGB and XBGR formats that we supported were in fact using the ARGB and ABGR Tegra formats. This happened to work in cases where no alpha was being considered. This change is also a fix for those formats. Signed-off-by: Thierry Reding <[email protected]>
2017-12-13drm/tegra: dc: Add Tegra186 supportThierry Reding1-32/+66
The display architecture has changed in several signifcant ways with the new Tegra186 SoC. Display controllers are a completely different design, but have been given a frontend that simulates the register interface for earlier chips. Unfortunately the frontend isn't completely backwards compatible, so the driver needs parameterization to take the changes into account. One big change is that the total number of display controllers has been increased to three. At the same time the number of planes available has remained constant. However, planes can now be freely assigned between the display controllers, giving applications more flexibility in making the best use of the available resources. Signed-off-by: Thierry Reding <[email protected]>
2017-12-13drm/tegra: Add Tegra186 display hub supportThierry Reding1-0/+114
The display architecture has changed in several significant ways with the new Tegra186 SoC. Shared between all display controllers is a set of common resources referred to as the display hub. The hub generates accesses to memory and feeds them into various composition pipelines, each of which being a window that can be assigned to arbitrary heads. Atomic state is subclassed in order to track the global bandwidth requirements and select and adjust the hub clocks appropriately. The plane code is shared to a large degree with earlier SoC generations, except where the programming differs. Signed-off-by: Thierry Reding <[email protected]>
2017-12-13drm/tegra: dc: Move state definition to headerThierry Reding1-0/+18
Move the display controller state definition to the header file so that it can be referenced by other files. Signed-off-by: Thierry Reding <[email protected]>
2017-12-13drm/tegra: Remove custom page-flip handlerThierry Reding1-3/+0
Tegra display hardware has GO bits and meets all the requirements to use drm_crtc_arm_vblank_event(). Use it instead and get rid of the hand- rolled implementation. Signed-off-by: Thierry Reding <[email protected]>
2017-12-13drm/tegra: Use atomic commit helpersThierry Reding1-0/+2
There's no reason not to use them, and they already get all the semantics right, so rip out all of the custom code and replace it by the helpers. Signed-off-by: Thierry Reding <[email protected]>
2017-12-13drm/tegra: dc: Support background colorThierry Reding1-1/+7
Starting with Tegra124, the interface to set the background color (the value generated for pixels that are not sourced from any window) is via a different register. Earlier generations called this the border color. Reverse the feature flag and assume that IP revisions that don't have support for background color will support border color instead. Signed-off-by: Thierry Reding <[email protected]>
2017-12-13drm/tegra: dc: Register debugfs in ->late_register()Thierry Reding1-2/+0
The ->late_register() and ->early_unregister() callbacks are called at the right time to make sure userspace only accesses interfaces when it should. Move debugfs registration and unregistration to these callback functions to avoid potential races with userspace. Signed-off-by: Thierry Reding <[email protected]>
2017-10-20drm/tegra: dc: Move some declarations to dc.hThierry Reding1-0/+120
Move the DC related declarations in drm.h to dc.h where they belong. Signed-off-by: Thierry Reding <[email protected]>
2015-08-13drm/tegra: sor: Add HDMI supportThierry Reding1-0/+4
The SOR1 introduced on Tegra210 supports HDMI 2.0 and DisplayPort. Add HDMI support and name the debugfs node after the type of SOR. The SOR introduced with Tegra124 is known simply as "sor", whereas the additional SOR found on Tegra210 is known as "sor1". Signed-off-by: Thierry Reding <[email protected]>
2015-08-13drm/tegra: dc: Rename BASE_COLOR_SIZE* fieldsThierry Reding1-0/+9
Use an underscore to separate the prefix from the color size suffix. Signed-off-by: Thierry Reding <[email protected]>
2015-08-13drm/tegra: dc: Rename register for consistencyThierry Reding1-3/+3
The horizontal pulse enable bits are named H_PULSE{0,1,2}_ENABLE in the TRM. Modify the driver to use the same naming for consistency. Signed-off-by: Thierry Reding <[email protected]>
2015-08-13drm/tegra: dc: Implement CRC debugfs interfaceThierry Reding1-0/+5
Signed-off-by: Thierry Reding <[email protected]>
2015-04-02drm/tegra: dc: Implement hardware VBLANK counterThierry Reding1-4/+3
The display controller on Tegra can use syncpoints to count VBLANK events. syncpoints are 32-bit unsigned integers, so well suited as VBLANK counters. Signed-off-by: Thierry Reding <[email protected]>
2014-08-04drm/tegra: Implement more tiling modesThierry Reding1-0/+5
Tegra124 supports a block-linear mode in addition to the regular pitch linear and tiled modes. Add support for these by moving the internal representation into a structure rather than a simple flag. Tested-by: Alexandre Courbot <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2014-06-05drm/tegra: Add hardware cursor supportThierry Reding1-3/+27
Enable hardware cursor support on Tegra124. Earlier generations support the hardware cursor to some degree as well, but not in a way that can be generically exposed. Signed-off-by: Thierry Reding <[email protected]>
2014-06-05drm/tegra: dc - Rename INVERT_V to V_DIRECTIONThierry Reding1-1/+2
V_DIRECTION is the name of the field in the documentation, so use that for consistency. Also add the H_DIRECTION field for completeness. Signed-off-by: Thierry Reding <[email protected]>
2014-04-04drm/tegra: Add eDP supportThierry Reding1-0/+1
Add support for eDP functionality found on Tegra124 and later SoCs. Only fast link training is currently supported. Signed-off-by: Thierry Reding <[email protected]>
2013-12-20drm/tegra: Relocate some output-specific codeThierry Reding1-0/+2
Some of the code in the CRTC's mode setting code is specific to the RGB output or needs to be called slightly differently depending on the type of output. Push that code down into the output drivers. Signed-off-by: Thierry Reding <[email protected]>
2013-12-20drm/tegra: Add Tegra124 DC supportThierry Reding1-0/+5
Tegra124 and later support interlacing, but the driver doesn't support it yet. Make sure interlacing stays disabled on hardware that supports it. Signed-off-by: Thierry Reding <[email protected]>
2013-12-20drm/tegra: Add DSI supportThierry Reding1-0/+2
This commit adds support for both DSI outputs found on Tegra. Only very minimal functionality is implemented, so advanced features like ganged mode won't work. Due to the lack of other test hardware, some sections of the driver are hardcoded to work with Dalmore. Signed-off-by: Thierry Reding <[email protected]>
2013-10-31drm/tegra: Support bottom-up buffer objectsThierry Reding1-0/+1
The gr3d engine renders images bottom-up. Allow buffers that are used for 3D content to be marked as such and implement support in the display controller to present them properly. Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2013-10-31drm/tegra: Add support for tiled buffer objectsThierry Reding1-0/+4
The gr2d and gr3d engines work more efficiently on buffers with a tiled memory layout. Allow created buffers to be marked as tiled so that the display controller can scan them out properly. Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2013-10-31drm/tegra: Move driver to DRM treeThierry Reding1-0/+400
In order to make subsystem-wide changes easier, move the Tegra DRM driver back into the DRM tree. Signed-off-by: Thierry Reding <[email protected]>
2013-04-22drm/tegra: Move drm to live under host1xTerje Bergstrom1-400/+0
Make drm part of host1x driver. Signed-off-by: Arto Merilainen <[email protected]> Signed-off-by: Terje Bergstrom <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Tested-by: Thierry Reding <[email protected]> Tested-by: Erik Faye-Lund <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2013-02-22drm/tegra: Implement page-flipping supportThierry Reding1-0/+2
All the necessary support bits like .mode_set_base() and VBLANK are now available, so page-flipping case easily be implemented on top. Signed-off-by: Thierry Reding <[email protected]>
2013-02-22drm/tegra: Add plane supportThierry Reding1-1/+11
Add support for the B and C planes which support RGB and YUV pixel formats and can be used as overlays or hardware cursor. Currently 32-bit XRGB as well as UYVY, YUV420 and YUV422 pixel formats are advertised. Other formats should be easy to add but these are the most common ones and should cover the majority of use-cases. Signed-off-by: Thierry Reding <[email protected]>
2012-11-20drm: Add NVIDIA Tegra20 supportThierry Reding1-0/+388
This commit adds a KMS driver for the Tegra20 SoC. This includes basic support for host1x and the two display controllers found on the Tegra20 SoC. Each display controller can drive a separate RGB/LVDS output. Signed-off-by: Thierry Reding <[email protected]> Tested-by: Stephen Warren <[email protected]> Acked-by: Mark Zhang <[email protected]> Reviewed-by: Mark Zhang <[email protected]> Tested-by: Mark Zhang <[email protected]> Tested-and-acked-by: Alexandre Courbot <[email protected]> Acked-by: Terje Bergstrom <[email protected]> Tested-by: Terje Bergstrom <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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