Age | Commit message (Collapse) | Author | Files | Lines |
|
Signed-off-by: Alex Deucher <[email protected]>
|
|
Signed-off-by: Alex Deucher <[email protected]>
|
|
Signed-off-by: Alex Deucher <[email protected]>
|
|
Signed-off-by: Alex Deucher <[email protected]>
|
|
Signed-off-by: Alex Deucher <[email protected]>
|
|
Signed-off-by: Alex Deucher <[email protected]>
|
|
Signed-off-by: Alex Deucher <[email protected]>
|
|
Signed-off-by: Alex Deucher <[email protected]>
|
|
This adds dpm support for SI asics. This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2/gen3 switching
- power containment
- shader power scaling
Set radeon.dpm=1 to enable.
v2: enable hainan support, rebase
v3: guard acpi stuff
v4: fix 64 bit math
v5: fix 64 bit div harder
v6: fix thermal interrupt check noticed by Jerome
v7: attempt fix state enable
Signed-off-by: Alex Deucher <[email protected]>
|
|
Signed-off-by: Alex Deucher <[email protected]>
|
|
Signed-off-by: Alex Deucher <[email protected]>
|
|
We weren't properly catching errors in dpm_enable()
and dpm_set_power_state().
Signed-off-by: Alex Deucher <[email protected]>
|
|
We weren't properly catching errors in dpm_enable()
and dpm_set_power_state().
Signed-off-by: Alex Deucher <[email protected]>
|
|
We weren't properly catching errors in dpm_enable()
and dpm_set_power_state().
Signed-off-by: Alex Deucher <[email protected]>
|
|
We weren't properly catching errors in dpm_enable()
and dpm_set_power_state().
Signed-off-by: Alex Deucher <[email protected]>
|
|
We weren't properly catching errors in dpm_enable()
and dpm_set_power_state().
Signed-off-by: Alex Deucher <[email protected]>
|
|
We weren't properly catching errors in dpm_enable()
and dpm_set_power_state().
Signed-off-by: Alex Deucher <[email protected]>
|
|
We weren't properly catching errors in dpm_enable()
and dpm_set_power_state().
Signed-off-by: Alex Deucher <[email protected]>
|
|
We weren't properly catching errors in dpm_enable()
and dpm_set_power_state().
Signed-off-by: Alex Deucher <[email protected]>
|
|
The arrays items are variable sized.
Signed-off-by: Alex Deucher <[email protected]>
|
|
Signed-off-by: Alex Deucher <[email protected]>
|
|
Signed-off-by: Alex Deucher <[email protected]>
|
|
Add a helper function to determine the preferred
pcie gen based on the card, system, and circumstance.
Signed-off-by: Alex Deucher <[email protected]>
|
|
Add a way to look up the bootup mvdd. Required for DPM on SI.
Signed-off-by: Alex Deucher <[email protected]>
|
|
Validate the voltages against the voltage requirements of the
dispclk. We currently don't adjust the disp clock so it never
changes, but we need to filter out voltage levels that are too
low none the less.
Signed-off-by: Alex Deucher <[email protected]>
|
|
Forgot to free some structs when allocation fails for some
tables.
Signed-off-by: Alex Deucher <[email protected]>
|
|
Use the new fixed point functions for leakage
calculations on cayman.
v2: fix up 64 bit math
Signed-off-by: Alex Deucher <[email protected]>
|
|
Consolidate the non-register defines.
Signed-off-by: Alex Deucher <[email protected]>
|
|
Required for SI.
Signed-off-by: Alex Deucher <[email protected]>
|
|
Used by SI dpm.
Signed-off-by: Alex Deucher <[email protected]>
|
|
Signed-off-by: Alex Deucher <[email protected]>
|
|
Required for dpm on SI.
Signed-off-by: Alex Deucher <[email protected]>
|
|
This makes it easier the understand what the code is
doing.
Signed-off-by: Alex Deucher <[email protected]>
|
|
Only Cape Verde supports power gating.
Signed-off-by: Alex Deucher <[email protected]>
|
|
Signed-off-by: Alex Deucher <[email protected]>
|
|
Signed-off-by: Alex Deucher <[email protected]>
|
|
These are needed for certain UVD power saving features.
Signed-off-by: Alex Deucher <[email protected]>
|
|
Required for DPM on SI.
Signed-off-by: Alex Deucher <[email protected]>
|
|
This is required for certain power management features.
Signed-off-by: Alex Deucher <[email protected]>
|
|
TN has some additional powergating features beyond what is
supported on ON/LN.
Signed-off-by: Alex Deucher <[email protected]>
|
|
Enables PCIE ASPM (Active State Power Management) on
SI asics.
v2: fix typo
Signed-off-by: Alex Deucher <[email protected]>
|
|
Enables PCIE ASPM (Active State Power Management) on
evergreen-cayman asics.
Signed-off-by: Alex Deucher <[email protected]>
|
|
Required for accessing certain pcie related registers.
Signed-off-by: Alex Deucher <[email protected]>
|
|
If both the motherboard and GPU support pcie gen2 or 3,
enable it. PCIE gen2 and 3 offer more bandwidth than
pcie gen1.
Signed-off-by: Alex Deucher <[email protected]>
|
|
SI uses a new atom table revision. Required for DPM on SI.
Signed-off-by: Alex Deucher <[email protected]>
|
|
SI uses a new atom table. Required for DPM on SI.
Signed-off-by: Alex Deucher <[email protected]>
|
|
There's a new table for calculating the memory pll
parameters on SI. Required for SI DPM support.
Signed-off-by: Alex Deucher <[email protected]>
|
|
These functions use acpi methods to adjust the pcie
gen speed. Used by DPM.
Signed-off-by: Alex Deucher <[email protected]>
|
|
Use the new asic callback instead.
Signed-off-by: Alex Deucher <[email protected]>
|
|
Signed-off-by: Alex Deucher <[email protected]>
|