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2012-10-02drm/radeon/pm: fix multi-head profile handling on BTC+ (v2)Alex Deucher4-4/+76
Starting on BTC, there are no longer separate states for single head and multi-head, we just use the high mclk/voltage for all states for multi-head. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=49981 v2: fix typo Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-01drm/radeon: fix radeon power state debug outputAlex Deucher1-11/+9
Driver used to print "default" as the state type regardless of whether it is the default state. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27drm/radeon: force MSIs on RS690 asicsAlex Deucher1-0/+4
There are so many quirks, lets just try and force this for all RS690s. See: https://bugs.freedesktop.org/show_bug.cgi?id=37679 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2012-09-27drm/radeon: Add MSI quirk for gateway RS690Alex Deucher1-0/+6
Fixes another system on: https://bugs.freedesktop.org/show_bug.cgi?id=37679 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2012-09-27drm/radeon: allow MIP_ADDRESS=0 for MSAA textures on EvergreenMarek Olšák2-8/+54
MIP_ADDRESS should point to the resolved FMASK for an MSAA texture. Setting MIP_ADDRESS to 0 means the FMASK pointer is invalid (the GPU won't read the memory then). The userspace has to set MIP_ADDRESS to 0 and *not* emit any relocation for it. Signed-off-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2012-09-27drm/radeon/kms: allow STRMOUT_BASE_UPDATE on RS780 and RS880Marek Olšák2-2/+4
This is required to make streamout work there. Signed-off-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2012-09-27drm/radeon: add 2-level VM pagetables support v9Dmitry Cherkasov4-30/+81
PDE/PTE update code uses CP ring for memory writes. All page table entries are preallocated for now in alloc_pt(). It is made as whole because it's hard to divide it to several patches that compile and doesn't break anything being applied separately. Tested on cayman card. v2: rebased on top of "refactor set_page chipset interface v3", code cleanups v3: switched offsets calc macros to inline funcs where possible, remove pd_addr from radeon_vm, switched RADEON_BLOCK_SIZE define, to 9 (and PTE_COUNT to 1 << BLOCK_SIZE) v4 (ck): move "incr" documentation to previous patch, cleanup and document RADEON_VM_* constants, change commit message to our usual format, simplify patch allot by removing everything current not necessary, disable SI workaround. v5: (agd5f): Fix typo in tables_size calculation in radeon_vm_alloc_pt(). Second line should have been '+=' rather than '='. v6: fix npdes calculation. In scenario when pfns to be mapped overlap two PDE spans: +-----------+-------------+ | PDE span | PDE span | +-----------+----+--------+ | | +---------+ | pfns | +---------+ the following npdes calculation gives incorrect result: npdes = (nptes >> RADEON_VM_BLOCK_SIZE) + 1; For the case above picture it should give npdes = 2, but gives one. This patch corrects it by rounding last pfn up to 512 border, first - down to 512 border and then subtracting and dividing by 512. v7: Make npde calculation clearer, fix ndw calculation. v8: (agd5f): reserve enough for 2 full VM PTs, add some additional comments. v9: fix typo in npde calculation Signed-off-by: Dmitry Cherkasov <Dmitrii.Cherkasov@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27drm/radeon: refactor set_page chipset interface v5Christian König4-63/+56
Cleanup the interface in preparation for hierarchical page tables. v2: add incr parameter to set_page for simple scattered PTs uptates added PDE-specific flags to r600_flags and radeon_drm.h removed superfluous value masking with 0xffffffff v3: removed superfluous bo_va->valid checking changed R600_PTE_VALID to R600_ENTRY_VALID to handle PDE too v4 (ck): fix indention style, rework and fix typos in commit message, add documentation for incr parameter, also use incr parameter for system pages v5 (agd5f): use upper_32_bits() and minor white space fixes Signed-off-by: Christian König <deathsimple@vodafone.de> Signed-off-by: Dmitry Cherkassov <Dmitrii.Cherkasov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27drm/radeon: Fix scratch register leak in IB test.Michel Dänzer2-12/+15
Restructure the code to jump out via labels instead of directly returning early. Also make error reporting consistent across all hardware generations. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Simon Kitching <skitching@vonos.net> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27drm/radeon: restore backlight level on resumeAlex Deucher4-4/+14
Restore the backlight level on resume. Some systems need to explicitly restore the backlight level on resume. Fixes panel resume on my Trinity laptop and may fix the following bugs: https://bugs.freedesktop.org/show_bug.cgi?id=43829 https://bugzilla.kernel.org/show_bug.cgi?id=46241 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27drm/radeon: add get_backlight_level callbackAlex Deucher5-0/+49
Read back the backlight level from the hw. Needed for proper backlight restoration on resume. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27drm/radeon: only adjust default clocks on NI GPUsAlex Deucher1-2/+6
SI asics store voltage information differently so we don't have a way to deal with it properly yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2012-09-27drm/radeon: validate PPLL in crtc fixupAlex Deucher1-2/+7
This allows us to bail if we can't support the requested setup from a PPLL perspective. Prevents broken setups from being attempted. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27drm/radeon: work around KMS modeset limitations in PLL allocation (v2)Alex Deucher2-28/+39
Since the current KMS API sets the mode independantly on each crtc, we may end up with resource conflicts. The PLL allocation is one of those cases. In the following example we have 3 crtcs in use driving 2 DVI connectors and 1 DP connector. On the initial kernel modeset for fbdev, the display topology ends up as follows: crtc0 -> DP-0 crtc1 -> DVI-0 crtc2 -> DVI-1 Because this is the first modeset, all of the PLLs are available as none have been assigned. So we end up with the following: crtc0 uses DCPLL crtc1 uses PPLL2 crtc2 uses PPLL1 When X starts, it assigns a different topology: crtc0 -> DVI-0 crtc1 -> DP-0 crtc2 -> DVI-1 However, since the KMS API is per crtc, we set the mode on each crtc independantly. When it comes time to set the mode on crtc0, the topology for crtc1 and crtc2 are still intact. crtc1 and crtc2 are already assigned PPLL2 and PPLL1 so when it comes time to set the mode on crtc0, crtc1 and crtc2 have not been torn down yet, so there appears to be no PLLs available. In reality, we are reconfiguring the entire display topology, however, since each crtc is handled independantly, we don't know that in the driver at each crtc mode set time. This patch checks to see if the same connector is being driven by another crtc, and if so, uses the PLL already associated with it. v2: store connector in the radeon crtc struct, simplify checking. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: make non-DP PPLL sharing more robustAlex Deucher1-13/+14
Compare the adjusted clock as well as the crtc mode clock. This handles cases where the driver adjusts the clock for specific special cases. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: store the encoder in the radeon_crtcAlex Deucher2-208/+166
This saves lots of lookups later. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: rework crtc pll setup to better support PPLL sharingAlex Deucher2-103/+150
We need the calculate the pixel clock before allocating a PPLL in order to insure the clocks really match. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: allow PPLL sharing on non-DP displaysAlex Deucher1-6/+65
If several non-DP displays use the same pixel clock we can use the same PPLL for all of them. If all relevant displays have the same pixel clock, this allows the driver to: - use fewer PPLLs which saves power - support more than two non-DP displays on DCE4+ The current drm modesetting infrastructure doesn't really provide a good framework for validating combinations that work or won't work, so it's possible you could go from a working configuration to a non-working one by changing the mode a one of the displays. However, there this is better than what was there before. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon/dce3: use a single PPLL for all DP displaysAlex Deucher1-0/+24
If possible, use a single PPLL for multiple DP displays on DCE3.x. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: rework pll selection (v4)Alex Deucher1-34/+129
For DP we can use the same PPLL for all active DP encoders. Take advantage of that to prevent cases where we may end up sharing a PPLL between DP and non-DP which won't work. Also clean up the code a bit. v2: - fix missing pll_id assignment in crtc init v3: - fix DP PPLL check - document functions - break in main encoder search loop after matching. no need to keep checking additional encoders. v4: - same as v3, but re-apply to drm-next as the corner cases are fixed properly in subsequent patches. fixes: https://bugs.freedesktop.org/show_bug.cgi?id=54471 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: fix typo in atombios_get_encoder_modeAlex Deucher1-1/+2
comparing the encoder mode to the encoder id for DVO. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon/atom: fix typo in SetPixelClock handlingAlex Deucher1-1/+4
MiscInfo field should be programmed with the crtc id rather than the pll id. However, at this point the two are the same for chips with this version of the table. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: white space cleanup in transmitter setupAlex Deucher1-8/+4
Makes it more consistent with the surrounding code. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: clean up encoder dp checksAlex Deucher1-4/+4
Use the proper struct in the union. That field has the same offset in every struct, so no functional change. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: rework the VM code a bit more (v2)Christian König4-72/+154
Roughly based on how nouveau is handling it. Instead of adding the bo_va when the address is set add the bo_va when the handle is opened, but set the address to zero until userspace tells us where to place it. This fixes another bunch of problems with glamor. v2: agd5f: fix build after dropping patch 7/8. Signed-off-by: Christian König <deathsimple@vodafone.de>
2012-09-20drm/radeon: fix gem_close_object handlingChristian König1-2/+5
Make the reserve non interruptible. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-20drm/radeon: let bo_reserve take no_intr instead of no_wait paramChristian König2-5/+4
The no_wait param isn't used anywhere, and actually isn't very usefull at all. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-20drm/radeon: move and rename radeon_bo_va functionChristian König5-20/+33
It doesn't really belong into the object functions, also rename it to avoid collisions with struct radeon_bo_va. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-20drm/radeon: move IB pool to 1MB offsetChristian König3-4/+5
Even GPUs can have a null pointer dereference, so move the IB pool to another offset to catch those. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-20drm/radeon: fix VA overlap checkChristian König1-1/+1
Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-20drm/radeon: fix VA range checkChristian König1-1/+1
The end offset is exclusive not inclusive. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-20drm/radeon: fix VM syncing with multiple ringsChristian König1-1/+1
When a VM is used on more than one ring we need to sync to the last user. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-20drm/radeon: Remove unused functionsLauri Kasanen4-74/+0
This applies on top of drm/radeon: Mark all possible functions / structs as static. Signed-off-by: Lauri Kasanen <cand@gmx.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: Mark all possible functions / structs as staticLauri Kasanen27-93/+93
Let's allow GCC to optimize better. This exposed some five unused functions, but this patch doesn't remove them. Signed-off-by: Lauri Kasanen <cand@gmx.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: remove dead function defAlex Deucher1-2/+1
Was removed in the async VM update series. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: implement bounds checking on thermal controller lookupAlex Deucher1-2/+9
Don't read past the end of the array if we encounter an unknown thermal controller. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: document async VM changes in ni.cAlex Deucher1-0/+15
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: make page table updates async v2Christian König5-25/+71
Currently doing the update with the CP. v2: Rebased on Jeromes bugfix. Make validity comparison more human readable. Signed-off-by: Christian König <deathsimple@vodafone.de>
2012-09-20drm/radeon: make sure ib bo is properly bound and up to date in vm spaceJerome Glisse1-0/+5
Make sure that the ib bo is bound and is page table is up to date in the virtual address space. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-20drm/radeon: Move looping over the PTEs into chip codeChristian König5-34/+34
Makes it easier to move it into the rings. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-20drm/radeon: rework VM page table handlingChristian König4-116/+43
Removing the need to wait for anything. Still not ideal, since we need to free pt on va remove. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-20drm/radeon: rework VMID handlingChristian König8-76/+153
Move binding onto the ring, simplifying handling a bit. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-20drm/radeon: make VM flushs a ring operationChristian König8-38/+42
Move flushing the VMs as function into the rings. First step to make VM operations async. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-20drm/radeon: add sync helper functionChristian König1-6/+14
Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-20drm/radeon: remove vm_unbindChristian König5-29/+0
It actually isn't very useful. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-20drm/radeon: move VM funcs into asic structureChristian König3-47/+54
So it looks more like the rest of the driver. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-20drm/radeon: cleanup VM id handling a bitChristian König7-26/+25
Store a reference to the VM into the IB structure, that makes calculating the IBs address a bit less complicated. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-09-20drm/radeon/atom: add consolidate bpc codeAlex Deucher1-67/+29
Several encoder setup functions had the same duplicated code for selecting the proper bpc setting for various atom tables. Consolidate it. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: rework the backlight control to be an asic callbackAlex Deucher7-33/+84
This cleans up the interface a bit as well. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: add initial support for ATCS ACPI methodsAlex Deucher2-1/+138
Just verify the interface and track what functions are supported. Not actually used yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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