aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/radeon/si.c
AgeCommit message (Collapse)AuthorFilesLines
2013-12-04drm/radeon: fixup bad vram size on SIAlex Deucher1-2/+9
Some boards seem to have garbage in the upper 16 bits of the vram size register. Check for this and clamp the size properly. Fixes boards reporting bogus amounts of vram. Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2013-11-08Merge tag 'drm-intel-fixes-2013-11-07' of ↵Dave Airlie1-0/+11
git://people.freedesktop.org/~danvet/drm-intel into drm-next Bit a bit -fixes pull request in the merge window than usual dua to two feauture-y things: - Display CRCs are now enabled on all platforms, including the odd DP case on gm45/vlv. Since this is a testing-only feature it should ever hurt, but I figured it'll help with regression-testing -fixes. So I left it in and didn't postpone it to 3.14. - Display power well refactoring from Imre. Would have caused major pain conflict with the bdw stage 1 patches if I'd postpone this to -next. It's only an relatively small interface rework, so shouldn't cause pain. It's also been in my tree since almost 3 weeks already. That accounts for about two thirds of the pull, otherwise just bugfixes: - vlv backlight fix from Jesse/Jani - vlv vblank timestamp fix from Jesse - improved edp detection through vbt from Ville (fixes a vlv issue) - eDP vdd fix from Paulo - fixes for dvo lvds on i830M - a few smaller things all over Note: This contains a backmerge of v3.12. Since the -internal branch always applied on top of -nightly I need that unified base to merge bdw patches. So you'll get a conflict with radeon connector props when pulling this (and nouveau/master will also conflict a bit when Ben doesn't rebase). The backmerge itself only had conflicts in drm/i915. There's also a tiny conflict between Jani's backlight fix and your sysfs lifetime fix in drm-next. * tag 'drm-intel-fixes-2013-11-07' of git://people.freedesktop.org/~danvet/drm-intel: (940 commits) drm/i915/vlv: use per-pipe backlight controls v2 drm/i915: make backlight functions take a connector drm/i915: move opregion asle request handling to a work queue drm/i915/vlv: use PIPE_START_VBLANK interrupts on VLV drm/i915: Make intel_dp_is_edp() less specific drm/i915: Give names to the VBT child device type bits drm/i915/vlv: enable HDA display audio for Valleyview2 drm/i915/dvo: call ->mode_set callback only when the port is running drm/i915: avoid unclaimed registers when capturing the error state drm/i915: Enable DP port CRC for the "auto" source on g4x/vlv drm/i915: scramble reset support for DP port CRC on vlv drm/i915: scramble reset support for DP port CRC on g4x drm/i916: add "auto" pipe CRC source ... Conflicts: MAINTAINERS drivers/gpu/drm/i915/intel_panel.c drivers/gpu/drm/nouveau/core/subdev/mc/base.c drivers/gpu/drm/radeon/atombios_encoders.c drivers/gpu/drm/radeon/radeon_connectors.c
2013-11-01drm/radeon: drop CP page table updates & cleanup v2Christian König1-60/+0
The DMA ring seems to be stable now. v2: remove pt_ring_index as well Signed-off-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2013-11-01drm/radeon: fix endian handling in rlc buffer setupAlex Deucher1-19/+20
The buffers needs to be in little endian format. Noticed-by: Sylvain BERTRAND <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2013-10-18drm/radeon: make missing smc ucode non-fatal (r7xx-SI)Alex Deucher1-0/+1
Prevent driver load problems if the smc is missing. bug: https://bugzilla.kernel.org/show_bug.cgi?id=63011 Signed-off-by: Alex Deucher <[email protected]> Tested-by: Mikko Rapeli <[email protected]> Cc: [email protected]
2013-10-09drm/radeon: improve soft reset on SIAlex Deucher1-0/+10
Disable CG/PG and stop the rlc before resetting. Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2013-09-11drm/radeon: fix typo in PG flagsAlex Deucher1-2/+2
s/CG/PG/ in the GFX powergating flag name. Signed-off-by: Alex Deucher <[email protected]>
2013-09-11drm/radeon/si: properly handle internal cp intsAlex Deucher1-2/+15
The internal cp interrupts need to be enabled and disabled at specific times in order clockgating to work properly. This patch changes the handling of the CP_INT_CNTL register to respect the current state of the internal CP interrupts when making changes to the other interrupts in CP_INT_CNTL. Signed-off-by: Alex Deucher <[email protected]>
2013-09-02Merge branch 'drm-next-3.12' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie1-453/+390
into drm-next Alex writes: This is the radeon drm-next request. Big changes include: - support for dpm on CIK parts - support for ASPM on CIK parts - support for berlin GPUs - major ring handling cleanup - remove the old 3D blit code for bo moves in favor of CP DMA or sDMA - lots of bug fixes [airlied: fix up a bunch of conflicts from drm_order removal] * 'drm-next-3.12' of git://people.freedesktop.org/~agd5f/linux: (898 commits) drm/radeon/dpm: make sure dc performance level limits are valid (CI) drm/radeon/dpm: make sure dc performance level limits are valid (BTC-SI) (v2) drm/radeon: gcc fixes for extended dpm tables drm/radeon: gcc fixes for kb/kv dpm drm/radeon: gcc fixes for ci dpm drm/radeon: gcc fixes for si dpm drm/radeon: gcc fixes for ni dpm drm/radeon: gcc fixes for trinity dpm drm/radeon: gcc fixes for sumo dpm drm/radeonn: gcc fixes for rv7xx/eg/btc dpm drm/radeon: gcc fixes for rv6xx dpm drm/radeon: gcc fixes for radeon_atombios.c drm/radeon: enable UVD interrupts on CIK drm/radeon: fix init ordering for r600+ drm/radeon/dpm: only need to reprogram uvd if uvd pg is enabled drm/radeon: check the return value of uvd_v1_0_start in uvd_v1_0_init drm/radeon: split out radeon_uvd_resume from uvd_v4_2_resume radeon kms: fix uninitialised hotplug work usage in r100_irq_process() drm/radeon/audio: set up the sads on DCE3.2 asics drm/radeon: fix handling of variable sized arrays for router objects ... Conflicts: drivers/gpu/drm/i915/i915_dma.c drivers/gpu/drm/i915/i915_gem_dmabuf.c drivers/gpu/drm/i915/intel_pm.c drivers/gpu/drm/radeon/cik.c drivers/gpu/drm/radeon/ni.c drivers/gpu/drm/radeon/r600.c
2013-08-30drm/radeon: fix init ordering for r600+Alex Deucher1-4/+5
The vram scratch buffer needs to be initialized before the mc is programmed otherwise we program 0 as the GPU address of the default GPU fault page. In most cases we put vram at zero anyway and reserve a page for the legacy vga buffer so in practice this shouldn't cause any problems, but better to make it correct. Was changed in: 6fab3febf6d949b0a12b1e4e73db38e4a177a79e Reported-by: FrankR Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2013-08-30drm/radeon: update line buffer allocation for dce6Alex Deucher1-4/+19
We need to allocate line buffer to each display when setting up the watermarks. Failure to do so can lead to a blank screen. This fixes blank screen problems on dce6 asics. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=64850 Based on an initial fix from: Jay Cornwall <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2013-08-30drm/radeon/si: Add support for CP DMA to CS checker for compute v2Tom Stellard1-45/+61
Also add a new RADEON_INFO query to check that CP DMA packets are supported on the compute ring. CP DMA has been supported since the 3.8 kernel, but due to an oversight we forgot to teach the CS checker that the CP DMA packet was legal for the compute ring on Southern Islands GPUs. This patch fixes a bug where the radeon driver will incorrectly reject a legal CP DMA packet from user space. I would like to have the patch backported to stable so that we don't have to require Mesa users to use a bleeding edge kernel in order to take advantage of this feature which is already present in the stable kernels (3.8 and newer). v2: - Don't bump kms version, so this patch can be backported to stable kernels. Cc: [email protected] Signed-off-by: Tom Stellard <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/radeon/si: enable DMA pg by defaultAlex Deucher1-12/+4
Enable DMA powergating by default. The DMA engines will be powergated when not in use. Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/radeon/si: properly set up the clearstate buffer for pg (v2)Alex Deucher1-0/+91
The format of the clearstate buffer used for pg (powergating) changed between NI and SI. This formats it properly for what the hardware expects on SI. v2: fix addresses Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/radeon: fixes for gfx clockgating on SIAlex Deucher1-13/+4
Clockgating requires signalling between the CP and the RLC to work properly. Resetting the CP block in the CP resume code messed up the internal coordination between the blocks. Removing the reset allows gfx clockgating to work properly. However, when gfx clock gating is enabled, there is a strange interaction with dpm which causes the chip to stay in the high performance level all the time, so leave gfx clockgating disabled for now. Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/radeon/si: restructure cg code (v3)Alex Deucher1-29/+178
Resturcture clockgating code so that it can be enabled/disabled from other components such as dpm. v2: make function static v3: add fine grained cg controls Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/radeon: use new cg/pg flags for SIAlex Deucher1-29/+30
Allows us finer grained control over clock and powergating on SI. Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/radeon: add audio support for DCE6/8 GPUs (v12)Alex Deucher1-0/+5
Similar to DCE4/5, but supports multiple audio pins which can be assigned per afmt block. v2: rework the driver to handle more than one audio pin. v3: try different dto reg v4: properly program dto v5 (ck): change dto programming order v6: program speaker allocation block v7: rebase v8: rebase on Rafał's changes v9: integrated Rafał's comments, update to latest drm_edid_to_speaker_allocation API v10: add missing line break in error message v11: add back audio enabled messages v12: fix copy paste typo in r600_audio_enable Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Christian König <[email protected]> Acked-by: Rafał Miłecki <[email protected]>
2013-08-30drm/radeon: separate DMA codeChristian König1-181/+7
Similar to separating the UVD code, just put the DMA functions into separate files. Signed-off-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/radeon: separate UVD code v3Christian König1-4/+4
Our different hardware blocks are actually completely separated, so it doesn't make much sense any more to structure the code by pure chipset generations. Start restructuring the code by separating our the UVD block. v2: updated commit message v3: rebased and restructurized start/stop functions for kv dpm. Signed-off-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/radeon: remove special handling for the DMA ringChristian König1-6/+6
Now that we have callbacks for [rw]ptr handling we can remove the special handling for the DMA rings and use the callbacks instead. Signed-off-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/radeon: rework UVD writeback & [rw]ptr handlingChristian König1-2/+1
The hardware just doesn't support this correctly. Disable it before we accidentally write anywhere we shouldn't. Signed-off-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/radeon: restructure UVD code to handle UVD PG (v2)Alex Deucher1-1/+1
When we PG (powergate) UVD, we need to re-initialize it before we can use it again. v2: rebase on UVD stop fixes Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/radeon: implement clock and power gating for CIK (v3)Alex Deucher1-1/+1
Only the APUs support power gating. v2: disable cgcg for now v3: workaround hw issue in mgcg Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/radeon: convert SI,CIK to use sumo_rlc functionsAlex Deucher1-163/+11
and remove duplicate si_rlc functions. Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/radeon/cik: restructure rlc setupAlex Deucher1-1/+1
Restructure rlc setup to handle clock and power gating. Signed-off-by: Alex Deucher <[email protected]>
2013-08-07drm/radeon: make missing smc ucode non-fatalAlex Deucher1-3/+7
The smc ucode is required for dpm (dynamic power management), but if it's missing just skip dpm setup and don't disable acceleration. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=67876 Signed-off-by: Alex Deucher <[email protected]>
2013-08-07drm/radeon: always program the MC on startupAlex Deucher1-1/+2
For r6xx+ asics. This mirrors the behavior of pre-r6xx asics. We need to program the MC even if something else in startup() fails. Failure to do so results in an unusable GPU. Based on a fix from: Mark Kettenis <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2013-08-07drm/radeon: fix halting UVDChristian König1-2/+4
Removing the clock/power or resetting the VCPU can cause hangs if that happens in the middle of a register write. Stall the memory and register bus before putting the VCPU into reset. Keep it in reset when unloading the module or suspending. Signed-off-by: Christian König <[email protected]> Cc: [email protected] Signed-off-by: Alex Deucher <[email protected]>
2013-07-29drm/radeon/si: disable cgcg and pg for nowAlex Deucher1-3/+3
Coarse grain clockgating causes problems with reclocking on some cards and powergating (verde only) causes problems with ring initialization. The proper fix (restructuring the init sequences) is too invasive for 3.11 so just disable them for now. Signed-off-by: Alex Deucher <[email protected]>
2013-07-29drm/radeon: properly handle cg on asics without UVDAlex Deucher1-6/+2
Don't try and enable clockgating if the asic doesn't have UVD. Use rdev->has_uvd rather than using local checks. Signed-off-by: Alex Deucher <[email protected]>
2013-07-23drm/radeon: s/drm_order/order_base_2/Daniel Vetter1-7/+7
Last driver and pretty obviously a major user of this little function. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-07-17drm/radeon: add a module parameter to disable aspmAlex Deucher1-0/+3
Can cause hangs when enabled in certain motherboards. Set radeon.aspm=0 to disable aspm. Signed-off-by: Alex Deucher <[email protected]>
2013-07-14drm/radeon: add fault decode function for SI (v2)Alex Deucher1-2/+270
Helpful for debugging GPUVM errors as we can see what hw block and page generated the fault in the log. v2: simplify fault decoding Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
2013-07-14drm/radeon: use radeon device for request firmwareJerome Glisse1-17/+6
Avoid creating temporary platform device that will lead to issue when several radeon gpu are in same computer. Instead directly use the radeon device for requesting firmware. Reviewed-by: Christian König <[email protected]> Signed-off-by: Jerome Glisse <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2013-06-27drm/radeon/si: fix typo in function nameAlex Deucher1-2/+2
Signed-off-by: Alex Deucher <[email protected]>
2013-06-27drm/radeon/kms: add dpm support for SI (v7)Alex Deucher1-0/+48
This adds dpm support for SI asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2/gen3 switching - power containment - shader power scaling Set radeon.dpm=1 to enable. v2: enable hainan support, rebase v3: guard acpi stuff v4: fix 64 bit math v5: fix 64 bit div harder v6: fix thermal interrupt check noticed by Jerome v7: attempt fix state enable Signed-off-by: Alex Deucher <[email protected]>
2013-06-27drm/radeon: switch SI to use radeon_ucode.hAlex Deucher1-6/+1
Signed-off-by: Alex Deucher <[email protected]>
2013-06-27drm/radeon/dpm: save some display parameters for DPMAlex Deucher1-0/+4
Required for SI. Signed-off-by: Alex Deucher <[email protected]>
2013-06-27drm/radeon: implement clock and power gating for SIAlex Deucher1-42/+460
Only Cape Verde supports power gating. Signed-off-by: Alex Deucher <[email protected]>
2013-06-27drm/radeon: add clearstate init for verde power gatingAlex Deucher1-5/+63
Signed-off-by: Alex Deucher <[email protected]>
2013-06-27drm/radeon: initialize save/restore buffer for pg on verdeAlex Deucher1-2/+241
Signed-off-by: Alex Deucher <[email protected]>
2013-06-27drm/radeon: update rlc programming sequence on SIAlex Deucher1-0/+82
This is required for certain power management features. Signed-off-by: Alex Deucher <[email protected]>
2013-06-27drm/radeon: add support for ASPM on SI asics (v2)Alex Deucher1-0/+203
Enables PCIE ASPM (Active State Power Management) on SI asics. v2: fix typo Signed-off-by: Alex Deucher <[email protected]>
2013-06-27drm/radeon: implement pcie gen2/3 support for SIAlex Deucher1-0/+162
If both the motherboard and GPU support pcie gen2 or 3, enable it. PCIE gen2 and 3 offer more bandwidth than pcie gen1. Signed-off-by: Alex Deucher <[email protected]>
2013-06-27drm/radeon/kms: fix up dce6 display watermark calc for dpmAlex Deucher1-25/+71
Calculate the low and high watermarks based on the low and high clocks for the current power state. The dynamic pm hw will select the appropriate watermark based on the internal dpm state. Signed-off-by: Alex Deucher <[email protected]>
2013-06-25drm/radeon: add support for MC/VM setup on CIK (v6)Alex Deucher1-2/+2
The vm callbacks are the same as the SI ones right now (same regs and bits). We could share the SI variants, and I may yet do that, but I figured I would add CIK specific ones for now in case we need to change anything. V2: add documentation, minor fixes. V3: integrate vram offset fixes for APUs V4: enable 2 level VM PTs V5: index SH_MEM_* regs properly V6: add ib_parse() Signed-off-by: Alex Deucher <[email protected]>
2013-06-03radeon: Fix system hang issue when using KMS with older cardsAdis Hamzić1-4/+6
The current radeon driver initialization routines, when using KMS, are written so that the IRQ installation routine is called before initializing the WB buffer and the CP rings. With some ASICs, though, the IRQ routine tries to access the GFX_INDEX ring causing a call to RREG32 with the value of -1 in radeon_fence_read. This, in turn causes the system to completely hang with some cards, requiring a hard reset. A call stack that can cause such a hang looks like this (using rv515 ASIC for the example here): * rv515_init (rv515.c) * radeon_irq_kms_init (radeon_irq_kms.c) * drm_irq_install (drm_irq.c) * radeon_driver_irq_preinstall_kms (radeon_irq_kms.c) * rs600_irq_process (rs600.c) * radeon_fence_process - due to SW interrupt (radeon_fence.c) * radeon_fence_read (radeon_fence.c) * hang due to RREG32(-1) The patch moves the IRQ installation to the card startup routine, after the ring has been initialized, but before the IRQ has been set. This fixes the issue, but requires a check to see if the IRQ is already installed, as is the case in the system resume codepath. I have tested the patch on three machines using the rv515, the rv770 and the evergreen ASIC. They worked without issues. This seems to be a known issue and has been reported on several bug tracking sites by various distributions (see links below). Most of reports recommend booting the system with KMS disabled and then enabling KMS by reloading the radeon module. For some reason, this was indeed a usable workaround, however, UMS is now deprecated and disabled by default. Bug reports: https://bugzilla.redhat.com/show_bug.cgi?id=845745 https://bugs.launchpad.net/ubuntu/+source/linux/+bug/561789 https://bbs.archlinux.org/viewtopic.php?id=156964 Signed-off-by: Adis Hamzić <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2013-05-29drm/radeon: fix typo in cu_per_sh on verdeAlex Deucher1-1/+1
Should be 5 rather than 2. Noticed by sroland and glisse on IRC. Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2013-05-20drm/radeon: add golden register settings for Hainan (v2)Alex Deucher1-0/+122
v2: fix typo Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.