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2015-05-14drm/msm/dp: fix error return codeJulia Lawall1-1/+2
Return a negative error code on failure. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ identifier ret; expression e1,e2; @@ ( if (\(ret < 0\|ret != 0\)) { ... return ret; } | ret = 0 ) ... when != ret = e1 when != &ret *if(...) { ... when != ret = e2 when forall return ret; } // </smpl> Signed-off-by: Julia Lawall <[email protected]>
2015-05-14drm: msm: Fix build when legacy fbdev support isn't setArchit Taneja1-0/+4
The DRM_KMS_FB_HELPER config is selected only when DRM_MSM_FBDEV config is selected. The driver accesses drm_fb_helper_* functions even when legacy fbdev support is disabled in msm. Wrap around these functions with #ifdef checks to prevent build break. Signed-off-by: Archit Taneja <[email protected]>
2015-05-14drm/msm/dsi: Fix a couple more 64-bit build warningsStephane Viau1-2/+2
Avoid such errors at compilation time: format '%d' expects argument of type 'int', but argument 3 has type 'size_t' Signed-off-by: Stephane Viau <[email protected]>
2015-05-14drm/msm: Fix a couple of 64-bit build warningsThierry Reding4-10/+10
Avoid casts from pointers to fixed-size integers to prevent the compiler from warning. Print virtual memory addresses using %p instead. Also turn a couple of %d/%x specifiers into %zu/%zd/%zx to avoid further warnings due to mismatched format strings. Signed-off-by: Thierry Reding <[email protected]> Reviewed-by: Rob Clark <[email protected]>
2015-04-20Merge Linus master into drm-nextDave Airlie2-8/+8
The merge is clean, but the arm build fails afterwards, due to API changes in the regulator tree. I've included the patch into the merge to fix the build. Signed-off-by: Dave Airlie <[email protected]>
2015-04-10Merge remote-tracking branches 'regulator/topic/mode', ↵Mark Brown1-3/+3
'regulator/topic/notifier', 'regulator/topic/palmas', 'regulator/topic/qcom' and 'regulator/topic/stw481x' into regulator-next
2015-04-01drm/msm/mdp5: Enable DSI connector in msm drm driverHai Li8-7/+497
This change adds the support in mdp5 kms driver for single and dual DSI. Dual DSI case depends on the framework API and sequence change to support dual data path. v1: Initial change v2: Address Rob Clark's comment - Separate command mode encoder to a new file mdp5_cmd_encoder.c - Rebase to not depend on msm_drm_sub_dev change Signed-off-by: Hai Li <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm: Initial add DSI connector supportHai Li8-0/+3423
This change adds the DSI connector support in msm drm driver. v1: Initial change v2: - Address comments from Archit + minor clean-ups - Rebase to not depend on msm_drm_sub_dev change [Rob's comment] v3: Fix issues when initialization is failed Signed-off-by: Hai Li <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm: Add split display interfaceHai Li1-0/+4
This change is to add an interface to MDP for connector devices setting split display information. Signed-off-by: Hai Li <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/mdp5: Move *_modeset_init out of construct_encoder functionHai Li1-35/+54
This change is to make the content in construct_encoder reflect its name. Also, DSI connector may be connected to video mode or command mode encoder, so that 2 different encoders need to be constructed for DSI. Signed-off-by: Hai Li <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/mdp5: Remove CTL flush dummy bitsStephane Viau1-11/+0
This TODO can now be removed and replaced by the previous patch "drm/msm/mdp5: Update headers (add CTL flush bits)" Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/mdp5: Update headers (add CTL flush bits)Stephane Viau1-2/+10
Some upcoming targets have more bits to set in CTL_FLUSH registers. Example: msm8x16 needs to set TIMING1 bit so that some of the INTF1's interface registers get flushed. Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/mdp5: Add hardware configuration for msm8x16Stephane Viau1-1/+51
This change adds the hw configuration for msm8x16 chipsets in mdp5_cfg module. Note that only one external display interface is present in this configuration (DSI) but has not been enabled yet. It will be enabled once drm/msm driver supports DSI connectors. v2: add CTL flush register's hardware mask [pointed by Archit] Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/mdp5: Get SMP client list from mdp5_cfgStephane Viau3-24/+41
SMP blocks are configured for specific client IDs (ports). These client IDs can be different from one chip to another for a given pipe. e.g.: DMA0 pipe fetch Y component is connected to: - port #10 for MDP5 v1.3 - port #4 for MDP5 v1.6 In order to be compatible for upcoming versions of MDP5, the client ID list is passed through the MDP5 config module rather than using a list of hard-coded enum values. Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/mdp5: Update headers (remove enum mdp5_client_id)Stephane Viau1-34/+7
This patch contains the generated header file of the following change "drm/msm/mdp5: Get SMP client list from mdp5_cfg". Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/mdp5: Separate MDP5 domain from MDSS domainStephane Viau7-38/+48
MDP block is actually contained inside the MDSS block. For some chipsets, the base address of the MDP registers is different from the current (assumed) 0x100 offset. Like CTL and LM blocks, this changes introduce a dynamic offset for the MDP instance, which can be found out at runtime, once the MDSS HW version is read. Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/mdp5: Update headers (introduce MDP5 domain)Stephane Viau1-85/+118
This change contains the generated header file for the following change "drm/msm/mdp5: Separate MDP5 domain from MDSS domain". Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/dsi: Update generated DSI header fileHai Li1-42/+376
Prepare for initial DSI implementation Signed-off-by: Hai Li <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/mdp5: Fix PIPE source image size settingsHai Li1-2/+2
The width and height in SSPP_SRC_IMG_SIZE register should be the size of the entire source framebuffer, not the fetch size. Signed-off-by: Hai Li <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/mdp5: Update generated mdp5 header file with DSI supportHai Li1-0/+105
This change adds the registers in mdp5 ping pong blocks and split display control registers. Signed-off-by: Hai Li <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/mdp5: Add pingpong entry to mdp5 config tableHai Li2-0/+9
Pingpong register base addresses are different across platforms. This change adds this information to config table and initialize the values for 8x74 and 8084. Signed-off-by: Hai Li <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/mdp5: Make the intf connection in config moduleStephane Viau3-49/+75
Up until now, we assume that eDP is tight to intf_0 and HDMI to intf_3. This information shall actually come from the mdp5_cfg module since it can change from one chip to another. v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit] v3: add sanity check before writing in INTF_TIMING_ENGINE_EN registers Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/mdp5: Add START signal to kick off certain pipelinesStephane Viau7-97/+276
Some interfaces (WB, DSI Command Mode) need to be kicked off through a START Signal. This signal needs to be sent at the right time and requests in some cases to keep track of the pipeline status (eg: whether pipeline registers are flushed AND output WB buffers are ready, in case of WB interface). Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/mdp5: Enhance operation mode for pipeline configurationStephane Viau7-74/+159
DSI and WB interfaces need a more complex pipeline configuration than the current mdp5_ctl_set_intf(). For example, memory output connections need to be selected for WB. Interface mode (Video vs. Command modes) also need to be configured for DSI. This change takes care of configuring the whole pipeline as far as operation mode goes. DSI and WB interfaces will be added later. v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit] Signed-off-by: Stephane Viau <[email protected]> [Remove temp bisectability hack -Rob] Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/mdp5: Update generated header filesStephane Viau2-35/+36
Prepare for pipeline operation mode configuration, in particular for DSI and WB modes. Signed-off-by: Stephane Viau <[email protected]> [Throw in a #define temporarily to keep things bisectable -Rob] Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/mdp5: only flush on a CRTC ->atomic_flush()Stephane Viau1-7/+0
MDP5 hardware has some limitation and requires to avoid flushing registers more than once between two Vblanks. This change removes all FLUSH operations (except for HW cursor) beside the one coming from a CRTC's ->atomic_flush(). This avoid this type of behavior (eg: CRTC + 1 plane overlay): [drm:mdp5_crtc_vblank_irq] vblank [drm:mdp5_ctl_commit] flush (20048) CTL + LM0 + RGB0 [drm:mdp5_ctl_commit] flush (20040) CTL + LM0 [drm:mdp5_crtc_vblank_irq] blank [drm:mdp5_ctl_commit] flush (20049) CTL + LM0 + RGB0 + VIG0 [drm:mdp5_crtc_vblank_irq] blank and replaces it by: [drm:mdp5_crtc_vblank_irq] vblank [drm:mdp5_ctl_commit] flush (20048) CTL + LM0 + RGB0 [drm:mdp5_crtc_vblank_irq] blank [drm:mdp5_ctl_commit] flush (20049) CTL + LM0 + RGB0 + VIG0 [drm:mdp5_crtc_vblank_irq] blank Only *one* FLUSH is called between Vblanks interrupts. Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm/hdmi: add 74.176MHz and 154.0MHz pix clksRob Clark1-0/+34
Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm: add support for "stolen" memRob Clark4-11/+66
Add support to use the VRAM carveout (if specified in dtb) for fbdev scanout buffer. This allows drm/msm to take over a bootloader splash- screen, and avoids corruption on screen that results if the kernel uses memory that is still being scanned out for itself. Signed-off-by: Rob Clark <[email protected]>
2015-04-01drm/msm: split out vram initializationRob Clark1-24/+34
We'll want to extend this a bit to handle also a reserved-memory ("stolen") region, so that drm/msm can take-over bootloader splash screen. First split it out into it's own fxn to reduce noise in the following patch. Signed-off-by: Rob Clark <[email protected]>
2015-03-10regulator: fixes for regulator_set_optimum_mode name changeStephen Rothwell1-3/+3
Signed-off-by: Stephen Rothwell <[email protected]> Signed-off-by: Mark Brown <[email protected]>
2015-03-09Merge tag 'v4.0-rc3' into drm-nextDave Airlie6-53/+81
Linux 4.0-rc3 backmerge to fix two i915 conflicts, and get some mainline bug fixes needed for my testing box Conflicts: drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/intel_display.c
2015-03-05drm: Pass in new and old plane state to prepare_fb and cleanup_fbTvrtko Ursulin2-4/+8
Use cases like rotation require these hooks to have some context so they know how to prepare and cleanup the frame buffer correctly. For i915 specifically, object backing pages need to be mapped differently for different rotation modes and the driver needs to know which mapping to instantiate and which to tear down when transitioning between them. v2: Made passed in states const. (Daniel Vetter) [airlied: add mdp5 and atmel fixups] Signed-off-by: Tvrtko Ursulin <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: [email protected] Reviewed-by: Rob Clark <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2015-03-04drm/msm: kexec fixesRob Clark2-0/+10
In kexec environment, we are more likely to encounter irq's already enabled from previous environment. At which point we find that writes to disable/clear pending irq's are slightly less than useless without first enabling clocks. TODO: full blown state read-in so kexec'd kernel can inherit the mode already setup. Signed-off-by: Rob Clark <[email protected]>
2015-03-04drm/msm/mdp5: fix cursor blendingRob Clark1-1/+0
Seems like we just want BLEND_EN and not BLEND_TRANSP_EN (setting the latter results in black pixels in the cursor image treated as transparent). Signed-off-by: Rob Clark <[email protected]>
2015-03-04drm/msm/mdp5: fix cursor ROIRob Clark1-28/+40
If cursor is set near the edge of the screen, it is not valid to use the new cursor width/height as the ROI dimensions. Split out the ROI calc and use it both cursor_set and cursor_move. Signed-off-by: Rob Clark <[email protected]>
2015-03-04drm/msm/atomic: Don't leak atomic commit object when commit failsLaurent Pinchart1-1/+3
If the atomic commit fails due to completion wait interruption the atomic commit object is not freed and is thus leaked. Free it. Signed-off-by: Laurent Pinchart <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-03-04drm/msm/mdp5: Avoid flushing registers when CRTC is disabledStephane Viau1-7/+19
When a CRTC is disabled, no CTL is allocated to it (CRTC->ctl == NULL); in that case we should not try to FLUSH registers and do nothing instead. This can happen when we try to move a cursor but the CRTC's CTL (CONTROL) has not been allocated yet (inactive CRTC). It can also happens when we .atomic_check()/.atomic_flush() on a disabled CRTC. A CTL needs to be kept as long as the CRTC is alive. Releasing it after the last VBlank is safer than in .atomic_flush(). Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-03-04drm/msm: update generated headers (add 6th lm.base entry)Stephane Viau1-11/+4
Some target have up to 6 layer mixers (LM). Let the header file access the last LM's base address. Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-03-04drm/msm/mdp5: fixup "drm/msm: fix fallout of atomic dpms changes"Stephane Viau2-5/+5
Commit 0b776d457b94 ("drm/msm: fix fallout of atomic dpms changes") has a typo in both mdp5_encoder_helper_funcs and mdp5_crtc_helper_funcs definitions: .dpms entry should be replaced by .disable and .enable Also fixed a typo in mdp5_encoder_enable(). Note that these typos are only present for MDP5. MDP4 is fine. Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-02-24drm/atomic-helper: Rename commmit_post/pre_planesDaniel Vetter1-2/+2
These names only make sense because of backwards compatability with the order used by the crtc helper library. There's not really any real requirement in the ordering here. So rename them to something more descriptive and update the kerneldoc a bit. Motivated in a discussion with Laurent about how to restore plane state for dpms for drivers with runtime pm. v2: Squash in fixup from Stephen Rothwell to fix a conflict with tegra. Cc: Laurent Pinchart <[email protected]> Reviewed-by: Rob Clark <[email protected]> Acked-by: Laurent Pinchart <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-02-01drm/msm: add moduleparam to disable fbdevRob Clark1-1/+8
Useful to avoid recompiling to disable fbdev. Useful because otherwise the first modeset happens under console_lock (ie. debugging sadness). Signed-off-by: Rob Clark <[email protected]>
2015-02-01drm/msm: fix build error with W=1Rob Clark1-3/+0
Combining -Werror with all the extra warning flags that W=1 adds doesn't go so well. Especially because some of the warnings triggered are from included headers. So just drop -Werror. Signed-off-by: Rob Clark <[email protected]>
2015-02-01drm/msm/mdp5: Fix negative SMP block allocationStephane Viau1-2/+3
In case we request a number of SMP blocks which is lower than the already reserved blocks, we should not try to allocate a negative number, but 0 blocks instead. Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-02-01drm/msm/hdmi: disallow interlacedRob Clark1-1/+1
So after clarification from qcom, it seems mdp4 and mdp5 support *de*interlacing but not generating an interlaced signal. Which would explain why interlaced modes never worked properly. So disable in the one connector which was claiming to support interlaced. Signed-off-by: Rob Clark <[email protected]>
2015-02-01drm/msm/atomic: fix issue with gnome-shell waylandRob Clark1-1/+4
The gnome-shell wayland compositor triggers a setcrtc with an fb that is still being rendered, triggering the call to _wait_fence_interruptable(). But a NULL timeout means "don't wait, return -EBUSY if not ready", which in turn causes the setcrtc to fail. Signed-off-by: Rob Clark <[email protected]>
2015-02-01drm/msm/mdp5: Add hardware cursor supportBeeresh Gopal1-0/+164
This patch implements the hardware accelarated cursor support for MDP5 platforms. Signed-off-by: Beeresh Gopal <[email protected]> Signed-off-by: Wentao Xu <[email protected]> Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-02-01drm/msm/hdmi: rework hdmi configurations, using dt_match[]Stephane Viau1-59/+71
In the same idea mdp5_cfg was added, this change allows us to quickly add new instances, such as apq8084's HDMI in this case. Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-02-01drm/msm/hdmi: Add HDMI platform config for apq8084Stephane Viau1-0/+17
This change add the regulator/clock configuration for MDP5 v1.3. This config is close to the one already existing for 8x74, except that one more regulator is needed (hpd-5v-en). Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-02-01drm/msm/hdmi: use dynamic allocation for hdmi resourcesStephane Viau2-8/+28
Instead of reporting BUG_ON when resources arrays are not dimensioned correctly, this patch does a dynamic allocation of these arrays. This is needed for the following patches that add a regulator for a new target. Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2015-02-01drm/msm/mdp5: fix parameter type for mdp5_ctl_set_intf()Stephane Viau2-2/+2
mdp5_ctl_set_intf()'s second argument should be "int", not "enum mdp5_intf". The passed in value is "intf", not "intf_id". Signed-off-by: Stephane Viau <[email protected]> Signed-off-by: Rob Clark <[email protected]>
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