aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/msm/dp/dp_parser.c
AgeCommit message (Collapse)AuthorFilesLines
2020-09-15drm/msm/dp: Use qmp phy for DP PLL and PHYStephen Boyd1-3/+9
Make the necessary changes to the DP driver to use the qmp phy from the common phy framework instead of rolling our own in the drm subsystem. This also removes the PLL code and adds proper includes so things build. Cc: Jeykumar Sankaran <[email protected]> Cc: Chandan Uddaraju <[email protected]> Cc: Vara Reddy <[email protected]> Cc: Tanmay Shah <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Manu Gautam <[email protected]> Cc: Sandeep Maheswaram <[email protected]> Cc: Douglas Anderson <[email protected]> Cc: Sean Paul <[email protected]> Cc: Jonathan Marek <[email protected]> Cc: Dmitry Baryshkov <[email protected]> Cc: Rob Clark <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-15drm/msm/dp: Add DP compliance tests on Snapdragon ChipsetsKuogee Hsieh1-11/+31
add event thread to execute events serially from event queue. Also timeout mode is supported which allow an event be deferred to be executed at later time. Both link and phy compliant tests had been done successfully. Changes in v2: -- Fix potential deadlock by removing redundant connect_mutex -- Check and enable link clock during modeset -- Drop unused code and fix function prototypes. -- set sink power to normal operation state (D0) before DPCD read Changes in v3: -- push idle pattern at main link before timing generator off -- add timeout handles for both connect and disconnect Changes in v4: -- add ST_SUSPEND_PENDING to handles suspend/modeset test operations -- clear dp phy aux interrupt status when ERR_DPPHY_AUX error -- send segment addr during edid read -- clear bpp depth before MISC register write Changes in v5: -- add ST_SUSPENDED to fix crash at resume Changes in v6: -- at msm_dp_display_enable() do not return until resume_done to avoid kms commit timeout Signed-off-by: Kuogee Hsieh <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-15drm/msm/dp: add support for DP PLL driverChandan Uddaraju1-0/+2
Add the needed DP PLL specific files to support display port interface on msm targets. The DP driver calls the DP PLL driver registration. The DP driver sets the link and pixel clock sources. Changes in v2: -- Update copyright markings on all relevant files. -- Use DRM_DEBUG_DP for debug msgs. Changes in v4: -- Update the DP link clock provider names Changes in V5: -- Addressed comments from Stephen Boyd, Rob clark. Changes in V6: -- Remove PLL as separate driver and include PLL as DP module -- Remove redundant clock parsing from PLL module and make DP as clock provider -- Map USB3 DPCOM and PHY IO using hardcoded register address and move mapping form parser to PLL module -- Access DP PHY modules from same base address using offsets instead of deriving base address of individual module from device tree. -- Remove dp_pll_10nm_util.c and include its functionality in dp_pll_10nm.c -- Introduce new data structures private to PLL module Changes in v7: -- Remove DRM_MSM_DP_PLL config from Makefile and Kconfig -- Remove set_parent from determin_rate API -- Remove phy_pll_vco_div_clk from parent list -- Remove flag CLK_DIVIDER_ONE_BASED -- Remove redundant cell-index property parsing Changes in v8: -- Unregister hardware clocks during driver cleanup Changes in v9: -- Remove redundant Kconfig option DRM_MSM_DP_10NM_PLL Changes in v10: -- Limit 10nm PLL function scope Signed-off-by: Chandan Uddaraju <[email protected]> Signed-off-by: Vara Reddy <[email protected]> Signed-off-by: Tanmay Shah <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2020-09-15drm/msm/dp: add displayPort driver supportChandan Uddaraju1-0/+265
Add the needed displayPort files to enable DP driver on msm target. "dp_display" module is the main module that calls into other sub-modules. "dp_drm" file represents the interface between DRM framework and DP driver. Changes in v12: -- Add support of pm ops in display port driver -- Clear bpp depth bits before writing to MISC register -- Fix edid read Previous Change log: https://lkml.kernel.org/lkml/[email protected]/ Signed-off-by: Chandan Uddaraju <[email protected]> Signed-off-by: Vara Reddy <[email protected]> Signed-off-by: Tanmay Shah <[email protected]> Co-developed-by: Abhinav Kumar <[email protected]> Signed-off-by: Abhinav Kumar <[email protected]> Co-developed-by: Kuogee Hsieh <[email protected]> Signed-off-by: Kuogee Hsieh <[email protected]> Co-developed-by: Guenter Roeck <[email protected]> Signed-off-by: Guenter Roeck <[email protected]> Co-developed-by: Stephen Boyd <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Signed-off-by: Rob Clark <[email protected]>