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path: root/drivers/gpu/drm/meson/meson_registers.h
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2020-07-24Merge v5.8-rc6 into drm-nextDave Airlie1-0/+6
I've got a silent conflict + two trees based on fixes to merge. Fixes a silent merge with amdgpu Signed-off-by: Dave Airlie <[email protected]>
2020-07-03drm/meson: add Amlogic Video FBC registersNeil Armstrong1-0/+22
Add the registers of the VPU VD1 Amlogic FBC decoder module, and routing register. Signed-off-by: Neil Armstrong <[email protected]> Tested-by: Kevin Hilman <[email protected]> Reviewed-by: Kevin Hilman <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-07-02drm/meson: viu: fix setting the OSD burst length in VIU_OSD1_FIFO_CTRL_STATMartin Blumenstingl1-0/+6
The burst length is configured in VIU_OSD1_FIFO_CTRL_STAT[31] and VIU_OSD1_FIFO_CTRL_STAT[11:10]. The public S905D3 datasheet describes this as: - 0x0 = up to 24 per burst - 0x1 = up to 32 per burst - 0x2 = up to 48 per burst - 0x3 = up to 64 per burst - 0x4 = up to 96 per burst - 0x5 = up to 128 per burst The lower two bits map to VIU_OSD1_FIFO_CTRL_STAT[11:10] while the upper bit maps to VIU_OSD1_FIFO_CTRL_STAT[31]. Replace meson_viu_osd_burst_length_reg() with pre-defined macros which set these values. meson_viu_osd_burst_length_reg() always returned 0 (for the two used values: 32 and 64 at least) and thus incorrectly set the burst size to 24. Fixes: 147ae1cbaa1842 ("drm: meson: viu: use proper macros instead of magic constants") Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Tested-by: Christian Hewitt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-12-10drm/meson: add RDMA register bits definesNeil Armstrong1-0/+48
The Amlogic VPU embeds a "Register DMA" that can write a sequence of registers on the VPU AHB bus, either manually or triggered by an internal IRQ event like VSYNC or a line input counter. This adds the register defines. Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Kevin Hilman <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-12-10drm/meson: add AFBC decoder registers for GXM and G12ANeil Armstrong1-0/+62
Add the registers used to program the ARM Framebuffer Compression decoders used in the Amlogic GXM and G12A SoCs families. This also adds the routing and pipeline configuration bits and registers needed to enable AFBC support. Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Kevin Hilman <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-09drm: meson: global clean-upJulien Masson1-17/+14
This patch aims to: - Add general and TODO comments - Respect coding style for multi-line comments - Align macro definitions - Remove useless macro Signed-off-by: Julien Masson <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-09drm: meson: venc: use proper macros instead of magic constantsJulien Masson1-0/+51
This patch add new macros which are used to set the following registers: - ENCI_CFILT_CTRL - ENCI_CFILT_CTRL2 - ENCI_MACV_MAX_AMP - ENCI_VIDEO_MODE_ADV - ENCI_VFIFO2VD_CTL - ENCI_VIDEO_EN - ENCP_VIDEO_MODE - VPU_HDMI_SETTING - VENC_UPSAMPLE_CTRL0 - VENC_UPSAMPLE_CTRL1 - VENC_UPSAMPLE_CTRL2 - VENC_VDAC_FIFO_CTRL - VENC_VDAC_DAC0_FILT_CTRL0 - VENC_INTCTRL Signed-off-by: Julien Masson <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-09drm: meson: viu: use proper macros instead of magic constantsJulien Masson1-0/+27
This patch add new macros which are used to set the following registers: - VIU_SW_RESET - VIU_OSD1_CTRL_STAT - VIU_OSD2_CTRL_STAT - VIU_OSD1_FIFO_CTRL_STAT - VIU_OSD2_FIFO_CTRL_STAT - VIU_MISC_CTRL0 - VIU_OSD_BLEND_CTRL - OSD1_BLEND_SRC_CTRL - OSD2_BLEND_SRC_CTRL - DOLBY_PATH_CTRL Signed-off-by: Julien Masson <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> [narmstrong: fix OSD1_BLEND_SRC_CTRL register init value for G12A] Signed-off-by: Neil Armstrong <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-09drm: meson: vpp: use proper macros instead of magic constantsJulien Masson1-0/+8
This patch add new macros which are used to set the following registers: - VPP_OSD_SCALE_COEF_IDX - VPP_DOLBY_CTRL - VPP_OFIFO_SIZE - VPP_HOLD_LINES - VPP_SC_MISC - VPP_VADJ_CTRL Signed-off-by: Julien Masson <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> [narmstrong: put back 0x1020080 in VPP_DUMMY_DATA1 for GXM] Signed-off-by: Neil Armstrong <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-09drm: meson: drv: use macro when initializing vpuJulien Masson1-0/+1
This patch add new macro which is used to set WRARB/RDARB mode of the VPU. Signed-off-by: Julien Masson <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-09drm: meson: crtc: use proper macros instead of magic constantsJulien Masson1-0/+16
This patch add new macros which describe couple bits field of the following registers: - VD1_BLEND_SRC_CTRL - VPP_SC_MISC Signed-off-by: Julien Masson <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-09drm: meson: mask value when writing bits relaxedJulien Masson1-1/+1
The value used in the macro writel_bits_relaxed has to be masked since we don't want change the bits outside the mask. Signed-off-by: Julien Masson <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-17drm/meson: drop use of drmP.hSam Ravnborg1-0/+2
Drop use of the deprecated drmP.h header. While doing so used the opportunity to clean up a little so includes are now sorted and removed unused include files. In a few cases added some forwards to allow header files to built in different include order. Signed-off-by: Sam Ravnborg <[email protected]> Acked-by: Emil Velikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Cc: Neil Armstrong <[email protected]> Cc: Kevin Hilman <[email protected]> Cc: Maxime Jourdan <[email protected]> Cc: Jerome Brunet <[email protected]> Cc: [email protected] Cc: [email protected] Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner1-11/+1
Based on 3 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [graeme] [gregory] [gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema] [hk] [hemahk]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1105 file(s). Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Allison Randal <[email protected]> Reviewed-by: Richard Fontana <[email protected]> Reviewed-by: Kate Stewart <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-04-09drm/meson: Add registers for G12A SoCNeil Armstrong1-0/+247
This patch adds the new VPU registers added since the Amlogic GXM SoCs. Signed-off-by: Neil Armstrong <[email protected]> Tested-by: Jerome Brunet <[email protected]> Reviewed-by: Jerome Brunet <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-11-13drm/meson: Support Overlay plane for video renderingNeil Armstrong1-0/+3
The Amlogic Meson GX SoCs support an Overlay plane behind the primary plane for video rendering. This Overlay plane support various YUV layouts : - YUYV - NV12 / NV21 - YUV444 / 422 / 420 / 411 / 410 The scaler supports a wide range of scaling ratios, but for simplicity, plane atomic check limits the scaling from x5 to /5 in vertical and horizontal scaling. The z-order is fixed and always behind the primary plane and cannot be changed. The scaling parameter algorithm was taken from the Amlogic vendor kernel code and rewritten to match the atomic universal plane requirements. The video rendering using this overlay plane support has been tested using the new Kodi DRM-KMS Prime rendering path along the in-review V4L2 Mem2Mem Hardware Video Decoder up to 3840x2160 NV12 frames on various display modes. Signed-off-by: Neil Armstrong <[email protected]> Acked-by: Daniel Vetter <[email protected]> Tested-by: Maxime Jourdan <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-12-08drm/meson: Add missing VPU initNeil Armstrong1-0/+4
The VPU init misses these configurations values. Signed-off-by: Neil Armstrong <[email protected]> Acked-by: Chris Wilson <[email protected]> Tested-by: Jerome Brunet <[email protected]> Reviewed-by: Jerome Brunet <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2017-04-04drm/meson: Add missing HDMI registerNeil Armstrong1-0/+1
Add missing VPU HDMI register. Acked-by: Daniel Vetter <[email protected]> Signed-off-by: Neil Armstrong <[email protected]>
2016-12-01drm: Add support for Amlogic Meson Graphic ControllerNeil Armstrong1-0/+1395
The Amlogic Meson Display controller is composed of several components : DMC|---------------VPU (Video Processing Unit)----------------|------HHI------| | vd1 _______ _____________ _________________ | | D |-------| |----| | | | | HDMI PLL | D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK | R |-------| |----| Processing | | | | | | osd2 | | | |---| Enci ----------|----|-----VDAC------| R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----| A | osd1 | | | Blenders | | Encl ----------|----|---------------| M |-------|______|----|____________| |________________| | | ___|__________________________________________________________|_______________| VIU: Video Input Unit --------------------- The Video Input Unit is in charge of the pixel scanout from the DDR memory. It fetches the frames addresses, stride and parameters from the "Canvas" memory. This part is also in charge of the CSC (Colorspace Conversion). It can handle 2 OSD Planes and 2 Video Planes. VPP: Video Post Processing -------------------------- The Video Post Processing is in charge of the scaling and blending of the various planes into a single pixel stream. There is a special "pre-blending" used by the video planes with a dedicated scaler and a "post-blending" to merge with the OSD Planes. The OSD planes also have a dedicated scaler for one of the OSD. VENC: Video Encoders -------------------- The VENC is composed of the multiple pixel encoders : - ENCI : Interlace Video encoder for CVBS and Interlace HDMI - ENCP : Progressive Video Encoder for HDMI - ENCL : LCD LVDS Encoder The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock tree and provides the scanout clock to the VPP and VIU. The ENCI is connected to a single VDAC for Composite Output. The ENCI and ENCP are connected to an on-chip HDMI Transceiver. This driver is a DRM/KMS driver using the following DRM components : - GEM-CMA - PRIME-CMA - Atomic Modesetting - FBDev-CMA For the following SoCs : - GXBB Family (S905) - GXL Family (S905X, S905D) - GXM Family (S912) The current driver only supports the CVBS PAL/NTSC output modes, but the CRTC/Planes management should support bigger modes. But Advanced Colorspace Conversion, Scaling and HDMI Modes will be added in a second time. The Device Tree bindings makes use of the endpoints video interface definitions to connect to the optional CVBS and in the future the HDMI Connector nodes. HDMI Support is planned for a next release. Acked-by: Daniel Vetter <[email protected]> Signed-off-by: Neil Armstrong <[email protected]>
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