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2020-05-18drm/i915/selftests: Refactor sibling selectionChris Wilson1-41/+27
Tvrtko spotted that some selftests were using 'break' not 'continue', which will fail for discontiguous engine layouts such as on Icelake (which may have vcs0 and vcs2). Reported-by: Tvrtko Ursulin <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-16drm/i915: Mark check_shadow_context_ppgtt as maybe unusedNathan Chancellor1-1/+1
When CONFIG_DRM_I915_DEBUG_GEM is not set, clang warns: drivers/gpu/drm/i915/gvt/scheduler.c:884:1: warning: function 'check_shadow_context_ppgtt' is not needed and will not be emitted [-Wunneeded-internal-declaration] check_shadow_context_ppgtt(struct execlist_ring_context *c, struct intel_vgpu_mm *m) ^ 1 warning generated. This warning is similar to -Wunused-function but rather than warning that the function is completely unused, it warns that it is used in some expression within the file but that expression will be evaluated to a constant or be optimized away in the final assembly, essentially making it appeared used but really isn't. Usually, this happens when a function or variable is only used in sizeof, where it will appear to be used but will be evaluated at compile time and not be required to be emitted. In this case, the function is only used in GEM_BUG_ON, which is defined as BUILD_BUG_ON_INVALID, which intentionally follows this pattern. To fix this warning, add __maybe_unused to make it clear that this is intentional depending on the configuration. Fixes: bec3df930fbd ("drm/i915/gvt: Support PPGTT table load command") Link: https://github.com/ClangBuiltLinux/linux/issues/1027 Signed-off-by: Nathan Chancellor <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-16drm/i915/gem: Retry faulthandlers on ENOSPCChris Wilson1-1/+1
As we no longer use the shmemfs allocation directly, we do not expect to receive -ENOSPC from a backing store allocation. The potential sources for -ENOSPC are then our own internal eviction code, so the choice is either to kill the potential application with SIGBUS or to retry the faulthandler. In this patch we retry the fault handler, but since this is a should never happen condition, it is arguable that we gather up copious debug and kill the application. At worst, we cause an interruptible busy-wait, stalling the application -- all causes should be transient and the system should eventually recover. A small stall is hopefully a better outcome than random oomkiller. Signed-off-by: Chris Wilson <[email protected]> Cc: Matthew Auld <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-16drm/i915: Clean up dbuf debugs during .atomic_check()Ville Syrjälä1-7/+19
Combine the two per-pipe dbuf debugs into one, and use the canonical [CRTC:%d:%s] style to identify the crtc. Also use the same style as the plane code uses for the ddb start/end, and prefix bitmask properly with 0x to make it clear they are in fact bitmasks. The "how many total slices we are going to use" debug we move to outside the crtc loop so it gets printed only once at the end. Cc: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Stanislav Lisovskiy <[email protected]>
2020-05-16drm/i915: Move the dbuf pre/post plane updateVille Syrjälä3-39/+41
Encapsulate the dbuf state more by moving the pre/post plane functions out from intel_display.c. We stick them into intel_pm.c since that's where the rest of the code lives for now. Eventually we should add a new file for this stuff at which point we also need to decide if it makes sense to even split the wm code from the ddb code, or to keep them together. Cc: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Stanislav Lisovskiy <[email protected]>
2020-05-16drm/i915: Nuke skl_ddb_get_hw_state()Ville Syrjälä2-8/+0
skl_ddb_get_hw_state() is redundant and kinda called in thw wrong spot anyway. Just kill it. Cc: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Stanislav Lisovskiy <[email protected]>
2020-05-16drm/i915: Introduce proper dbuf stateVille Syrjälä6-99/+207
Add a global state to track the dbuf slices. Gets rid of all the nasty coupling between state->modeset and dbuf recomputation. Also we can now totally nuke state->active_pipe_changes. dev_priv->wm.distrust_bios_wm still remains, but that too will get nuked soon. Cc: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Stanislav Lisovskiy <[email protected]>
2020-05-16drm/i915: Unify the low level dbuf codeVille Syrjälä3-32/+24
The low level dbuf slice code is rather inconsitent with its functiona naming and organization. Make it more consistent. Also share the enable/disable functions between all platforms since the same code works just fine for all of them. Cc: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Stanislav Lisovskiy <[email protected]>
2020-05-16drm/i915: Polish some dbuf debugsVille Syrjälä1-19/+17
Polish some of the dbuf code to give more meaningful debug messages and whatnot. Also we can switch over to the per-device debugs/warns at the same time. Cc: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Stanislav Lisovskiy <[email protected]>
2020-05-16drm/i915: Make skl_compute_dbuf_slices() behave consistently for all platformsVille Syrjälä1-1/+1
Currently skl_compute_dbuf_slices() returns 0 for any inactive pipe on icl+, but returns BIT(S1) on pre-icl for any pipe (whether it's active or not). Let's make the behaviour consistent and always return 0 for any inactive pipe. Cc: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Stanislav Lisovskiy <[email protected]>
2020-05-15drm/i915: avoid unused scale_user_to_hw() warningArnd Bergmann1-10/+10
After the function is no longer marked 'inline', there is now a new warning pointing out that the only caller is inside of an #ifdef: drivers/gpu/drm/i915/display/intel_panel.c:493:12: warning: 'scale_user_to_hw' defined but not used [-Wunused-function] 493 | static u32 scale_user_to_hw(struct intel_connector *connector, | ^~~~~~~~~~~~~~~~ Move the function itself into that #ifdef as well. Fixes: 81b55ef1f47b ("drm/i915: drop a bunch of superfluous inlines") Signed-off-by: Arnd Bergmann <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-15drm/i915: Protect overlay colorkey macro argumentsVille Syrjälä1-4/+4
Put the customary () around the macro argument in the overlay colorkey macros. And while at switch to using a consistent case for the hex constants. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2020-05-15drm/i915: Enable pipe gamma for the overlayVille Syrjälä1-0/+2
We pass the plane data through the pipe gamma for all the other planes. Can't see why we should treat the overlay differently, so let's enable pipe gamma for it as well. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2020-05-15drm/i915: Configure overlay cc_out precision based on crtc gamma configVille Syrjälä1-2/+6
Put the overlay color conversion unit into 10bit mode if the pipe isn't using the 8bit legacy gamma. Not 100% sure this is what the intention of the bit was but makes at least some sense to me. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Acked-by: Chris Wilson <[email protected]>
2020-05-15drm/i915: Fix overlay colorkey for 30bpp and 8bppVille Syrjälä1-3/+11
As with the video sprites the colorkey is always specified as 8bpc. For 10bpc primary plane formats we just ignore the two lsbs of each component. For C8 we'll replicate the same key to each chanel, which is what the hardware wants. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2020-05-15drm/i915: Fix max cursor size for i915g/gmVille Syrjälä1-1/+2
Apparently the 128x128 and 256x256 ARGB cursor modes were only added on LPT/CST. While the display section of bspec isn't super clear on the subject, it does highlight these two modes in a different color, has a few changlog entries indicating the 256x256 mode was added for a LPT DCN, and that the 128x128 mode was also added later (though no DCN/platform note there). The "device dependencies" bspec section does list the 256x256x32 as a new feature for LPT/CST, and goes on to mention that current hw only has the 64x64x32 mode (which reinforces the notion that the 128x128 mode was also added at the same time). Testing on actual hardware confirms all of this. CI shows all the 128x128 and 256x256 tests failing on GDG, and my ALV definitely doesn't like them. So we shall limit GDG/ALV to 64x64 only. And while at it let's adjust the mobile gen2 case to list the two platforms explicitly so that the if-ladder looks reasonably uniform. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Acked-by: Chris Wilson <[email protected]>
2020-05-15drm/i915: Update DRIVER_DATE to 20200515Joonas Lahtinen1-2/+2
Signed-off-by: Joonas Lahtinen <[email protected]>
2020-05-14drm/i915: Extract i915_cs_timestamp_{ns_to_ticks,tick_to_ns}()Ville Syrjälä5-10/+17
Pull the code to do the CS timestamp ns<->ticks conversion into helpers and use them all over. The check in i915_perf_noa_delay_set() seems a bit dubious, so we switch it to do what I assume it wanted to do all along (ie. make sure the resulting delay in CS timestamp ticks doesn't exceed 32bits)? Cc: Lionel Landwerlin <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2020-05-14drm/i915: Store CS timestamp frequency in HzVille Syrjälä6-30/+30
kHz isn't accurate enough for storing the CS timestamp frequency on some of the platforms. Store the value in Hz instead. Cc: Lionel Landwerlin <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
2020-05-14drm/i915: Nuke pointless div by 64bitVille Syrjälä1-6/+5
Bunch of places use a 64bit divisor needlessly. Switch to 32bit divisor. Cc: Lionel Landwerlin <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2020-05-14drm/i915: Enable SAGV support for Gen12Stanislav Lisovskiy1-4/+0
Flip the switch and enable SAGV support for Gen12 also. Signed-off-by: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915: Restrict qgv points which don't have enough bandwidth.Stanislav Lisovskiy3-37/+162
According to BSpec 53998, we should try to restrict qgv points, which can't provide enough bandwidth for desired display configuration. Currently we are just comparing against all of those and take minimum(worst case). v2: Fixed wrong PCode reply mask, removed hardcoded values. v3: Forbid simultaneous legacy SAGV PCode requests and restricting qgv points. Put the actual restriction to commit function, added serialization(thanks to Ville) to prevent commit being applied out of order in case of nonblocking and/or nomodeset commits. v4: - Minor code refactoring, fixed few typos(thanks to James Ausmus) - Change the naming of qgv point masking/unmasking functions(James Ausmus). - Simplify the masking/unmasking operation itself, as we don't need to mask only single point per request(James Ausmus) - Reject and stick to highest bandwidth point if SAGV can't be enabled(BSpec) v5: - Add new mailbox reply codes, which seems to happen during boot time for TGL and indicate that QGV setting is not yet available. v6: - Increase number of supported QGV points to be in sync with BSpec. v7: - Rebased and resolved conflict to fix build failure. - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus) v8: - Don't report an error if we can't restrict qgv points, as SAGV can be disabled by BIOS, which is completely legal. So don't make CI panic. Instead if we detect that there is only 1 QGV point accessible just analyze if we can fit the required bandwidth requirements, but no need in restricting. v9: - Fix wrong QGV transition if we have 0 planes and no SAGV simultaneously. v10: - Fix CDCLK corruption, because of global state getting serialized without modeset, which caused copying of non-calculated cdclk to be copied to dev_priv(thanks to Ville for the hint). v11: - Remove unneeded headers and spaces(Matthew Roper) - Remove unneeded intel_qgv_info qi struct from bw check and zero out the needed one(Matthew Roper) - Changed QGV error message to have more clear meaning(Matthew Roper) - Use state->modeset_set instead of any_ms(Matthew Roper) - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used - Keep using crtc_state->hw.active instead of .enable(Matthew Roper) - Moved unrelated changes to other patch(using latency as parameter for plane wm calculation, moved to SAGV refactoring patch) v12: - Fix rebase conflict with own temporary SAGV/QGV fix. - Remove unnecessary mask being zero check when unmasking qgv points as this is completely legal(Matt Roper) - Check if we are setting the same mask as already being set in hardware to prevent error from PCode. - Fix error message when restricting/unrestricting qgv points to "mask/unmask" which sounds more accurate(Matt Roper) - Move sagv status setting to icl_get_bw_info from atomic check as this should be calculated only once.(Matt Roper) - Edited comments for the case when we can't enable SAGV and use only 1 QGV point with highest bandwidth to be more understandable.(Matt Roper) v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä) - Changed comment for zero new_mask in qgv points masking function to better reflect reality(Ville Syrjälä) - Simplified bit mask operation in qgv points masking function (Ville Syrjälä) - Moved intel_qgv_points_mask closer to gen11 SAGV disabling, however this still can't be under modeset condition(Ville Syrjälä) - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask (Ville Syrjälä) - Extracted PCode changes to separate patch.(Ville Syrjälä) - Now treat num_planes 0 same as 1 to avoid confusion and returning max_bw as 0, which would prevent choosing QGV point having max bandwidth in case if SAGV is not allowed, as per BSpec(Ville Syrjälä) - Do the actual qgv_points_mask swap in the same place as all other global state parts like cdclk are swapped. In the next patch, this all will be moved to bw state as global state, once new global state patch series from Ville lands v14: - Now using global state to serialize access to qgv points - Added global state locking back, otherwise we seem to read bw state in a wrong way. v15: - Added TODO comment for near atomic global state locking in bw code. v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed with Jani Nikula. - Take bw_state_changed flag into use. v17: - Moved qgv point related manipulations next to SAGV code, as those are semantically related(Ville Syrjälä) - Renamed those into intel_sagv_(pre)|(post)_plane_update (Ville Syrjälä) v18: - Move sagv related calls from commit tail into intel_sagv_(pre)|(post)_plane_update(Ville Syrjälä) v19: - Use intel_atomic_get_bw_(old)|(new)_state which is intended for commit tail stage. v20: - Return max bandwidth for 0 planes(Ville) - Constify old_bw_state in bw_atomic_check(Ville) - Removed some debugs(Ville) - Added data rate to debug print when no QGV points(Ville) - Removed some comments(Ville) v21, v22, v23: - Fixed rebase conflict v24: - Changed PCode mask to use ICL_ prefix v25: - Resolved rebase conflict v26: - Removed redundant NULL checks(Ville) - Removed redundant error prints(Ville) v27: - Use device specific drm_err(Ville) - Fixed parenthesis ident reported by checkpatch Line over 100 warns to be fixed together with existing code style. Signed-off-by: Stanislav Lisovskiy <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: James Ausmus <[email protected]> [vsyrjala: Drop duplicate intel_sagv_{pre,post}_plane_update() prototypes and drop unused NUM_SAGV_POINTS define] Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915: Add TGL+ SAGV supportStanislav Lisovskiy3-19/+99
Starting from TGL we need to have a separate wm0 values for SAGV and non-SAGV which affects how calculations are done. v2: Remove long lines v3: Removed COLOR_PLANE enum references v4, v5, v6: Fixed rebase conflict v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville) - Removed sagv_uv_wm0(Ville) - can_sagv->use_sagv_wm(Ville) v8: - Moved tgl_crtc_can_enable_sagv function up(Ville) - Changed comment regarding pipe_wm usage(Ville) - Call intel_can_enable_sagv and tgl_compute_sagv_wm only for Gen12(Ville) - Some sagv debugs removed(Ville) - skl_print_wm_changes improvements(Ville) - Do assignment instead of memcpy in skl_pipe_wm_get_hw_state(Ville) v9: - Removed can_sagv variable(Ville) - Removed spurious line(Ville) - Changed u32 to unsigned int as agreed(Ville) - Assign sagv only for gen12 in skl_pipe_wm_get_hw_state(Ville) Signed-off-by: Stanislav Lisovskiy <[email protected]> [vsyrjala: Remove the dead 'return false' from intel_crtc_can_enable_sagv()] Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14Merge tag 'gvt-next-2020-05-12' of https://github.com/intel/gvt-linux into ↵Joonas Lahtinen7-12/+155
drm-intel-next-queued gvt-next-2020-05-12 - Support PPGTT update via LRI cmd (Zhenyu) - Remove extra kmap for shadow ctx update (Zhenyu) - Move workload cleanup out of execlist handling code (Zhenyu) Signed-off-by: Joonas Lahtinen <[email protected]> From: Zhenyu Wang <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915/psr: Use new DP VSC SDP compute routine on PSRGwan-gyeong Mun4-43/+26
In order to use a common VSC SDP Colorimetry calculating code on PSR, it uses a new psr vsc sdp compute routine. Because PSR routine has its own scenario and timings of writing a VSC SDP, the current PSR routine needs to have its own drm_dp_vsc_sdp structure member variable on struct i915_psr. In order to calculate colorimetry information, intel_psr_update() function and intel_psr_enable() function extend a drm_connector_state argument. There are no changes to PSR mechanism. v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp v4: Rebased v8: Rebased v10: When a PSR is enabled, it needs to add DP_SDP_VSC to infoframes.enable. It is needed for comparing between HW and pipe_state of VSC_SDP. v11: If PSR is disabled by flag, it don't enable psr on pipe compute. v12: Fix an inconsistent indenting Signed-off-by: Gwan-gyeong Mun <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Reported-by: kbuild test robot <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915/dp: Add compute routine for DP PSR VSC SDPGwan-gyeong Mun2-2/+72
In order to use a common VSC SDP Colorimetry calculating code on PSR, it adds a compute routine for PSR VSC SDP. As PSR routine can not use infoframes.vsc of crtc state, it also adds new writing of DP SDPs (Secondary Data Packet) for PSR. PSR routine has its own scenario and timings of writing a VSC SDP. v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp v4: Use struct drm_device logging macros v10: 1) Fix packing of VSC SDP where Pixel Encoding/Colorimetry Format is not supported. 2) Change a checking of PSR state. Signed-off-by: Gwan-gyeong Mun <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915: Stop sending DP SDPs on ddi disableGwan-gyeong Mun1-0/+2
Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp() to make sure not to send VSC SDP and HDR Metadata Infoframe SDP. v5: Polish commit message [Uma] Signed-off-by: Gwan-gyeong Mun <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915: Program DP SDPs on pipe updatesGwan-gyeong Mun1-0/+1
Call intel_dp_set_infoframes() function on pipe updates to make sure that we send VSC SDP and HDR Metadata Infoframe SDP (when applicable) on fastsets. Signed-off-by: Gwan-gyeong Mun <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915: Fix enabled infoframe states of lspconGwan-gyeong Mun1-1/+1
Compared to implementation of DP and HDMI's encoder->infoframes_enabled, the lspcon's implementation returns its active state. (we expect enabled infoframe states of HW.) It leads to pipe state mismatch error when ddi_get_config is called. Because the current implementation of lspcon is not ready to support readout infoframes, we need to return 0 here. In order to support readout to lspcon, we need to implement read_infoframe and infoframes_enabled. And set_infoframes also have to set an appropriate bit on crtc_state->infoframes.enable Cc: Ville Syrjälä <[email protected]> Signed-off-by: Gwan-gyeong Mun <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915: Add state readout for DP VSC SDPGwan-gyeong Mun2-0/+45
Added state readout for DP VSC SDP and enabled state validation for DP VSC SDP. v2: Minor style fix v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp v4: Use struct drm_device logging macros v10: Skip checking of VSC SDP when a crtc config has psr. Signed-off-by: Gwan-gyeong Mun <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915: Add state readout for DP HDR Metadata Infoframe SDPGwan-gyeong Mun1-0/+8
Added state readout for DP HDR Metadata Infoframe SDP. v9: Rebased v10: Rebased Signed-off-by: Gwan-gyeong Mun <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915: Program DP SDPs with computed configsGwan-gyeong Mun3-237/+1
In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata Infoframe SDP), it replaces intel_dp_vsc_enable() function and intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes() function. And it removes unused functions. Before: intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() compute sdp configs and program sdp registers on enable callback of encoder. After: It separates computing of sdp configs and programming of sdp register. The compute config callback of encoder calls computing sdp configs. The enable callback of encoder calls programming sdp register. v3: Rebased v5: Polish commit message [Uma] v10: Rebased Signed-off-by: Gwan-gyeong Mun <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915: Include DP VSC SDP in the crtc state dumpGwan-gyeong Mun1-0/+13
Dump out the DP VSC SDP in the normal crtc state dump v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp Use drm core's DP VSC SDP logging function Signed-off-by: Gwan-gyeong Mun <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dumpGwan-gyeong Mun1-0/+3
Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump. HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata Infoframe SDP use the same member variable in infoframes of crtc state. Signed-off-by: Gwan-gyeong Mun <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915: Include HDMI DRM infoframe in the crtc state dumpGwan-gyeong Mun1-0/+3
Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the normal crtc state dump. Signed-off-by: Gwan-gyeong Mun <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915/dp: Read out DP SDPsGwan-gyeong Mun2-0/+190
It adds code to read the DP SDPs from the video DIP and unpack them into the crtc state. It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP In order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function. It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and [Table 2-117: VSC SDP Payload for DB16 through DB18] In order to unpack DP HDR Metadata Infoframe SDP, it adds intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP 1.4a spec. ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame]. A naming rule and style of intel_read_dp_sdp() function references intel_read_infoframe() function of intel_hdmi.c v2: Minor style fix v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp v4: Use struct drm_device logging macros v5: Addressed review comments from Uma - Polish commit message and comments - Combine the if checks of sdp.HB2 and sdp.HB3 - Add 6bpc to unpacking of VSC SDP Signed-off-by: Gwan-gyeong Mun <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915/gt: Transfer old virtual breadcrumbs to irq_workerChris Wilson4-34/+57
The second try at staging the transfer of the breadcrumb. In part one, we realised we could not simply move to the second engine as we were only holding the breadcrumb lock on the first. So in commit 6c81e21a4742 ("drm/i915/gt: Stage the transfer of the virtual breadcrumb"), we removed it from the first engine and marked up this request to reattach the signaling on the new engine. However, this failed to take into account that we only attach the breadcrumb if the new request is added at the start of the queue, which if we are transferring, it is because we know there to be a request to be signaled (and hence we would not be attached). In this attempt, we try to transfer the completed requests to the irq_worker on its rq->engine->breadcrumbs. This preserves the coupling between the rq and its breadcrumbs, so that i915_request_cancel_breadcrumb() does not attempt to manipulate the list under the wrong lock. v2: Code sharing is fun. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1862 Fixes: 6c81e21a4742 ("drm/i915/gt: Stage the transfer of the virtual breadcrumb") Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915/selftests: Always call the provided engine->emit_init_breadcrumbChris Wilson2-4/+2
While this does not appear to fix any issues, the backend itself knows when it wants to emit a breadcrumb, so let it make the final call. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915: Show per-engine default property values in sysfsChris Wilson3-1/+97
By providing the default values configured into the kernel via sysfs, it is much more convenient for userspace to restore those sane defaults, or at least know what are considered good baseline. This is useful, for example, to cleanup after any failed userspace prior to commencing new jobs. /sys/class/drm/card0/engine/rcs0/ ├── capabilities ├── class ├── .defaults │   ├── heartbeat_interval_ms │   ├── max_busywait_duration_ns │   ├── preempt_timeout_ms │   ├── stop_timeout_ms │   └── timeslice_duration_ms ├── heartbeat_interval_ms ├── instance ├── known_capabilities ├── max_busywait_duration_ns ├── mmio_base ├── name ├── preempt_timeout_ms ├── stop_timeout_ms └── timeslice_duration_ms Signed-off-by: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Reviewed-by: Maciej Patelczyk <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14drm/i915: Drop no-semaphore boostingChris Wilson8-73/+11
Now that we have fast timeslicing on semaphores, we no longer need to prioritise none-semaphore work as we will yield any work blocked on a semaphore to the next in the queue. Previously with no timeslicing, blocking on the semaphore caused extremely bad scheduling with multiple clients utilising multiple rings. Now, there is no impact and we can remove the complication. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-14Merge tag 'drm-intel-next-2020-04-30' of ↵Dave Airlie107-1954/+6183
git://anongit.freedesktop.org/drm/drm-intel into drm-next Driver Changes: - Fix GitLab #1698: Performance regression with Linux 5.7-rc1 on Iris Plus 655 and 4K screen (Chris) - Add Wa_14011059788 for Tigerlake (Matt A) - Add per ctx batchbuffer wa for timestamp for Gen12 (Mika) - Use indirect ctx bb to load cmd buffer control value from context image to avoid corruption (Mika) - Enable DP Display Audio WA (Uma, Jani) - Update forcewake firmware ranges for Icelake (Radhakrishna) - Add missing deinitialization cases of load failure for display (Jose) - Implement TC cold sequences for Icelake and Tigerlake (Jose) - Unbreak enable_dpcd_backlight modparam (Lyude) - Move the late flush_submission in retire to the end (Chris) - Demote "Reducing compressed framebufer size" message to info (Peter) - Push MST link retraining to the hotplug work (Ville) - Hold obj->vma.lock over for_each_ggtt_vma() (Chris) - Fix timeout handling during TypeC AUX power well enabling for ICL (Imre) - Fix skl+ non-scaled pfit modes (Ville) - Prefer soft-rc6 over RPS DOWN_TIMEOUT (Chris) - Sanitize GT first before poisoning HWSP (Chris) - Fix up clock RPS frequency readout (Chris) - Avoid reusing the same logical CCID (Chris) - Avoid dereferencing a dead context (Chris) - Always enable busy-stats for execlists (Chris) - Apply the aggressive downclocking to parking (Chris) - Restore aggressive post-boost downclocking (Chris) - Scrub execlists state on resume (Chris) - Add debugfs attributes for LPSP (Ansuman) - Improvements to kernel selftests (Chris, Mika) - Add tiled blits selftest (Zbigniew) - Fix error handling in __live_lrc_indirect_ctx_bb() (Dan) - Add pre/post plane updates for SAGV (Stanislav) - Add ICL PG3 PW ID for EHL (Anshuman) - Fix Sphinx build duplicate label warning (Jani) - Error log non-zero audio power refcount after unbind (Jani) - Remove object_is_locked assertion from unpin_from_display_plane (Chris) - Use single set of AUX powerwell ops for gen11+ (Matt R) - Prefer drm_WARN_ON over WARN_ON (Pankaj) - Poison residual state [HWSP] across resume (Chris, Tvrtko) - Convert request-before-CS assertion to debug (Chris) - Carefully order virtual_submission_tasklet (Chris) - Check carefully for an idle engine in wait-for-idle (Chris) - Only close vma we open (Chris) - Trace RPS events (Chris) - Use the RPM config register to determine clk frequencies (Chris) - Drop rq->ring->vma peeking from error capture (Chris) - Check preempt-timeout target before submit_ports (Chris) - Check HWSP cacheline is valid before acquiring (Chris) - Use proper fault mask in interrupt postinstall too (Matt R) - Keep a no-frills swappable copy of the default context state (Chris) - Add atomic helpers for bandwidth (Stanislav) - Refactor setting dma info to a common helper from device info (Michael) - Refactor DDI transcoder code for clairty (Ville) - Extend PG3 power well ID to ICL (Anshuman) - Refactor PFIT code for readability and future extensibility (Ville) - Clarify code split between intel_ddi.c and intel_dp.c (Ville) - Move out code to return the digital_port of the aux ch (Jose) - Move rps.enabled/active and use of RPS interrupts to flags (Chris) - Remove superfluous inlines and dead code (Jani) - Re-disable -Wframe-address from top-level Makefile (Nick) - Static checker and spelling fixes (Colin, Nathan) - Split long lines (Ville) Signed-off-by: Dave Airlie <[email protected]> From: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-13drm/i915: Handle idling during i915_gem_evict_something busy loopsChris Wilson1-14/+12
i915_gem_evict_something() is charged with finding a slot within the GTT that we may reuse. Since our goal is not to stall, we first look for a slot that only overlaps idle vma. To this end, on the first pass we move any active vma to the end of the search list. However, we only stopped moving active vma after we see the first active vma twice. If during the search, that first active vma completed, we would not notice and keep on extending the search list. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1746 Fixes: 2850748ef876 ("drm/i915: Pull i915_vma_pin under the vm->mutex") Fixes: b1e3177bd1d8 ("drm/i915: Coordinate i915_active with its own mutex") Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: <[email protected]> # v5.5+ Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit 73e28cc40bf00b5d168cb8f5cff1ae63e9097446) Signed-off-by: Rodrigo Vivi <[email protected]>
2020-05-13drm/i915: Drop I915_RESET_TIMEOUT and friendsChris Wilson1-7/+0
These were used to set various timeouts for the reset procedure (deciding when the engine was dead, and even if the reset itself was not making forward progress). No longer used. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Maciej Patelczyk <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-13drm/i915: Mark the addition of the initial-breadcrumb in the requestChris Wilson3-9/+30
The initial-breadcrumb is used to mark the end of the awaiting and the beginning of the user payload. We verify that we do not start the user payload before all signaler are completed, checking our semaphore setup by looking for the initial breadcrumb being written too early. We also want to ensure that we do not add semaphore waits after we have already closed the semaphore section, an issue for later deferred waits. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-13drm/i915/gem: Remove redundant exec_fenceChris Wilson1-26/+14
Since there can only be one of in_fence/exec_fence, just use the single in_fence local. v2: Consolidate lookup Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-13drm/i915: Remove duplicate inline specifier on write_pteNathan Chancellor1-1/+1
When building with clang: drivers/gpu/drm/i915/gt/gen8_ppgtt.c:392:24: warning: duplicate 'inline' declaration specifier [-Wduplicate-decl-specifier] declaration specifier [-Wduplicate-decl-specifier] static __always_inline inline void ^ include/linux/compiler_types.h:138:16: note: expanded from macro 'inline' #define inline inline __gnu_inline __inline_maybe_unused notrace ^ 1 warning generated. __always_inline is defined as 'inline __attribute__((__always_inline))' so we do not need to specify it twice. Fixes: 84eac0c65940 ("drm/i915/gt: Force pte cacheline to main memory") Link: https://github.com/ClangBuiltLinux/linux/issues/1024 Reported-by: kbuild test robot <[email protected]> Signed-off-by: Nathan Chancellor <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-13drm/i915/gt: Suspend tasklets before resume sanitizationChris Wilson1-4/+4
It is possible for a residual tasklet to be pending execution as we resume (whether that's some prior test kicking off the tasklet, or if we are in a suspend/resume stress test). As such, we do not want that tasklet to execute in the middle of our sanitization, such that it sees the poisoned state. For example, <4>[ 449.386553] invalid opcode: 0000 [#1] PREEMPT SMP NOPTI <4>[ 449.386555] CPU: 1 PID: 5115 Comm: i915_selftest Tainted: G U W 5.7.0-rc4-CI-CI_DRM_8472+ #1 <4>[ 449.386556] Hardware name: Intel Corporation Ice Lake Client Platform/IceLake U DDR4 SODIMM PD RVP TLC, BIOS ICLSFWR1.R00.3183.A00.1905020411 05/02/2019 <4>[ 449.386585] RIP: 0010:process_csb+0x6bf/0x830 [i915] <4>[ 449.386588] Code: 00 48 c7 c2 10 bc 4c a0 48 c7 c7 d4 75 34 a0 e8 87 0e e6 e0 bf 01 00 00 00 e8 9d e0 e5 e0 31 f6 bf 09 00 00 00 e8 e1 ba d6 e0 <0f> 0b 8b 87 10 05 00 00 85 c0 0f 85 5f f9 ff ff 48 c7 c1 70 a5 4f <4>[ 449.386591] RSP: 0018:ffffc90000170ea0 EFLAGS: 00010297 <4>[ 449.386594] RAX: 0000000080000101 RBX: 0000000000000000 RCX: 0000000000000000 <4>[ 449.386596] RDX: ffff88849d5bc040 RSI: 0000000000000000 RDI: 0000000000000009 <4>[ 449.386598] RBP: ffffc90000170f00 R08: 0000000000000000 R09: 0000000000000000 <4>[ 449.386600] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88843ccea018 <4>[ 449.386602] R13: ffff88843ccea658 R14: ffff88843ccea640 R15: ffff88843ccea000 <4>[ 449.386605] FS: 00007f826a813300(0000) GS:ffff88849fe80000(0000) knlGS:0000000000000000 <4>[ 449.386607] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4>[ 449.386609] CR2: 0000560366b94280 CR3: 000000048ba02002 CR4: 0000000000760ee0 <4>[ 449.386611] PKRU: 55555554 <4>[ 449.386613] Call Trace: <4>[ 449.386616] <IRQ> <4>[ 449.386646] ? execlists_submission_tasklet+0xcf/0x140 [i915] <4>[ 449.386674] execlists_submission_tasklet+0x2f/0x140 [i915] <4>[ 449.386679] tasklet_action_common.isra.16+0x6c/0x1c0 <4>[ 449.386684] __do_softirq+0xdf/0x49e <4>[ 449.386687] irq_exit+0xba/0xc0 <4>[ 449.386690] smp_apic_timer_interrupt+0xb7/0x280 <4>[ 449.386693] apic_timer_interrupt+0xf/0x20 <4>[ 449.386695] </IRQ> <4>[ 449.386698] RIP: 0010:_raw_spin_unlock_irqrestore+0x49/0x60 <4>[ 449.386701] Code: c7 02 75 1f 53 9d e8 26 ab 75 ff bf 01 00 00 00 e8 7c a3 69 ff 65 8b 05 7d 9b 5c 7e 85 c0 74 0c 5b 5d c3 e8 09 aa 75 ff 53 9d <eb> df e8 ca 39 5b ff 5b 5d c3 0f 1f 00 66 2e 0f 1f 84 00 00 00 00 <4>[ 449.386703] RSP: 0018:ffffc90000a6b950 EFLAGS: 00000202 ORIG_RAX: ffffffffffffff13 <4>[ 449.386706] RAX: 0000000080000001 RBX: 0000000000000202 RCX: 0000000000000000 <4>[ 449.386708] RDX: ffff88849d5bc040 RSI: ffff88849d5bc900 RDI: ffffffff82386f12 <4>[ 449.386710] RBP: ffff88847d400f00 R08: ffff88849d5bc900 R09: 0000000000000000 <4>[ 449.386712] R10: 0000000000000000 R11: 0000000000000000 R12: 00000000ffff0b0b <4>[ 449.386714] R13: 000000000000000c R14: ffff88847d40bf70 R15: ffff88847d40cef8 <4>[ 449.386742] reset_csb_pointers+0x59/0x140 [i915] <4>[ 449.386769] execlists_sanitize+0x3e/0x60 [i915] <4>[ 449.386797] gt_sanitize+0xd6/0x260 [i915] As part of the reset preparation, engine->reset.prepare() prevents the tasklet from running, so pull the sanitization inside the critical section for reset. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1812 Fixes: 23122a4d992b ("drm/i915/gt: Scrub execlists state on resume") Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-13drm/i915: Make active_pipes check skl specificStanislav Lisovskiy2-6/+11
Seems that only skl needs to have SAGV turned off for multipipe scenarios, so lets do it this way. If anything blows up - we can always revert this patch. v2: Changed if condition to look better (Ville). Signed-off-by: Stanislav Lisovskiy <[email protected]> [vsyrjala: wrapped long line to appease checkpatch] Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-13drm/i915: Extract skl SAGV checkingStanislav Lisovskiy1-2/+8
Introduce platform dependent SAGV checking in combination with bandwidth state pipe SAGV mask. This is preparation to adding TGL support, which requires different way of SAGV checking. v2, v3, v4, v5, v6: Fix rebase conflict v7: - Nuke icl specific function, use skl for icl as well, gen specific active_pipes check to be added in the next patch(Ville) v8: - Use more generic intel_crtc_can_enable_sagv for checking(Ville) Signed-off-by: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-05-13drm/i915: Introduce skl_plane_wm_level accessor.Stanislav Lisovskiy1-2/+21
For future Gen12 SAGV implementation we need to seemlessly alter wm levels calculated, depending on whether we are allowed to enable SAGV or not. So this accessor will give additional flexibility to do that. Currently this accessor is still simply working as "pass-through" function. This will be changed in next coming patches from this series. v2: - plane_id -> plane->id(Ville Syrjälä) - Moved wm_level var to have more local scope (Ville Syrjälä) - Renamed yuv to color_plane(Ville Syrjälä) in skl_plane_wm_level v3: - plane->id -> plane_id(this time for real, Ville Syrjälä) - Changed colorplane id type from boolean to int as index (Ville Syrjälä) - Moved crtc_state param so that it is first now (Ville Syrjälä) - Moved wm_level declaration to tigher scope in skl_write_plane_wm(Ville Syrjälä) v4: - Started to use enum values for color plane - Do sizeof for a type what we are memset'ing - Zero out wm_uv as well(Ville Syrjälä) v5: - Fixed rebase conflict caused by COLOR_PLANE_* enum removal v6: - Do not use skl_plane_wm_level accessor in skl_allocate_pipe_ddb v7: - Get rid of wm_uv, which is not used in skl_plane_write_wm(Ville) Signed-off-by: Stanislav Lisovskiy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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