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2014-07-23drm/i915: Improve PSR debugfs outputDaniel Vetter1-0/+6
Add busy_frontbuffer_bits and locking. Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-23drm/i915: Fix up PSR frontbuffer trackingDaniel Vetter4-49/+85
I've tried to split this up, but all the changes are so tightly related that I didn't find a good way to do this without breaking bisecting. Essentially this completely changes how psr is glued into the overall driver, and there's not much you can do to soften such a paradigm change. - Use frontbuffer tracking bits stuff to separate disable and re-enable. - Don't re-check everything in the psr work. We have now accurate tracking for everything, so no need to check for sprites or tiling really. Allows us to ditch tons of locks. - That in turn allows us to properly cancel the work in the disable function - no more deadlocks. - Add a check for HSW sprites and force a flush. Apparently the hardware doesn't forward the flushing when updating the sprite base address. We can do the same trick everywhere else we have such issues, e.g. on baytrail with ... everything. - Don't re-enable psr with a delay in psr_exit. It really must be turned off forever if we detect a gtt write. At least with the current frontbuffer render tracking. Userspace can do a busy ioctl call or no-op pageflip to re-enable psr. - Drop redundant checks for crtc and crtc->active - now that they're only called from enable this is guaranteed. - Fix up the hsw port check. eDP can also happen on port D, but the issue is exactly that it doesn't work there. So an || check is wrong. - We still schedule the psr work with a delay. The frontbuffer flushing interface mandates that we upload the next full frame, so need to wait a bit. Once we have single-shot frame uploads we can do better here. v2: Don't enable psr initially, rely upon the fb flush of the initial plane setup for that. Gives us more unified code flow and makes the crtc enable sequence less a special case. v3: s/psr_exit/psr_invalidate/ for consistency v4: Fixup whitespace. v5: Correctly bail out of psr_invalidate/flush when dev_priv->psr.enabled is NULL. Spotted by Rodrigo. v6: - Only schedule work when there's work to do. Fixes WARNINGs reported by Rodrigo. - Comments Chris requested to clarify the code. v7: Fix conflict on rebase (Rodrigo) Cc: Chris Wilson <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> (v6) Signed-off-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-23drm/i915: Add locking to psr codeDaniel Vetter2-7/+32
It's not really optional to have locking ... The ugly part is how much locking the psr work needs since it has to recheck everything. Which is way too much. But we need to ditch the psr work in it's current form anyway and implement proper frontbuffer tracking. The other nasty bit that had to go was the delayed work cancle in psr_exit. Which means a bunch of races just became a bit more likely, but mea culpa. v2: Fixup HAS_PSR checks, resulting in uninitialized mutex issues. Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-23drm/i915: More checks for psr.enabledDaniel Vetter1-0/+6
We need to make sure that no one else is using this in the enable function and also that the work item hasn't raced with the disabled function. v2: Improve bisectability by moving one hunk to an earlier patch. v3: added missing dev_priv declaration (Rodrigo) Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> (v2) Signed-off-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-23drm/i915: Lock down psr sw/hw state trackingDaniel Vetter1-20/+23
Make sure we track the sw side (psr.active) correctly and WARN everywhere it might get out of sync with the hw. v2: Fixup WARN_ON logic inversion, reported by Rodrigo. Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-23drm/i915: Don't try to disable psr harder from the work itemDaniel Vetter1-3/+1
It's disabled already except when we've raced. Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-23drm/i915: Track the psr dp connector in dev_priv->psr.enabledDaniel Vetter3-15/+12
Trying to fish that one out through looping is a bit a locking nightmare. So just set it and use it in the work struct. v2: - Don't Oops in psr_work, spotted by Rodrigo. - Fix compile warning. Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-23drm/i915: Add a FIXME about drrs/psr interactionsDaniel Vetter1-0/+5
Can't review this right now due to lack of DRRS code. Reviewed-by: Rodrigo Vivi <[email protected]> Cc: Vandana Kannan <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-23drm/i915: Run psr_setup unconditionallyDaniel Vetter2-7/+1
Due to runtime pm and system s/r we need to restore hw state every time we enable a pipe again. Hence trying to avoid that is just pointless book-keeping which Rodrigo then tried to work around by manually adding psr_setup calls to our resume code. Much simpler to just remove code instead. v2: Properly bail out of psr exit if psr isn't enabled. Spotted by Rodrigo. Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-23drm/i915: Power gating display wells during i915_pm_suspendBorun Fu4-17/+25
On VLV, after i915_pm_suspend display power wells are staying power ungated. So, after initiating mem sleep "echo mem > /sys/power/state" Display is staing D0 State. There might be better way/place to power gate these wells. Also, we need to make sure that if wells are power gated due to DPMS OFF sequence, they need not be turned off by i915_pm_suspend again. v2: Extracted helper for intel_crtc_disable and power gating CRTC power wells. [Daniel] Cc: Imre Deak <[email protected]> Cc: Paulo Zanoni <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Jani Nikula <[email protected]> Change-Id: I34c80da66aa24c423a5576c68aa1f3a8d0f43848 Signed-off-by: Borun Fu <[email protected]> Signed-off-by: Sagar Kamble <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-22drm/i915: fix build without fbdev.Chris Wilson1-4/+18
Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2014-07-22drm/i915: fix freeze with blank screen booting highmemHugh Dickins1-2/+2
x86_64 boots and displays fine, but booting x86_32 with CONFIG_HIGHMEM has frozen with a blank screen throughout 3.16-rc on this ThinkPad T420s, with i915 generation 6 graphics. Fix 9d0a6fa6c5e6 ("drm/i915: add render state initialization"): kunmap() takes struct page * argument, not virtual address. Which the compiler kindly points out, if you use the appropriate u32 *batch, instead of silencing it with a void *. Why did bisection lead decisively to nearby 229b0489aa75 ("drm/i915: add null render states for gen6, gen7 and gen8")? Because the u32 deposited at that virtual address by the previous stub failed the PageHighMem test, and so did no harm. Signed-off-by: Hugh Dickins <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-22drm/i915: mst topology dumper in debugfs (v0.2)Dave Airlie1-0/+23
use the mst helper code to dump the topology in debugfs. v0.2: drop is_mst check - as we want to dump other info Reviewed-by: Todd Previte <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2014-07-22drm/i915: add DP 1.2 MST support (v0.7)Dave Airlie12-38/+934
This adds DP 1.2 MST support on Haswell systems. Notes: a) this reworks irq handling for DP MST ports, so that we can avoid the mode config locking in the current hpd handlers, as we need to process up/down msgs at a better time. Changes since v0.1: use PORT_PCH_HOTPLUG to detect short vs long pulses add a workqueue to deal with digital events as they can get blocked on the main workqueue beyong mode_config mutex fix a bunch of modeset checker warnings acks irqs in the driver cleanup the MST encoders Changes since v0.2: check irq status again in work handler move around bring up and tear down to fix DPMS on/off use path properties. Changes since v0.3: updates for mst apis more state checker fixes irq handling improvements fbcon handling support improved reference counting of link - fixes redocking. Changes since v0.4: handle gpu reset hpd reinit without oopsing check link status on HPD irqs fix suspend/resume Changes since v0.5: use proper functions to get max link/lane counts fix another checker backtrace - due to connectors disappearing. set output type in more places fro, unknown->displayport don't talk to devices if no HPD asserted check mst on short irqs only check link status properly rebase onto prepping irq changes. drop unsued force_act Changes since v0.6: cleanup unused struct entry. [airlied: fix some sparse warnings]. Reviewed-by: Todd Previte <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2014-07-21drm/i915: Reorder the semaphore deadlock check, againChris Wilson1-7/+4
commit 4be173813e57c7298103a83155c2391b5b167b4c Author: Chris Wilson <[email protected]> Date: Fri Jun 6 10:22:29 2014 +0100 drm/i915: Reorder semaphore deadlock check did the majority of the work, but it missed one crucial detail: The check for the unkickable deadlock on this ring must come after the check whether the ring that we are waiting on has already passed its target seqno. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80709 Tested-by: Stefan Huber <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Jani Nikula <[email protected]> Cc: [email protected] Signed-off-by: Daniel Vetter <[email protected]>
2014-07-21Merge 3.16-rc6 into driver-core-nextGreg Kroah-Hartman12-30/+156
We want the platform changes in here as well. Signed-off-by: Greg Kroah-Hartman <[email protected]>
2014-07-21drm/i915: split conversion function out into separate functionDave Airlie1-13/+18
for MST I need to reuse this, so just move it now. Signed-off-by: Dave Airlie <[email protected]>
2014-07-21drm/i915: check connector->encoder before using it.Dave Airlie3-18/+27
DP MST will need connectors that aren't connected to specific encoders, add some checks in advance to avoid oopses. Reviewed-by: Todd Previte <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2014-07-21i915: split some DP modesetting code into a separate functionDave Airlie2-5/+14
this is just prep work for mst support. Reviewed-by: Todd Previte <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2014-07-21drm/i915: add some registers need for displayport MST support.Dave Airlie1-2/+9
These are just from the Haswell spec. Reviewed-by: Todd Previte <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2014-07-21drm/i915: fix psr match conditions screw ups.Dave Airlie1-3/+4
Not enough brown paper bags, you'll have to share one. (oops below). The initial match condition code was racy (locking is coming I hear). then along came: cd234b0bfd5ab012e42274b24aae420fa1823d58 drm/i915: Do not dereference NULL crtc or fb until after checking Chris made an attempt to fix it, Ben "reviewed" it. Daniel merged it. Then drm/i915: Make use of intel_fb_obj() (v2) 2ff8fde1ea0992dfd735dce94f8cae2aacff8e5c made it worse by removing the obj check later. All in all, my laptop can't barely turn off the display without hitting this. Posted to #intel-gfx out of niceness, but I've merged this already into drm-next. Here's an oops. [ 11.528185] BUG: unable to handle kernel NULL pointer dereference at 00000000000000d0 [ 11.528233] IP: [<ffffffffa0161fde>] intel_edp_psr_match_conditions+0x1e/0x2e0 [i915] [ 11.528294] PGD 35bc0067 PUD c997c067 PMD 0 [ 11.528321] Oops: 0000 [#1] SMP [ 11.528916] CPU: 3 PID: 244 Comm: kworker/3:2 Not tainted 3.16.0-rc4+ #17 [ 11.528949] Hardware name: LENOVO 20ARS25701/20ARS25701, BIOS GJET72WW (2.22 ) 02/21/2014 [ 11.529004] Workqueue: events intel_edp_psr_work [i915] [ 11.529031] task: ffff8803079fdaa0 ti: ffff8803079c4000 task.ti: ffff8803079c4000 [ 11.529067] RIP: 0010:[<ffffffffa0161fde>] [<ffffffffa0161fde>] intel_edp_psr_match_conditions+0x1e/0x2e0 [i915] [ 11.529129] RSP: 0018:ffff8803079c7d40 EFLAGS: 00010246 [ 11.529155] RAX: 0000000000000000 RBX: ffff88030c11c000 RCX: c000000000000000 [ 11.529189] RDX: 0000000000000001 RSI: 1df0000000000000 RDI: ffff88030c1190d8 [ 11.529222] RBP: ffff8803079c7d60 R08: ffffffff82691140 R09: 0000000000000000 [ 11.529256] R10: ffff8803079fdaa0 R11: 3e00000000000000 R12: ffff88030c11c728 [ 11.529290] R13: ffff88030c1190d8 R14: ffff88031e2d8e00 R15: 00000000000000c0 [ 11.529324] FS: 0000000000000000(0000) GS:ffff88031e2c0000(0000) knlGS:0000000000000000 [ 11.529361] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 11.529389] CR2: 00000000000000d0 CR3: 00000000c8d9d000 CR4: 00000000001407e0 [ 11.529423] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 11.529457] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 11.529489] Stack: [ 11.529500] ffff88030c119000 ffff88030c11c728 ffff88030c1190d8 ffff88031e2d8e00 [ 11.529541] ffff8803079c7d88 ffffffffa01679b2 ffff880035b29a80 ffff880307909f00 [ 11.529583] ffff88031e2d4740 ffff8803079c7df8 ffffffff810a78ab ffffffff810a7849 [ 11.529624] Call Trace: [ 11.529654] [<ffffffffa01679b2>] intel_edp_psr_work+0x52/0x90 [i915] [ 11.529689] [<ffffffff810a78ab>] process_one_work+0x1db/0x540 [ 11.529719] [<ffffffff810a7849>] ? process_one_work+0x179/0x540 [ 11.529750] [<ffffffff810a81ed>] worker_thread+0x11d/0x520 [ 11.529779] [<ffffffff810a80d0>] ? create_and_start_worker+0x60/0x60 [ 11.529810] [<ffffffff810aeb04>] kthread+0xe4/0x100 [ 11.529836] [<ffffffff810aea20>] ? kthread_create_on_node+0x200/0x200 [ 11.529870] [<ffffffff81705ebc>] ret_from_fork+0x7c/0xb0 [ 11.529896] [<ffffffff810aea20>] ? kthread_create_on_node+0x200/0x200 [ 11.529926] Code: ba 31 13 f0 c9 85 f6 75 84 eb d0 66 90 0f 1f 44 00 00 55 48 89 e5 41 56 41 55 41 54 53 48 8b 87 68 ff ff ff 48 8b 9f 28 ff ff ff <48> 8b 80 d0 00 00 00 4c 8b 63 28 48 8b 40 48 48 85 c0 0f 84 1a [ 11.530110] RIP [<ffffffffa0161fde>] intel_edp_psr_match_conditions+0x1e/0x2e0 [i915] [ 11.530163] RSP <ffff8803079c7d40> [ 11.530180] CR2: 00000000000000d0 Signed-off-by: Dave Airlie <[email protected]>
2014-07-19Merge tag 'drm-intel-next-2014-07-11' of ↵Dave Airlie23-1246/+2000
git://anongit.freedesktop.org/drm-intel into drm-next - fbc improvements when stolen memory is tight (Ben) - cdclk handling improvements for vlv/chv (Ville) - proper fix for stuck primary planes on gmch platforms with cxsr (Imre&Ebgert Eich) - gen8 hw semaphore support (Ben) - more execlist prep work from Oscar Mateo - locking fixes for primary planes (Matt Roper) - code rework to support runtime pm for dpms on hsw/bdw (Paulo, Imre & me), but not yet enabled because some fixes from Paulo haven't made the cut - more gpu boost tuning from Chris - as usual piles of little things all over * tag 'drm-intel-next-2014-07-11' of git://anongit.freedesktop.org/drm-intel: (93 commits) drm/i915: Make the RPS interrupt generation mask handle the vlv wa drm/i915: Move RPS evaluation interval counters to i915->rps drm/i915: Don't cast a pointer to void* unnecessarily drm/i915: don't read LVDS regs at compute_config time drm/i915: check the power domains in intel_lvds_get_hw_state() drm/i915: check the power domains in ironlake_get_pipe_config() drm/i915: don't skip shared DPLL assertion on LPT drm/i915: Only touch WRPLL hw state in enable/disable hooks drm/i915: Switch to common shared dpll framework for WRPLLs drm/i915: ->enable hook for WRPLLs drm/i915: ->disable hook for WRPLLs drm/i915: State readout support for WRPLLs drm/i915: add POWER_DOMAIN_PLLS drm/i915: Document that the pll->mode_set hook is optional drm/i915: Basic shared dpll support for WRPLLs drm/i915: Precompute static ddi_pll_sel values in encoders drm/i915: BDW also has special-purpose DP DDI clocks drm/i915: State readout and cross-checking for ddi_pll_sel drm/i915: Move ddi_pll_sel into the pipe config drm/i915: Add a debugfs file for the shared dpll state ...
2014-07-18drm/i915: use helpersRob Clark3-18/+12
Signed-off-by: Rob Clark <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2014-07-14Revert "drm/i915: reverse dp link param selection, prefer fast over wide again"Dave Airlie1-2/+2
This reverts commit 38aecea0ccbb909d635619cba22f1891e589b434. This breaks Haswell Thinkpad + Lenovo dock in SST mode with a HDMI monitor attached. Before this we can 1920x1200 mode, after this we only ever get 1024x768, and a lot of deferring. This didn't revert clean, but this should be fine. bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1117008 Cc: [email protected] # v3.15 Signed-off-by: Dave Airlie <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-14drm/i915: Track the primary plane correctly when reassigning planesDaniel Vetter1-0/+1
commit 98ec77397a5c68ce753dc283aaa6f4742328bcdd Author: Ville Syrjälä <[email protected]> Date: Wed Apr 30 17:43:01 2014 +0300 drm/i915: Make primary_enabled match the actual hardware state introduced more accurate tracking of the primary plane and some checks. It missed the plane->pipe reassignement code for gen2/3 though, which the checks caught and resulted in WARNING backtraces. Since we only use this path if the plane is on and on the wrong pipe we can just always set the tracking bit to "enabled". Reported-and-tested-by: Paul Bolle <[email protected]> Cc: Paul Bolle <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-14drm/i915: Ignore VBT backlight presence check on HP Chromebook 14Scot Doyle1-0/+3
commit c675949ec58ca50d5a3ae3c757892f1560f6e896 drm/i915: do not setup backlight if not available according to VBT caused a regression on the HP Chromebook 14 (with Celeron 2955U CPU), which has a misconfigured VBT. Apply quirk to ignore the VBT backlight presence check during backlight setup. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79813 Signed-off-by: Scot Doyle <[email protected]> Tested-by: Stefan Nagy <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Daniel Vetter <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-14Revert "drm/i915: Don't set the 8to6 dither flag when not scaling"Daniel Vetter2-4/+11
This reverts commit 773875bfb6737982903c42d1ee88cf60af80089c. It is very much needed and the lack of dithering has been reported by a large list of people with various gen2/3 hardware. Also, the original patch was complete non-sense since the WARNING backtraces in the references bugzilla are about gmch_pfit.lvds_border_bits mismatch, not at all about the dither bit. That one seems to work. Cc: Jiri Kosina <[email protected]> Cc: Pavel Machek <[email protected]> Cc: Hans de Bruin <[email protected]> Cc: [email protected] Acked-by: Pavel Machek <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-12drm/i915: byt_gpu_freq() can be staticFengguang Wu1-4/+4
CC: Deepak S <[email protected]> CC: Daniel Vetter <[email protected]> Signed-off-by: Fengguang Wu <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-12drm/i915/chv: calculate rc6 residency correctlyMika Kuoppala2-9/+32
The register to read cz count is different from vlv. Also the counts returned from CCK_CTL1 for BSW are (ticks in 30ns - 1). czcount_30ns of value 1 is a special case for 320Mhz. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80703 Suggested-by: Deepak S <[email protected]> Cc: Jesse Barnes <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Tested-by: Guo Jinxian <[email protected]> Reviewed-by: Deepak S <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-11drm/i915: Add RP1 render P state thresholds in CHVDeepak S1-0/+15
This is useful for userspace utilities to verify and micromanaging the increase/decrease frequncy. v2: Use vlv_gpu_freq to get freq (Deepak) Signed-off-by: Deepak S <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-11drm/i915/chv: Add basic PM interrupt support for CHVDeepak S2-1/+5
Enabled PM interrupt programming for CHV. Re-using gen8 code and extending same for CHV. Signed-off-by: Deepak S <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-11drm/i915: CHV GPU frequency to opcode functionsDeepak S1-2/+76
Adding chv specific fre/encode conversion. v2: Remove generic function and platform check (Daniel) Signed-off-by: Deepak S <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-11drm/i915: populate mem_freq/cz_clock for chvDeepak S3-0/+36
We need mem_freq or cz clock for freq/opcode conversion Signed-off-by: Deepak S <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-11drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfsDeepak S1-3/+15
This is useful for userspace utilities to verify and micromanaging the increase/decrease frequncy. Signed-off-by: Deepak S <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-11drm/i915: Read guaranteed freq for valleyviewDeepak S1-0/+16
Reading RP1 for valleyview to help us enable "pm_rps" i-g-t testcase execution. Signed-off-by: Deepak S <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> [danvet: Add missing static.] Signed-off-by: Daniel Vetter <[email protected]>
2014-07-11drm/i915: Call encoder->post_disable() in intel_sanitize_encoder()Ville Syrjälä1-0/+2
VLV and CHV disable the DP port only in the .post_disable() hook, so we need to make intel_sanitize_encoder() call that when it's trying to disable encoders without an active pipes. My bsw actaully hits this when an external display is connected. The BIOS still likes to turn on the eDP port, but leaves the pipe disabled. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Rafael Barbalho <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-11drm/i915: ddi: enable runtime pm during dpmsDaniel Vetter1-17/+8
Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> [danvet: Remove now bogus comment.] Signed-off-by: Daniel Vetter <[email protected]>
2014-07-11drm/i915: Use the cached min/min/rpe values in the vlv debugfs codeVille Syrjälä3-15/+14
No need to re-read the hardware rps fuses when we already have all the values tucked away in dev_priv->rps. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Deepak S <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-11drm/i915: Don't disable PPGTT for CHV based in PCI revVille Syrjälä1-1/+2
In commit 62942ed7279d3e06dc15ae3d47665eff3b373327 Author: Jesse Barnes <[email protected]> Date: Fri Jun 13 09:28:33 2014 -0700 drm/i915/vlv: disable PPGTT on early revs v3 we forgot about CHV. IS_VALLEYVIEW() is true for CHV, so we need to explicitly avoid disabling PPGTT on CHV. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Deepak S <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-10Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds10-24/+130
Pull drm fixes from Dave Airlie: "Nothing too scary, we have one outstanding i915 regression but Daniel has promised the fix as soon as he's finished testing it a bit. Fixes for the main x86 drivers: - radeon: dpm fixes, displayport regression fix - i915: quirks for backlight regression, edp reboot fix, valleyview black screen fixes - nouveau: display port regression fixes, fix for memory reclocking" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/radeon/dpm: Reenabling SS on Cayman drm/radeon: fix typo in ci_stop_dpm() drm/radeon: fix typo in golden register setup on evergreen drm/radeon: only print meaningful VM faults drm/radeon/dp: return -EIO for flags not zero case drm/i915/vlv: T12 eDP panel timing enforcement during reboot drm/i915: Only unbind vgacon, not other console drivers drm/i915: Don't clobber the GTT when it's within stolen memory drm/i915/vlv: Update the DSI ULPS entry/exit sequence drm/i915/vlv: DPI FIFO empty check is not needed drm/i915: Toshiba CB35 has a controllable backlight drm/i915: Acer C720 and C720P have controllable backlights drm/i915: quirk asserts controllable backlight presence, overriding VBT drm/nouveau/ram: fix test for gpio presence drm/nouveau/dp: workaround broken display drm/nouveau/dp: fix required link bandwidth calculations drm/nouveau/kms: restore fbcon after display has been resumed drm/nv50-/kms: pass a non-zero value for head to sor dpms methods drm/nouveau/fb: Prevent inlining of ramfuc_reg drm/gk104/ram: bash mpll bit 31 on
2014-07-10drm/i915: Make the RPS interrupt generation mask handle the vlv waChris Wilson1-5/+5
We can eliminate a lot of special case code by making the computation of the interrupt mask be correct for all callers. Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-10drm/i915: Move RPS evaluation interval counters to i915->rpsChris Wilson2-27/+23
Place the RPS counters inside the RPS struct. Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-10drm/i915: Don't cast a pointer to void* unnecessarilyDamien Lespiau1-1/+1
C is super happy to asign anything pointer to void *. Don't pretend otherwise. Signed-off-by: Damien Lespiau <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-10drm/i915: don't read LVDS regs at compute_config timePaulo Zanoni1-4/+9
We may reach this point while the machine is still runtime suspended, so we'll hit a WARN. The other encoders also don't touch registers at this point, so instead of waking the machine up, write some code to keep the register always at the same state, including after we runtime suspend/resume. Testcase: igt/pm_rpm Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80463 Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-10drm/i915: check the power domains in intel_lvds_get_hw_state()Paulo Zanoni1-0/+5
Just like we do for the other encoders. This should fix some WARNs when running pm_rpm on SNB. Testcase: igt/pm_rpm Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80463 Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-10drm/i915: check the power domains in ironlake_get_pipe_config()Paulo Zanoni1-0/+4
Just like we already do in haswell_get_pipe_config(). This should prevent some WARNs when we run pm_rpm on SNB. Testcase: igt/pm_rpm Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80463 Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-10drm/i915: don't skip shared DPLL assertion on LPTPaulo Zanoni1-5/+0
Since we now have support for shared DPLLS. Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-10drm/i915: Only touch WRPLL hw state in enable/disable hooksDaniel Vetter3-21/+8
To be able to do this we need to separately keep track of how many crtcs need a given WRPLL and how many actually actively use it. The common shared dpll framework already has all this, including massive state readout and cross checking. Which allows us to do this switch in a fairly small patch. Reviewed-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-10drm/i915: Switch to common shared dpll framework for WRPLLsDaniel Vetter5-144/+27
Mostly this patch is one big excersize in deleting code and asserts which are no longer needed. Note that we still abuse the shared dpll framework a bit since we call the enable/disable functions from the crtc mode_set and off hooks. But changing the actual hardware sequence will be done in the next step. Note that besides the massive amount of changes in this patch the places and order in which the low-level WRPLL code is called is absolutely unchanged. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Damien Lespiau <[email protected]> [imre: rebased on patchset version w/o pch/crt/fdi refactoring] Signed-off-by: Imre Deak <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-07-10drm/i915: ->enable hook for WRPLLsDaniel Vetter1-32/+19
This time around another cute hack to pre-fill the pll->hw_state with the right values. And also remove a bunch of checks which will be replaced by lots more checks in the common framework. Reviewed-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
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