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path: root/drivers/gpu/drm/i915
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2011-01-11drm/i915: detect & report PCH display error interruptsJesse Barnes2-2/+81
FDI and the transcoders can fail for various reasons, so detect those conditions and report on them. Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: cleanup rc6 codeJesse Barnes4-46/+75
Cleanup several aspects of the rc6 code: - misnamed intel_disable_clock_gating function (was only about rc6) - remove commented call to intel_disable_clock_gating - rc6 enabling code belongs in its own function (allows us to move the actual clock gating enable call back into restore_state) - allocate power & render contexts up front, only free on unload (avoids ugly lazy init at rc6 enable time) Signed-off-by: Jesse Barnes <[email protected]> [ickle: checkpatch cleanup] Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: fix rc6 enabling around suspend/resumeJesse Barnes2-3/+3
Enabling RC6 implies setting a graphics context. Make sure we do that only after the ring has been enabled, otherwise our ring commands will hang. Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: re-enable rc6 support for Ironlake+Jesse Barnes4-21/+91
Re-enable rc6 support on Ironlake for power savings. Adds a debugfs file to check current RC state, adds a missing workaround for Ironlake MI_SET_CONTEXT instructions, and renames MCHBAR_RENDER_STANDBY to RSTDBYCTL to match the docs. Keep RC6 and the power context disabled on pre-ILK. It only seems to hang and doesn't save any power. Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: Make the ring IMR handling privateChris Wilson2-12/+15
As the IMR for the USER interrupts are not modified elsewhere, we can separate the spinlock used for these from that of hpd and pipestats. Those two IMR are manipulated under an IRQ and so need heavier locking. Reported-and-tested-by: Alexey Fisher <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915/ringbuffer: Simplify the ring irq refcountingChris Wilson2-39/+25
... and move it under the spinlock to gain the appropriate memory barriers. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32752 Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915/debugfs: Show the per-ring IMRChris Wilson3-14/+24
Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: Mask USER interrupts on gen6 (until required)Chris Wilson5-62/+113
Otherwise we may consume 20% of the CPU just handling IRQs whilst rendering. Ouch. Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: Handle ringbuffer stalls when flushingChris Wilson4-43/+65
Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: Enforce write ordering through the GTTChris Wilson2-1/+16
We need to ensure that writes through the GTT land before any modification to the MMIO registers and so must impose a mandatory write barrier when flushing the GTT domain. This was revealed by relaxing the write ordering by experimentally mapping the registers and the GATT as write-combining. Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: Remove impossible testChris Wilson1-8/+0
As has_gem is unconditionally set to true, the conditional immediately following that assignment is superfluous. Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: avoid reading non-existent PLL reg on Ironlake+Jesse Barnes1-5/+7
These functions need to be reworked for Ironlake and above, but until then at least avoid reading non-existent registers. Signed-off-by: Jesse Barnes <[email protected]> [ickle: combine with a gratuitous tidy] Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: add 'reset' parameterChris Wilson1-0/+6
When bringing up new hardware, or otherwise experimenting, GPU hangs are a way of life. However, the automatic GPU reset can do more harm than good under these circumstances, as we may wish to capture a full trace for debugging. Based on a patch by Zhenyu Wang. Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: fix the wrong latency value while computing wm0Yuanhan Liu1-5/+5
On Ironlake, the LP0 latency is hardcoded and in ns unit, while on Sandybridge, it comes from a register and with unit 0.1 us. So, fix the wrong latency value while computing wm0 on Ironlake and Sandybridge. Signed-off-by: Yuanhan Liu <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: support low power watermarks on IronlakeJesse Barnes2-130/+133
This patch actually makes the watermark code even uglier (if that's possible), but has the advantage of sharing code between SNB and ILK at least. Longer term we should refactor the watermark stuff into its own file and clean it up now that we know how it's supposed to work. Supporting WM2 on my Vaio reduced power consumption by around 0.5W, so this patch is definitely worthwhile (though it also needs lots of test coverage). Signed-off-by: Jesse Barnes <[email protected]> [ickle: pass the watermark structs arounds] Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: Workaround erratum on i830 for TAIL pointer within last 2 cachelinesChris Wilson2-3/+11
On i830 if the tail pointer is set to within 2 cachelines of the end of the buffer, the chip may hang. So instead if the tail were to land in that location, we pad the end of the buffer with NOPs, and start again at the beginning. Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: Use the mappable sizes determined by GTT for consistency.Chris Wilson2-17/+10
There should be no difference, but we can eliminate redundant code. Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: support overclocking on Sandy BridgeJesse Barnes2-0/+28
In some configuration, the PCU may allow us to overclock the GPU. Check for this case and adjust the max frequency as appropriate. Also initialize the min/max frequencies to default values as indicated by hardware. Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915/lvds: Always use 0 to disable the pfit controllerChris Wilson1-0/+4
... and just any combination of bits & ~PFIT_ENABLE. This way we do not attempt disable to the panel fitter controller uselessly upon intel_lvds_disable(). Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915/panel: Only record the backlight level when it is enabledChris Wilson5-8/+39
By tracking the current status of the backlight we can prevent recording the value of the current backlight when we have disabled it. And so prevent restoring it to 'off' after an unbalanced sequence of intel_lvds_disable/enable. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=22672 Tested-by: Alex Riesen <[email protected]> Tested-by: Larry Finger <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: [email protected]
2011-01-11drm/i915/sdvo: Defer detection of output capabilities until probingChris Wilson1-22/+11
Alex Fiestas reported an issue with his HDMI connector being misdetected as DVI unless he had something connected upon boot. By moving the decision as to whether to use HDMI or DVI encoding for the HDMI capable output until we probe the monitor means that we should avoid sending a HDMI signal to a DVI monitor and also correctly detect hardware like Alex's. However, to really determine what connector is soldered onto the wire we need to inspect the VBT sdvo child devices - but can we trust it? Reported-by: Alex Fiestas <[email protected]> Tested-by: Alex Fiestas <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32828 Signed-off-by: Chris Wilson <[email protected]> Cc: [email protected]
2011-01-11drm/i915: fix calculation of eDP signal levels on SandybridgeYuanhan Liu2-11/+21
Some voltage swing/pre-emphasis level use the same value on eDP Sandybridge, like 400mv_0db and 600mv_0db are with the same value of (0x0 << 22). So, fix them, and point out the value if it isn't a supported voltage swing/pre-emphasis level. Signed-off-by: Yuanhan Liu <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: [email protected]
2011-01-11drm/i915/crt: Check for a analog monitor in case of DVI-IDavid Müller1-5/+25
Since Linux 2.6.36 the digital output on my system (855GME + DVI-I) is not working any longer. The analog output is always activated regardless of the type of monitor attached. The culprit seems to be intel_crt_detect_ddc(), which returns true as soon as an ACK from the EDID device is received. Obviously this approach does not work with DVI-I where the analog and digital outputs share a common DDC bus. In a similar manner to the shared DDC wire, ala the "Mac Mini Hack", we need an additional check to make sure that there really is an analog device attached to the DDC. Signed-off-by: David Müller <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: [email protected]
2011-01-11drm/i915: make DP training try a little harderJesse Barnes1-4/+23
When trying to do channel equalization, we need to make sure we still have clock recovery on all lanes while training. We also need to try clock recovery again if we lose the clock or if channel eq fails 5 times. We'll try clock recovery up to 5 more times before giving up entirely. Gets suspend/resume working on my Vaio again and brings us back into compliance with the DP training sequence spec. Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: check eDP encoder correctly when setting modesJesse Barnes1-1/+1
We were using a stale pointer in the check which caused us to use CPU attached DP params when we should have been using PCH attached params. Signed-off-by: Jesse Barnes <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31988 Tested-by: Jan-Hendrik Zab <[email protected]> Tested-by: Christoph Lukas <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: [email protected]
2011-01-07drm: Update fbdev fb_fix_screeninfoJames Simmons1-1/+0
If you change the color depth via fbset or some other framebuffer aware userland application struct fb_fix_screeninfo is not updated to this new information. This patch fixes this issue. Also the function is changed to just pass in struct drm_framebuffer so in the future we could use more fields. I'm hoping some day fix->smem* could be set here :-) Signed-off-by: James Simmons <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2011-01-05drm/switcheroo: track state of switch in drivers.Dave Airlie2-1/+15
We need to track the state of the switch in drivers, so that after s/r we don't resume the card we've explicitly switched off before. Also don't allow a userspace open to occur if we've switched the gpu off. Signed-off-by: Dave Airlie <[email protected]>
2011-01-05vga_switcheroo: add reprobe hook for fbcon to recheck connected outputs.Dave Airlie1-0/+1
This adds a hook after the mux is switched for the driver to reprobe the connected outputs. Signed-off-by: Dave Airlie <[email protected]>
2011-01-05Merge branch 'master' of /home/airlied/kernel/linux-2.6 into drm-core-nextDave Airlie5-3/+56
2010-12-30drm/i915/dvo: Report LVDS attached to ch701x as connectedChris Wilson1-1/+1
As we have already detected something attached to the chip during initialisation, always report the LVDS connector status as connected during probing. Signed-off-by: Chris Wilson <[email protected]>
2010-12-30Revert "drm/i915/bios: Reverse order of 100/120 Mhz SSC clocks"Chris Wilson1-1/+1
As I feared, whilst this fixed the clocks for the Lenovo U160, it broke many other machines. So lets reverts commit 448f53a1ede54eb854d036abf and search for the real bug. Reported-and-tested-by: Travis Hume <[email protected]> [et al] Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=25842 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32698 Signed-off-by: Chris Wilson <[email protected]>
2010-12-23drm/i915: Verify Ironlake eDP presence on DP_A using the capability fuseChris Wilson2-1/+25
Signed-off-by: Chris Wilson <[email protected]>
2010-12-23drm/i915, intel_ips: When i915 loads after IPS, make IPS relink to i915.Eric Anholt1-0/+23
The IPS driver is designed to be able to run detached from i915 and just not enable GPU turbo in that case, in order to avoid module dependencies between the two drivers. This means that we don't know what the load order between the two is going to be, and we had previously only supported IPS after (optionally) i915, but not i915 after IPS. If the wrong order was chosen, you'd get no GPU turbo, and something like half the possible graphics performance. Signed-off-by: Eric Anholt <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: [email protected]
2010-12-23drm/i915/sdvo: Add hdmi connector properties after initing the connectorChris Wilson1-1/+2
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=25012 Reported-by: Tõnu Raitviir <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-12-23drm/i915: Set the required VFMUNIT clock gating disable on Ironlake.Eric Anholt2-0/+5
It's required by the specs, but we don't know why. Let's not find out why. Signed-off-by: Eric Anholt <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-12-22Merge remote branch 'intel/drm-intel-next' of /ssd/git/drm-next into ↵Dave Airlie29-4778/+6727
drm-core-next * 'intel/drm-intel-next' of /ssd/git/drm-next: (771 commits) drm/i915: Undo "Uncouple render/power ctx before suspending" drm/i915: Allow the application to choose the constant addressing mode drm/i915: dynamic render p-state support for Sandy Bridge drm/i915: Enable EI mode for RCx decision making on Sandybridge drm/i915/sdvo: Border and stall select became test bits in gen5 drm/i915: Add Guess-o-matic for pageflip timestamping. drm/i915: Add support for precise vblank timestamping (v2) drm/i915: Add frame buffer compression on Sandybridge drm/i915: Add self-refresh support on Sandybridge drm/i915: Wait for vblank before unpinning old fb Revert "drm/i915: Avoid using PIPE_CONTROL on Ironlake" drm/i915: Pass clock limits down to PLL matcher drm/i915: Poll for seqno completion if IRQ is disabled drm/i915/ringbuffer: Make IRQ refcnting atomic agp/intel: Fix missed cached memory flags setting in i965_write_entry() drm/i915/sdvo: Only use the SDVO pin if it is in the valid range drm/i915: Enable RC6 autodownclocking on Sandybridge drm/i915: Terminate the FORCE WAKE after we have finished reading drm/i915/gtt: Clear the cachelines upon resume drm/i915: Restore GTT mapping first upon resume ...
2010-12-21drm/fb: Don't expose mmio for fbdev emulation layerJames Simmons1-5/+1
For the fbdev api if the struct fb_var_screeninfo accel_flags field is set to FB_ACCELF_TEXT then userland applications can not mmap the mmio region. Since it is a bad idea for DRM drivers to expose the mmio region via the fbdev layer we always set the accel_flags to prevent this. Please apply. Signed-off-by: James Simmons <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2010-12-20drm/i915: Undo "Uncouple render/power ctx before suspending"Chris Wilson1-0/+2
Manaul revert of 0cdab21f9a1fca50dd27e488839f5a6578e333b2, just to remove the call to disable the clock gatings and powerctx before suspend. Peter Clifton bisected a suspend failure on his gme45 and found this to be the culprit. As this was intended to be a fix for a similar suspend failure for Ironlake (it didn't work), undoing this patch should have no other side-effects. Reported-and-tested-by: Peter Clifton <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-12-20drm/i915: Allow the application to choose the constant addressing modeChris Wilson4-1/+40
The relative-to-general state default is useless as it means having to rewrite the streaming kernels for each batch. Relative-to-surface is more useful, as that stream usually needs to be rewritten for each batch. And absolute addressing mode, vital if you start streaming state, is also only available by adjusting the register... Signed-off-by: Chris Wilson <[email protected]>
2010-12-18drm/i915: dynamic render p-state support for Sandy BridgeJesse Barnes7-20/+137
Add an interrupt handler for switching graphics frequencies and handling PM interrupts. This should allow for increased performance when busy and lower power consumption when idle. Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-12-17drm/i915: Enable EI mode for RCx decision making on SandybridgeChris Wilson1-0/+1
And no I have no idea what the difference is either, just that is the recommendation. Signed-off-by: Chris Wilson <[email protected]>
2010-12-16drm/i915/sdvo: Border and stall select became test bits in gen5Chris Wilson1-2/+5
This is even more important as those bits will be moved in future. Signed-off-by: Chris Wilson <[email protected]>
2010-12-16drm/i915: Add Guess-o-matic for pageflip timestamping.Mario Kleiner1-14/+20
This patch changes the strategy for pageflip completion timestamping. It detects if the pageflip completion routine gets executed before or after drm_handle_vblank, and thereby decides if the returned vblank count and timestamp must be incremented by 1 frame(duration) or not. It compares the current system time at invocation against the current vblank timestamp. If the difference is more than 0.9 video refresh interval durations then it assumes the vblank timestamp and count are outdated and need to be incremented and does so. Otherwise it assumes a delayed pageflip irq and doesn't correct the timestamp and count. Advantage of this patch: Pageflip timestamping becomes more robust against implementation errors and is maintenance free for future GPU's. Disadvantage: A few dozen (hundred?) nsecs extra time spent in pageflip irq handler for each flip, compared to hard-coded per-gpu settings? Signed-off-by: Mario Kleiner <[email protected]> Acked-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-12-16drm/i915: Add support for precise vblank timestamping (v2)Mario Kleiner5-6/+119
v2: Change IS_IRONLAKE to IS_GEN5 to adapt to 2.6.37 This patch adds new functions for use by the drm core: .get_vblank_timestamp() provides a precise timestamp for the end of the most recent (or current) vblank interval of a given crtc, as needed for the DRI2 implementation of the OML_sync_control extension. It is a thin wrapper around the drm function drm_calc_vbltimestamp_from_scanoutpos() which does almost all the work. .get_scanout_position() provides the current horizontal and vertical video scanout position and "in vblank" status of a given crtc, as needed by the drm for use by drm_calc_vbltimestamp_from_scanoutpos(). The patch modifies the pageflip completion routine to use these precise vblank timestamps as the timestamps for pageflip completion events. This code has been only tested on a HP-Mini Netbook with Atom processor and Intel 945GME gpu. The codepath for (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) gpu's has not been tested so far due to lack of hardware. Signed-off-by: Mario Kleiner <[email protected]> Acked-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-12-15drm/i915: Add frame buffer compression on SandybridgeYuanhan Liu4-3/+20
Add frame buffer compression on Sandybridge. The method is similar to Ironlake, except that two new registers of type GTTMMADR must be written with the right fence info. Signed-off-by: Yuanhan Liu <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-12-15drm/i915: Add self-refresh support on SandybridgeYuanhan Liu3-18/+334
Add the support of memory self-refresh on Sandybridge, which is now support 3 levels of watermarks and the source of the latency values for watermarks has changed. On Sandybridge, the LP0 WM value is not hardcoded any more. All the latency value is now should be extracted from MCHBAR SSKPD register. And the MCHBAR base address is changed, too. For the WM values, if any calculated watermark values is larger than the maximum value that can be programmed into the associated watermark register, that watermark must be disabled. Signed-off-by: Yuanhan Liu <[email protected]> [ickle: remove duplicate compute routines and fixup for checkpatch] Signed-off-by: Chris Wilson <[email protected]>
2010-12-15drm/i915: Wait for vblank before unpinning old fbChris Wilson1-1/+3
Be paranoid and ensure that the vblank has passed and the scanout has switched to the new fb, before unpinning the old one and possibly tearing down its PTEs. Signed-off-by: Chris Wilson <[email protected]>
2010-12-15Revert "drm/i915: Avoid using PIPE_CONTROL on Ironlake"Chris Wilson2-3/+162
Restore PIPE_CONTROL once again just for Ironlake, as it appears that MI_USER_INTERRUPT does not have the same coherency guarantees, that is on Ironlake the interrupt following a GPU write is not guaranteed to arrive after the write is coherent from the CPU, as it does on the other generations. Reported-by: Zhenyu Wang <[email protected]> Reported-by: Shuang He <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32402 Signed-off-by: Chris Wilson <[email protected]>
2010-12-14drm/i915/bios: Reverse order of 100/120 Mhz SSC clocksChris Wilson1-1/+1
Fixes the lack of output on the LVDS panel of the Lenovo U160. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31596 Reported-and-tested-by: Dirk Gouders <[email protected]> Cc: [email protected] Signed-off-by: Chris Wilson <[email protected]>
2010-12-14drm/i915: Pass clock limits down to PLL matcherChris Wilson1-18/+16
As we already know the limits for the hardware clock, pass it down rather than recomputing them for each match. Signed-off-by: Chris Wilson <[email protected]>
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