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path: root/drivers/gpu/drm/i915
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2011-01-24drm/i915,agp/intel: Do not clear stolen entriesChris Wilson3-4/+15
We can only utilize the stolen portion of the GTT if we are in sole charge of the hardware. This is only true if using GEM and KMS, otherwise VESA continues to access stolen memory. Reported-by: Arnd Bergmann <[email protected]> Reported-by: Frederic Weisbecker <[email protected]> Tested-by: Jiri Olsa <[email protected]> Tested-by: Frederic Weisbecker <[email protected]> Cc: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-23drm/i915: Recognise non-VGA display devicesChris Wilson2-3/+9
Starting with SandyBridge (though possible with earlier hacked BIOSes), the BIOS may initialise the IGFX as secondary to a discrete GPU. Prior, it would simply disable the integrated GPU. So we adjust our PCI class mask to match any DISPLAY_CLASS device. In such a configuration, the IGFX is not a primary VGA controller and so should not take part in VGA arbitration, and the error return from vga_client_register() is expected. Signed-off-by: Chris Wilson <[email protected]> Cc: [email protected]
2011-01-23drm/i915: Fix use of invalid array size for ring->sync_seqnoChris Wilson2-2/+2
There are I915_NUM_RINGS-1 inter-ring synchronisation counters, but we were clearing I915_NUM_RINGS of them. Oops. Reported-by: Jiri Slaby <[email protected]> Tested-by: Jiri Slaby <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-23drm/i915: Remove unused code: i915_enable_interrupt()Chris Wilson2-13/+0
Signed-off-by: Chris Wilson <[email protected]>
2011-01-20drm/i915/ringbuffer: Fix use of stale HEAD position whilst polling for spaceChris Wilson2-17/+24
During suspend, Linus found that his machine would hang for 3 seconds, and identified that intel_ring_buffer_wait() was the culprit: "Because from looking at the code, I get the notion that "intel_read_status_page()" may not be exact. But what happens if that inexact value matches our cached ring->actual_head, so we never even try to read the exact case? Does it _stay_ inexact for arbitrarily long times? If so, we might wait for the ring to empty forever (well, until the timeout - the behavior I see), even though the ring really _is_ empty." As the reported HEAD position is only updated every time it crosses a 64k boundary, whilst draining the ring it is indeed likely to remain one value. If that value matches the last known HEAD position, we never read the true value from the register and so trigger a timeout. Reported-by: Linus Torvalds <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-20drm/i915/ringbuffer: Kill an annoyingly frequent debug messageChris Wilson1-1/+0
This is better handled through the tracepoints and just clutters the debug logs. Signed-off-by: Chris Wilson <[email protected]>
2011-01-20drm/i915: Don't kick-off hangcheck after a DRI interruptChris Wilson1-1/+5
Hangcheck and error recovery is only used by GEM. Reported-by: Herbert Xu <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-20drm/i915: Initialise ring vfuncs for old DRI pathsChris Wilson3-18/+52
We weren't setting up the vfunc table when initialising the old DRI ringbuffer, leading to such OOPSes as: BUG: unable to handle kernel NULL pointer dereference at (null) IP: [<(null)>] (null) PGD 10c441067 PUD 1185e5067 PMD 0 Oops: 0010 [#1] PREEMPT SMP last sysfs file: /sys/class/dmi/id/chassis_asset_tag CPU 3 Modules linked in: i915 drm_kms_helper drm fb fbdev i2c_algo_bit cfbcopyarea video backlight output cfbimgblt cfbfillrect autofs4 ipv6 nfs lockd fscache nfs_acl auth_rpcgss sunrpc coretemp hwmon_vid mousedev usbhid hid option usb_wwan snd_hda_codec_via asus_atk0110 atl1e usbserial snd_hda_intel snd_hda_codec firmware_class snd_hwdep snd_pcm snd_seq snd_timer snd_seq_device processor parport_pc thermal snd thermal_sys parport 8250_pnp button rng_core rtc_cmos shpchp hwmon rtc_core ehci_hcd pci_hotplug uhci_hcd soundcore tpm_tis i2c_i801 rtc_lib tpm serio_raw snd_page_alloc tpm_bios i2c_core usbcore psmouse intel_agp sg pcspkr sr_mod evdev cdrom ext3 jbd mbcache dm_mod sd_mod ata_piix libata scsi_mod unix Jan 18 15:49:29 lithui kernel: Pid: 3605, comm: Xorg Not tainted 2.6.36.2 #5 P5KPL-CM/System Product Name RIP: 0010:[<0000000000000000>] [<(null)>] (null) RSP: 0018:ffff8801150d1d40 EFLAGS: 00010202 RAX: 000000000001ffff RBX: ffff88011a011b00 RCX: 000000000001a704 RDX: ffff880118566028 RSI: ffff880118566028 RDI: ffff880117876800 RBP: ffff8801150d1d48 R08: ffff8801195fe300 R09: 00000000c0086444 R10: 0000000000000001 R11: 0000000000003206 R12: ffff880117876800 R13: ffff880118566000 R14: ffff880117876820 R15: ffff8801150d1df8 FS: 00007f1038d456e0(0000) GS:ffff880001780000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000000 CR3: 00000001187e7000 CR4: 00000000000006e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400 Process Xorg (pid: 3605, threadinfo ffff8801150d0000, task ffff88011b016e40) Stack: ffffffffa043b8e6 ffff8801150d1d98 ffffffffa041768b dead000000000000 <0> 0000000000000048 00007f1023f2a000 0000000000000044 0000000000000008 <0> ffff88010d26bd80 ffff880117876800 ffff8801150d1df8 ffff8801150d1ea8 Call Trace: [<ffffffffa043b8e6>] ? intel_ring_advance+0x16/0x20 [i915] [<ffffffffa041768b>] i915_irq_emit+0x15b/0x240 [i915] [<ffffffffa03ea7b1>] drm_ioctl+0x1f1/0x460 [drm] [<ffffffffa0417530>] ? i915_irq_emit+0x0/0x240 [i915] [<ffffffff810dd8f1>] ? do_sync_read+0xd1/0x120 [<ffffffff81025b1f>] ? do_page_fault+0x1df/0x3d0 [<ffffffff810ed5c7>] do_vfs_ioctl+0x97/0x550 [<ffffffff8115c2ea>] ? security_file_permission+0x7a/0x90 [<ffffffff810edb19>] sys_ioctl+0x99/0xa0 [<ffffffff810024ab>] system_call_fastpath+0x16/0x1b Code: Bad RIP value. RIP [<(null)>] (null) RSP <ffff8801150d1d40> CR2: 0000000000000000 Reported-by: Herbert Xu <[email protected]> Tested-by: Herbert Xu <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29153 Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=23172 Signed-off-by: Chris Wilson <[email protected]> Cc: [email protected]
2011-01-20Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2-1/+30
Apply the SandyBridge stability fixes from -fixes.
2011-01-19drm/i915: Include TLB miss latency in g4x watermark computationsChris Wilson2-65/+160
Reports of FIFO underruns are still persisting on gm45. References: https://bugs.freedesktop.org/show_bug.cgi?id=27589 Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: Disable SSC for outputs other than LVDS or DPChris Wilson4-26/+36
For CRT and SDVO/HDMI, we need to use a normal, non-SSC, clock and so we must clear any enabling bits left-over from earlier outputs. And also seems to correct the LVDS panel on the Lenovo U160. However, at one point, it did cause an "ERROR failed to disable trancoder". So prolonged testing on top of Jesse's refactored and error-checking CRTC logic is desired. Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915/bios: Change default clock source on PineView to use SSCBryan Freed1-8/+23
The i915 driver normally assumes the video bios has configured several of the LVDS panel registers, and it just inherits the values. If the vbios has not run, several of these will need to be setup. If these are not correct then although the panel looks ok, output from an HDMI encoder (eg, Chrontel CH7036) will be incorrect. Signed-off-by: Mark Hayter <[email protected]> [ickle: minor adjustments] Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: Honour LVDS sync polarity from EDIDBryan Freed2-0/+21
The i915 driver normally assumes the video bios has configured several of the LVDS panel registers, and it just inherits the values. If the vbios has not run, several of these will need to be setup. So we need to check that the LVDS sync polarity is correctly configured per any available modelines (e.g. EDID) and adjust if not, issuing a warning as we do. Signed-off-by: Mark Hayter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: tune Sandy Bridge DRPS constantsJesse Barnes3-8/+46
These make us increase our frequency much more readily, and decrease them only after significant idle time, resulting in a 20% performance increase for nexuiz. Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: Trivial sparse fixesChris Wilson8-36/+35
Move code around and invoke iomem annotation in a few more places in order to silence sparse. Still a few more iomem annotations to go... Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: allow 945 to control self refresh (CxSR) automaticallyAlexander Lam1-38/+24
I changed 945's self refresh to work without the need for the driver to enable/disable self refresh manually based on the idle state of the gpu. This is much better than enabling/disabling self refresh for various reasons, including staying in a lower power state for more time and avoiding the need for cpu cycles. This was originally done manually to workaround issues with the hardware hanging. However, since 944001201: drm/i915: enable low power render writes on GEN3 hardware, automatic CxSR seems stable. Signed-off-by: Alexander Lam <[email protected]> Acked-by : Li Peng <[email protected]> [ickle: play safe with the ordering and disable CxSR before tweaking any watermark and enable afterwards.] Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: Use PM QoS to prevent C-State starvation of gen3 GPUChris Wilson2-0/+38
945 class hardware has an interesting quirk in which the vblank interrupt is not raised if the CPU is in a low power state. (We also suspect that the memory bus is clocked to the CPU/c-state and not the GPU so there are secondary starvation issues.) In order to prevent the most obvious issue of the low of the vblank interrupt (stuttering compositing that only updates when the mouse is moving) is to install a PM QoS request to prevent low c-states whilst the GPU is active. Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: skip FDI & PCH enabling for DP_AJesse Barnes1-37/+60
eDP on the CPU doesn't need the PCH set up at all, it can in fact cause problems. So avoid FDI training and PCH PLL enabling in that case. Signed-off-by: Jesse Barnes <[email protected]> Tested-by: Yuanhan Liu <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: set phase sync pointer override enable before setting phase sync ↵Jesse Barnes2-4/+11
pointer We need to unlock the phase sync pointer enable bit before we can actually enable the phase sync pointer workaround on Ironlake. Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: factor out FDI disable and add FDI assertionsJesse Barnes1-44/+60
Factor out the FDI disable function (make it a mirror of ironlake_fdi_enable) and add some FDI related assertions to the FDI training code (we need an active pipe & plane before we start transmitting bits). Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: add transcoder enable/disable functionsJesse Barnes1-25/+170
Along with assertion checks for the FDI transmitters and receivers (including PLLs). Modify the pipe enable function to check for FDI PLL status as well, when driving PCH ports. Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: assert panel is unlocked before writing transcoder timing regsJesse Barnes1-1/+2
Otherwise our writes will be silently ignored. Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: add PCH DPLL enable/disable functionsJesse Barnes2-11/+75
With assertions to check transcoder and reference clock state. Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: add PLL enable/disable functionsJesse Barnes1-46/+78
For pre-ILK only. Saves some code in the CRTC enable/disable functions and allows us to check for pipe and panel status at enable/disable time. Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: add panel lock assertion functionJesse Barnes1-0/+29
When PLLs or timing regs are changed, we need to make sure the panel lock will allow it. Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: add pipe/plane enable/disable functionsJesse Barnes2-97/+216
Add plane enable/disable functions to prevent duplicated code and allow us to easily check for plane enable/disable requirements (such as pipe enable, plane status, pll status etc). Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: don't enable plane, pipe and PLL prematurelyJesse Barnes1-3/+5
On Ironlake+ we need to enable these in a specific order. Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-19drm/i915: Use ACPI OpRegion to determine lid statusChris Wilson3-0/+10
Admittedly, trusting ACPI or the BIOS at all to be correct is littered with numerous examples where it is wrong. Maybe, just maybe, we will have better luck using the ACPI OpRegion lid status... Signed-off-by: Chris Wilson <[email protected]>
2011-01-18drm/i915: make the blitter report buffer modifications to the FBC unitJesse Barnes2-0/+25
Without this change, blits to the front buffer won't invalidate FBC state, causing us to scan out stale data. Make sure we update these bits on every FBC enable, since they may get clobbered if we shut off the display. References: https://bugzilla.kernel.org/show_bug.cgi?id=26932 Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-18drm/i915: set more FBC chicken bitsJesse Barnes2-1/+5
Add a couple of missing workaround bits for ILK & SNB. These disable clock gating on a couple of units that would otherwise prevent FBC from working. Signed-off-by: Jesse Barnes <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-14Revert "drm: Update fbdev fb_fix_screeninfo"Dave Airlie1-0/+1
This reverts commit dfe63bb0ad9810db13aab0058caba97866e0a681. This commit was causing nouveau not to work properly, for -rc1 I'd prefer it worked and we can look if this is useful for 2.6.39. Cc: James Simmons <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2011-01-14drm/i915/lvds: Add AOpen i915GMm-HFS to the list of false-positive LVDSKnut Petersen1-0/+8
Signed-off-by: Knut Petersen <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: [email protected]
2011-01-14drm/i915: Disable GPU semaphores on SandyBridge mobileChris Wilson1-1/+2
Hopefully, this is a temporary measure whilst the root cause is understood. At the moment, we experience a hard hang whilst looping urbanterror that has been identified as a result of the use of semaphores, but so far only on SNB mobile. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32752 Tested-by: [email protected] Signed-off-by: Chris Wilson <[email protected]>
2011-01-13drm/i915/execbuffer: Clear domains before beginning reloc processingChris Wilson1-4/+3
After reordering the sequence of relocating objects, commit 6fe4f1404, we can no longer rely on seeing all reloc targets prior to performing the relocation. As a result we were ignoring the need to flush objects from the render cache and invalidate the sampler caches, resulting in rendering glitches. So we need to clear the relocation domains earlier. Reported-by: Linus Torvalds <[email protected]> Tested-by: Linus Torvalds <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-13drm/i915/execbuffer: Reorder relocations to match new object orderChris Wilson1-6/+9
On the fault path, commit 6fe4f140 introduction a regression whereby it changed the sequence of the objects but continued to use the original ordering of relocation entries. The result was that incorrect GTT offsets were being fed into the execbuffer causing lots of misrendering and potential hangs. Reported-by: Linus Torvalds <[email protected]> Tested-by: Linus Torvalds <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-13drm/i915: Fix error handler to capture the first batch after the seqnoChris Wilson1-1/+1
Whilst we had no older batches on the active list, everything was fine. However, if the GPU is free running and the requests are only being reaped by the periodic retirer, than the current seqno may not be at the start of the list. In this case we need to select the first batch after the last seqno written by the gpu and not inclusive of the seqno. Signed-off-by: Chris Wilson <[email protected]>
2011-01-13drm/i915: Add a module option to override the use of SSCChris Wilson4-17/+21
In order to workaround the issue with LVDS not working on the Lenovo U160 apparently due to using the wrong SSC frequency, add an option to disable SSC. Suggested-by: Lukács, Árpád <[email protected]> Bugzillla: https://bugs.freedesktop.org/show_bug.cgi?id=32748 Signed-off-by: Chris Wilson <[email protected]> Cc: [email protected]
2011-01-12drm/i915/panel: The backlight is enabled if the current value is non-zeroIndan Zupancic1-1/+1
... and not if the maximum is non-zero. This fixes the typo introduced in 47356eb6728501452 and preserves the backlight value from boot. [ickle: My thanks also to Indan Zupancic for diagnosing the original regression and suggesting the appropriate fix.] Signed-off-by: Chris Wilson <[email protected]> Cc: [email protected] # after 47356eb6728501452
2011-01-12drm/i915/debugfs: Correct format after changing type of err object 'size'Chris Wilson1-1/+1
Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915/execbuffer: Reorder binding of objects to favour restrictionsChris Wilson2-26/+47
As the mappable portion of the aperture is always a small subset at the start of the GTT, it is allocated preferentially by drm_mm. This is useful in case we ever need to map an object later. However, if you have a large object that can consume the entire mappable region of the GTT this prevents the batchbuffer from fitting and so causing an error. Instead allocate all those that require a mapping up front in order to improve the likelihood of finding sufficient space to bind them. Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: If we hit OOM when allocating GTT pages, clear the apertureChris Wilson1-8/+4
Rather than evicting an object at random, which is unlikely to alleviate the memory pressure sufficient to allow us to continue, zap the entire aperture. That should give the system long enough to recover and reap some pages from the evicted objects, forestalling the allocation error for the new object. Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915/evict: Ensure we completely cleanup on failureChris Wilson1-1/+8
... and not leave the objects in a inconsistent state. Signed-off-by: Chris Wilson <[email protected]> Cc: [email protected]
2011-01-11drm/i915/execbuffer: Correctly clear the current object list upon EFAULTChris Wilson1-3/+1
Before releasing the lock in order to copy the relocation list from user pages, we need to drop all the object references as another thread may usurp and execute another batchbuffer before we reacquire the lock. However, the code was buggy and failed to clear the list... Signed-off-by: Chris Wilson <[email protected]> Cc: [email protected]
2011-01-11drm/i915/debugfs: Show all objects in the gttChris Wilson1-10/+43
Useful for determining the layout. Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: Record AGP memory type upon errorChris Wilson3-4/+16
Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: Periodically flush the active lists and requestsChris Wilson1-4/+26
In order to retire active buffers whilst no client is active, we need to insert our own flush requests onto the ring. This is useful for servers that queue up some rendering and then go to sleep as it allows us to the complete processing of those requests, potentially making that memory available again much earlier. Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915/gtt: Unmap the PCI pages after unbinding them from the GTTChris Wilson1-7/+3
Dave Airlie spotted that his ILK laptop with DMAR enabled was generating the occasional DMAR warning. "The ordering in the previous code was to rewrite the GTT table before unmapping the pages and that makes sense to me." This is his stable patch ported to d-i-n. Reported-by: Dave Airlie <[email protected]> Original-patch-by: Dave Airlie <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: Record the error batchbuffer on each ringChris Wilson3-120/+50
Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: Include TLB miss overhead for computing WMChris Wilson1-2/+9
The docs recommend that if 8 display lines fit inside the FIFO buffer, then the number of watermark entries should be increased to hide the latency of filling the rest of the FIFO buffer. Signed-off-by: Chris Wilson <[email protected]>
2011-01-11drm/i915: Propagate error from flushing the ringChris Wilson3-48/+90
... in order to avoid a BUG() and potential unbounded waits. Signed-off-by: Chris Wilson <[email protected]>
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