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path: root/drivers/gpu/drm/i915/intel_runtime_pm.c
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2015-12-17drm/i915: clarify comment about mandatory RPM put/get during driver load/unloadImre Deak1-2/+13
2015-12-11Merge tag 'drm-i915-get-eld' of tiwai/sound into drm-intel-next-queuedDaniel Vetter1-2/+2
2015-12-01drm/i915/bxt: Disable power well supportMatt Roper1-0/+5
2015-12-01Merge tag 'drm-intel-next-2015-11-20-merged' of git://anongit.freedesktop.org...Dave Airlie1-229/+277
2015-11-25drm/i915: fix potential dangling else problems in for_each_ macrosJani Nikula1-2/+2
2015-11-23drm/i915/pm: Print offending domain in refcount failureDaniel Stone1-2/+6
2015-11-23drm/i915/pm: Unstatic power_domain_strDaniel Stone1-0/+66
2015-11-23drm/i915/skl: re-enable power well supportImre Deak1-5/+0
2015-11-23Merge tag 'v4.4-rc2' into drm-intel-next-queuedDaniel Vetter1-0/+18
2015-11-17drm/i915/gen9: Add boot parameter for disabling DC6Patrik Jakobsson1-3/+11
2015-11-17drm/i915/gen9: Turn DC handling into a power wellPatrik Jakobsson1-29/+83
2015-11-17drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5()Patrik Jakobsson1-3/+0
2015-11-17drm/i915: Remove distinction between DDI 2 vs 4 lanesPatrik Jakobsson1-46/+25
2015-11-17drm/i915: Remove DDI power domain exclusion SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINSVille Syrjälä1-5/+1
2015-11-17drm/i915: Introduce a gmbus power domainVille Syrjälä1-30/+4
2015-11-17drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6Patrik Jakobsson1-18/+17
2015-11-17drm/i915: fix handling of the disable_power_well module optionImre Deak1-1/+15
2015-11-17drm/i915/skl: remove redundant DDI/IRQ reinitialization during PW1 enablingImre Deak1-5/+0
2015-11-17drm/i915/skl: disable DC states before display core init/uninitImre Deak1-0/+4
2015-11-17drm/i915/gen9: simplify DC toggling codeImre Deak1-36/+27
2015-11-17drm/i915/skl: don't toggle PW1 and MISC power wells on-demandImre Deak1-27/+9
2015-11-17drm/i915/skl: init/uninit display core as part of the HW power domain stateImre Deak1-2/+54
2015-11-17drm/i915: rename intel_power_domains_resume to *_sync_hwImre Deak1-2/+2
2015-11-17drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequencesDamien Lespiau1-0/+28
2015-11-17drm/i915: fix lookup_power_well for power wells without any domainImre Deak1-2/+4
2015-11-17drm/i915: fix the power well ID for always on wellsImre Deak1-0/+2
2015-11-12drm/i915/skl: Removed assert for csr-fw-loading check during disabling dc6Animesh Manna1-1/+0
2015-11-12drm/i915/gen9: Remove csr.state, csr_lock and related code.Daniel Vetter1-15/+2
2015-11-12drm/i915/gen9: move assert_csr_loaded into intel_rpm.cDaniel Vetter1-0/+8
2015-11-11drm/i915: Kill intel_runtime_pm_disable()Ville Syrjälä1-17/+0
2015-11-07Merge tag 'drm-intel-next-fixes-2015-11-06' of git://anongit.freedesktop.org/...Dave Airlie1-0/+18
2015-11-06drm/i915/skl: disable display side power well support for nowImre Deak1-0/+18
2015-10-28drm/i915/kbl: Introduce Kabylake platform defition.Rodrigo Vivi1-1/+1
2015-10-20Merge tag 'drm-intel-next-2015-10-10' of git://anongit.freedesktop.org/drm-in...Dave Airlie1-7/+54
2015-10-19drm/i915/skl: Making DC6 entry is the last call in suspend flow.Animesh Manna1-12/+7
2015-10-16Merge commit '06d1ee32a4d25356a710b49d5e95dbdd68bdf505' of git://git.kernel.o...Dave Airlie1-1/+2
2015-10-06drm/i915: Skip CHV PHY asserts until PHY has been fully resetVille Syrjälä1-1/+45
2015-09-30drm/i915: fixup runtime PM handling v2Jesse Barnes1-3/+0
2015-09-30drm/i915/skl: Block disable call for pw1 if dmc firmware is present.Animesh Manna1-3/+9
2015-09-28drm/i915/skl: Don't call intel_prepare_ddi when encoder list isn't yet initia...Rodrigo Vivi1-1/+2
2015-09-14drm/i915: make CSR firmware messages less verboseJesse Barnes1-18/+18
2015-09-02Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter1-0/+2
2015-09-01drm/i915: Add CHV PHY LDO power sanity checksVille Syrjälä1-17/+109
2015-09-01drm/i915: Add some CHV DPIO lane power state assertsVille Syrjälä1-0/+54
2015-08-31drm/i915/skl: Adding DDI_E power well domainXiong Zhang1-0/+2
2015-08-26drm/i915: Force CL2 off in CHV x1 PHYVille Syrjälä1-0/+9
2015-08-26drm/i915: Enable DPIO SUS clock gating on CHVVille Syrjälä1-1/+2
2015-08-26drm/i915: Trick CL2 into life on CHV when using pipe B with port BVille Syrjälä1-0/+29
2015-08-26drm/i915: Implement PHY lane power gating for CHVVille Syrjälä1-9/+114
2015-08-26drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enableVille Syrjälä1-21/+24
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