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2024-07-01drm/i915: Skip programming FIA link enable bits for MTL+Gustavo Sousa1-0/+3
Starting with Xe_LPD+, although FIA is still used to readout Type-C pin assignment, part of Type-C support is moved to PICA and programming PORT_TX_DFLEXDPMLE1(*) registers is not applicable anymore like it was for previous display IPs (e.g. see BSpec 49190). v2: - Mention Bspec 49190 as a reference of instructions for previous IPs. (Shekhar Chauhan) - s/Xe_LPDP/Xe_LPD+/ in the commit message. (Matt Roper) - Update commit message to be more accurate to the changes in the IP. (Imre Deak) Bspec: 65750, 65448 Reviewed-by: Shekhar Chauhan <[email protected]> Reviewed-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Gustavo Sousa <[email protected]>
2024-06-28drm/i915/mtl: Skip PLL state verification in TBT modeImre Deak3-8/+12
In TBT-alt mode the driver doesn't program the PHY's PLL, which is handled instead by Thunderbolt driver/FW components, hence the PLL's HW vs. SW state verification should be skipped. During HW readout set a flag in the PLL state if the port was at the moment in TBT-alt mode and skip the verification of PLL parameters in this case. Fixes: 45fe957ae769 ("drm/i915/display: Add compare config for MTL+ platforms") Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11258 Cc: Mika Kahola <[email protected]> Reviewed-by: Mika Kahola <[email protected]> Signed-off-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-27drm/i915/dsb: Try to document that DSB_STATUS bit 16 is level triggeredVille Syrjälä1-1/+1
DSB_STATUS bit 16 is supposed to be a sticky bit informing us whether the DSB was idle or not when the pipe's delayed vblank (when double buffered registers latch) occurred. Unfortunately it turns out this is a level triggred signal, ie. the bit will be set whenever the DSB is busy during the scanline window between start of delayed vblank and vtotal. Try to document that fact by renaming the bit. Sadly this also thwarts my plan to use this bit to sanity check that the (to be introduced) DSB based vblank evasion did its job correctly. That would require an edge triggered signal instead. So looks like we'll have to rely mostly on luck instead :( Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-26drm/i915/display: For MTL+ platforms skip mg dp programmingImre Deak1-0/+3
For MTL+ platforms we use PICA chips for Type-C support and hence mg programming is not needed. Fixes issue with drm warn of TC port not being in legacy mode. Cc: [email protected] Signed-off-by: Mika Kahola <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Gustavo Sousa <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-25drm/i915/psr: Modify dg2_activate_panel_replay to support eDPJouni Högander1-0/+13
There are couple of bits in PSR2_CTL which needs to be written in case of eDP Panel Replay Bspec: 68920 v2: use boolean instead of assuming eDP Panel Replay mean Early Transport Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-25drm/i915/psr: Check Early Transport for Panel Replay as wellJouni Högander1-3/+3
Move Early Transport validity check to be performed for Panel Replay as well and use Early Transport for eDP Panel Replay always. v2:set crtc_state->enable_psr2_su_region_et directly (not in if block) Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-25drm/i915/psr: Perform scanline indication check for Panel Replay as wellJouni Högander1-6/+6
Scanline indication needs to be checked and configure for both PSR2 and Panel Replay Selective Update. Move this check to intel_sel_update_config_valid. Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-25drm/i915/psr: Perform psr2 checks related to ALPM for Panel ReplayJouni Högander1-13/+28
eDP1.5 support ALPM with Panel Replay as well. We need to check ALPM related things for Panel Replay as well. Bspec: 68920 v5: - instead of using crtc_state->has_panel_replay provide aux_less flag v4: - do not move _compute_psr2_sdp_prior_scanline_indication - move ALPM related checks to separate function v3: move vblank check as well v2: do not move Vblank >= PSR2_CTL Block Count Number maximum line count check Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-25drm/i915/alpm: Make crtc_state as const in intel_alpm_compute_paramsJouni Högander2-5/+6
Intel_alpm_compute_params doesn't change crtc_state. Let's convert it as const. Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-25drm/i915/psr: HW will not allow PR on eDP when HDCP enabledJouni Högander1-0/+14
Take into account in Panel Replay compute config that HW will not allow PR on eDP when HDCP enabled. v2: add debug message to print out why Panel Replay is not possible Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-25drm/i915/psr: 128b/132b Panel Replay is not supported on eDPJouni Högander1-2/+19
Take into account that 128b/132b Panel Replay is not supported on eDP. Bspec: 68920 v2: - make crtc_state as const - add debug message to print out why Panel Replay is not possible Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-25drm/i915/psr: Check panel Early Transport capability for eDP PRJouni Högander1-5/+12
Our HW doesn't support panel replay without Early Transport on eDP. Bspec: 68920 Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-25drm/i915/psr: enable sink for eDP1.5 Panel ReplayJouni Högander1-6/+30
eDP1.5 allows Panel Replay on eDP as well. Take this into account when enabling sink PSR/Panel Replay. Write also PANEL_REPLAY_CONFIG2 register accordingly. v3: - set DP_PANEL_REPLAY_CRC_VERIFICATION in PANEL_REPLAY_CONFIG2 - PANEL_REPLAY_CONFIG2 is available in DP2.1 as well v2: do not configure ALPM for DP2.0 Panel Replay Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-25drm/i915/psr: Inform Panel Replay source support on eDP as wellJouni Högander1-2/+4
Display version >= 20 support eDP 1.5. Inform Panel Replay source support on eDP for display version >= 20. Bspec: 68920 Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-25drm/i915/psr: Check panel ALPM capability for eDP Panel ReplayJouni Högander1-0/+7
Our HW doesn't support Panel Replay without AUX_LESS ALPM on eDP. Check panel support for this and prevent eDP panel replay if it doesn't exits. Bspec: 68920 v3: remove excessive parens v2: use intel_alpm_aux_less_wake_supported Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-24drm/i915: Use the same vblank worker for atomic unpinMaarten Lankhorst5-2/+49
In case of legacy cursor update, the cursor VMA needs to be unpinned only after vblank. This exceeds the lifetime of the whole atomic commit. Any trick I attempted to keep the atomic commit alive didn't work, as drm_atomic_helper_setup_commit() force throttles on any old commit that wasn't cleaned up. The only option remaining is to remove the plane from the atomic commit, and use the same path as the legacy cursor update to clean the state after vblank. Changes since previous version: - Call the memset for plane state immediately when scheduling vblank, this prevents a use-after-free in cursor cleanup. Signed-off-by: Maarten Lankhorst <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-24drm/i915: Use vblank worker to unpin old legacy cursor fb safelyVille Syrjälä3-2/+30
The cursor hardware only does sync updates, and thus the hardware will be scanning out from the old fb until the next start of vblank. So in order to make the legacy cursor fastpath actually safe we should not unpin the old fb until we're sure the hardware has ceased accessing it. The simplest approach is to just use a vblank work here to do the delayed unpin. Not 100% sure it's a good idea to put this onto the same high priority vblank worker as eg. our timing critical gamma updates. But let's keep it simple for now, and it we later discover that this is causing problems we can think about adding a lower priority worker for such things. This patch is slightly reworked by Maarten Cc: Maarten Lankhorst <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Maarten Lankhorst <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-24drm/i915: Nuke the TGL+ chroma plane tile row alignment stuffVille Syrjälä3-26/+1
I don't think the display hardware really has such chroma plane tile row alignment requirements as outlined in commit d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned") Bspec had the same exact thing to say about earlier hardware as well, but we never cared and things work just fine. The one thing mentioned in that commit that is definitely true however is the fence alignment issue. But we don't deal with that on earlier hardware either. We do have code to deal with that issue for the first color plane, but not the chroma planes. So I think if we did want to check this more extensively we should do it in the same places where we already check the first color plane (namely convert_plane_offset_to_xy() and intel_fb_bo_framebuffer_init()). Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-24drm/i915: Update plane alignment requirements for TGL+Ville Syrjälä1-43/+56
Currently we still use the SKL+ PLANE_SURF alignment even for TGL+ even though the hardware no longer needs it. Introduce a separate tgl_plane_min_alignment() and update it to more accurately reflect the hardware requirements. v2: Don't screw up DPT+semiplanar 2MiB alignment Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-24drm/i915: Move intel_surf_alignment() into skl_univerals_plane.cVille Syrjälä3-80/+78
Now that all pre-skl platforms have their own .min_alignment() functions the remainder of intel_surf_alignment() can be hoisted into skl_univerals_plane.c (and renamed appropriately). Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-24drm/i915: Split pre-skl platforms out from intel_surf_alignment()Ville Syrjälä3-18/+96
Extract the necessary chunks from intel_surf_alignment() into per-platform variants for all pre-skl primary/sprite planes. Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-24drm/i915: Split cursor alignment to per-platform vfuncsVille Syrjälä3-21/+38
Split intel_cursor_alignment() into per-platform variants. Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-24drm/i915: Introduce fb->min_alignmentVille Syrjälä4-20/+34
Different planes could have different alignment requirements even for the same format/modifier. Collect the alignment requirements across all planes capable of scanning out the fb such that the alignment is satisfactory to all those planes. So far this was sort of handled by making sure intel_surf_alignment() declares the superset of all planes' alignment requirements, but maintaining that manually is annoying. So we're going to move towards each plane declaring only its own requirements, and thus we need code to generate the superset. v2: Drop the borked per-plane vma optimization (Imre) Assert that the plane's declared alignment is POT (Imre) Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Imre Deak <[email protected]>
2024-06-24drm/i915: Introduce the plane->min_alignment() vfuncVille Syrjälä10-34/+85
Different hardware generations have different scanout alignment requirements. Introduce a new vfunc that will allow us to make that distinction without horrible if-ladders. For now we directly plug in the existing intel_surf_alignment() and intel_cursor_alignment() functions. For fbdev we (temporarily) introduce intel_fbdev_min_alignment() that simply queries the alignment from the primary plane of the first crtc. TODO: someone will need to fix xe's alignment handling Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Acked-by: Rodrigo Vivi <[email protected]>
2024-06-24drm/i915/display: Consider adjusted_pixel_rate to be u64Mitul Golani1-1/+1
Consider adjusted_pixel_rate to be a u64 to match the return type of mul_u32_u32() and avoid any compiler dependency for do_div. Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal") Cc: Mitul Golani <[email protected]> Cc: Ankit Nautiyal <[email protected]> Cc: Suraj Kandpal <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Nathan Chancellor <[email protected]> Cc: [email protected] Reported-by: Nathan Chancellor <[email protected]> Closes: https://lore.kernel.org/r/20240619154207.GA1125704@thelio-3990X Signed-off-by: Mitul Golani <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Suraj Kandpal <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-24drm/i915/psr: Set DP_PSR_SU_REGION_SCANLINE_CAPTURE bit when neededJouni Högander1-0/+3
Setting DP_PSR_SU_REGION_SCANLINE_CAPTURE (Selective Update Region Scan Line Capture Indication in spec) bit was dropped when psr_enable_sink was split to _psr_enable_sink and _panel_replay_enable_sink. Add setting it back. Fixes: 32f0045f905c ("drm/i915/psr: Split enabling sink for PSR and Panel Replay") Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-20drm/i915: Pass intel_display to the encoder suspend/shutdown helpersImre Deak2-15/+15
Pass intel_display to the encoder suspend/shutdown helpers instead of drm_i915_private for better isolation. v2: Pass intel_display to HAS_DISPLAY() as well, update commit log accordingly. (Jani) Cc: Jani Nikula <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> # v1 Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-20drm/i915: Move encoder suspend/shutdown helpers to intel_encoder.cImre Deak2-0/+48
Move the encoder suspend/shutdown helpers to intel_encoder.c, this being the logical place for encoder functions. This also allows sharing the above helpers with the xe driver, done in a follow-up patch. While at it rename the functions using the usual intel_encoder prefix and in the functions rename the dev_priv parameter to i915. v2: Remove extra w/s in the include section. (Jani) Reviewed-by: Rodrigo Vivi <[email protected]> # v1 Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-20drm/i915/dsb: Document that the ATS fault bits are for mtl+Ville Syrjälä1-2/+2
The ATS faults have something to do with some new iommu stuff on mtl+. Document that the relevant DSB interrupt bits aren't valid for earlier platforms. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-20drm/i915: Drop useless intel_dsb.h includeVille Syrjälä1-1/+0
intel_crtc.c doens't need intel_dsb.h so don't include it. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-20drm/i915/dsb: Add i915.enable_dsb module parameterVille Syrjälä3-0/+7
As we extend the use of DSB for critical pipe/plane register programming, it'll be nice to have an escape valve at hand, in case things go very poorly. To that end, add a i915.enable_dsb modparam by which we can force the driver to take the pure mmio path instead. v2: Use 0400 permissions for the actual modparam (Jani) Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-20drm/i915/dsb: Convert the DSB code to use intel_display rather than i915Ville Syrjälä1-26/+26
The future direction will be to mainly use intel_display rather than i915 in the display code. Start on that path for the DSB code. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-20drm/i915/dsb: Plumb the whole atomic state into intel_dsb_prepare()Ville Syrjälä3-6/+11
The DSB code will need to examine both the old and new crtc states. Pass in the whole atomic state so we can dig up what we need. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-20drm/i915: Pass the whole atomic state to intel_color_prepare_commit()Ville Syrjälä3-9/+13
We'll have need to examine both the old and new crtc states in intel_color_prepare_commit(), so let's just pass in the whole atomic state. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-20drm/i915: Introduce intel_mode_vdisplay()Ville Syrjälä2-0/+11
The DSB code will need to know the hardware's idea of vertical active, as that is also what defines the start of undelayed vblank. Introduce a helper that gives us that information, in line with the other intel_mode_v*() functions. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-20drm/i915: Add flip done tracepointVille Syrjälä2-0/+24
Add a tracepoint to see exactly when async flips complete. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-20drm/i915: Add async flip tracepointVille Syrjälä4-7/+50
Add a separate tracepoint for async flips vs. sync plane updates to make it a bit easier to figure out what is happening. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-20drm/i915: Extract intel_crtc_arm_vblank_event()Ville Syrjälä2-10/+20
We'll need to arm the vblank event also from the future DSB based codepath. Extract the function that does the whold dance for us. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-19drm/i915: Enable plane/pipeDMC ATS fault interrupts on mtlVille Syrjälä1-0/+10
MTL has some new IOMMU thing that has a few new fault interrupts. Enable those so we can know if things are going poorly. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-19drm/i915: Enable pipeDMC fault interrupts on tgl+Ville Syrjälä1-2/+13
PipeDMC has its own fault interrupt. Enable that so that we can know if things are failing. While at it, define the other pipeDMC interrupt as well, even though we're not currently using it. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-19drm/i915: Nuke the intermediate pipe fault bitmasksVille Syrjälä1-4/+22
GEN8_DE_PIPE_IRQ_FAULT_ERRORS & co. don't really achieve anything. Get rid of them and just declare all the bits directly in gen8_de_pipe_fault_mask(). Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2024-06-19Merge drm/drm-next into drm-intel-nextJani Nikula3-29/+30
Sync to v6.10-rc3. Signed-off-by: Jani Nikula <[email protected]>
2024-06-19intel_alpm: Fix wrong offset for PORT_ALPM_* registersJouni Högander2-4/+7
PORT_ALPM_* registers are using MMIO_TRANS2 macro. This is not correct as they are port register. Use _PORT_MMIO instead. Fixes: 4ee30a448255 ("drm/i915/alpm: Add ALPM register definitions") Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-19Revert "drm/i915/psr: Disable early transport by default"Jouni Högander1-3/+0
This reverts commit f3c2031db7dfdf470a2d9bf3bd1efa6edfa72d8d. We want to notice possible issues faced with PSR2 Region Early Transport as early as possible -> let's revert patch disabling Region Early Transport by default. Also eDP 1.5 Panel Replay requires Early Transport. Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-19drm/i915/psr: Add new debug bit to disable Panel ReplayJouni Högander2-3/+9
Add new debug bit to be used with i915_edp_psr_debug debugfs interface. This can be used to disable Panel Replay. v2: ensure that fastset is performed when the bit changes Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-19drm/i915/psr: Disable PSR/Panel Replay on sink side for PSR onlyJouni Högander1-6/+6
Enabling/disabling Panel Replay on sink side has to be done before link training. We can't disable it in sink side on PSR disable. Fixes: 88ae6c65ecdb ("drm/i915/psr: Unify panel replay enable/disable sink") Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-19drm/i915/psr: Disable PSR2 SU Region ET if enable_psr module parameter is setJouni Högander1-1/+12
Currently PSR2 SU Region Early Transport is enabled by default on Lunarlake if panel supports it despite enable_psr module parameter value. This patch makes it possible for user to limit used PSR mode and prevent SU Region Early Transport by setting enable_psr as 2. With default (-1) PSR2 SU Region Early Transport is allowed. v2: fix/improve commit desciption Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-19drm/i915/psr: Disable Panel Replay if PSR mode is set via module parameterJouni Högander2-4/+26
If user is specifically limiting PSR mode to PSR1 or PSR2: disable Panel Replay. With default value -1 all modes are allowed including Panel Replay. Disabling PSR using value 0 disables Panel Replay as well. Also own compute config helper is added for Panel Replay. This makes sense because number of Panel Replay specific checks are increasing. v2: Squash adding Panel Replay compute config helper Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-19drm/i915/alpm: Fix port clock usage in AUX Less wake time calculationJouni Högander1-1/+2
Port clock is link rate in 10 kbit/s units. Take this into account when calculating AUX Less wake time. Fixes: da6a9836ac09 ("drm/i915/psr: Calculate aux less wake time") Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Animesh Manna <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-19drm/i915/display: Wa 16021440873 is writing wrong registerJouni Högander2-11/+5
Wa 16021440873 is writing wrong register. Instead of PIPE_SRCSZ_ERLY_TPT write CURPOS_ERLY_TPT. v2: use right offset as well Fixes: 29cdef8539c3 ("drm/i915/display: Implement Wa_16021440873") Signed-off-by: Jouni Högander <[email protected]> Reviewed-by: Mika Kahola <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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