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2019-07-11drm/i915: Don't pass stack garbage to pcode in the second data registerVille Syrjälä1-1/+1
Zero initialize val2 so that we don't pass stack garbage to the pcode qgv read command. I suspect in this case pcode just ignores the initial value in that registers, but better safe than sorry. Cc: Dan Carpenter <[email protected]> Reported-by: Dan Carpenter <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2019-07-11drm/i915: Use intel_ types in intel_atomic_commit()Ville Syrjälä1-39/+37
Make life less annoying by favoring the intel_ types over the drm_ types in intel_atomic_commit(). Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Imre Deak <[email protected]>
2019-07-11drm/i915: Use intel_ types in intel_{lock,modeset}_all_pipes()Ville Syrjälä1-17/+21
Streamline the code a bit by using intel_ types instead of the drm_ types. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Imre Deak <[email protected]>
2019-07-11drm/i915: Polish intel_atomic_track_fbs()Ville Syrjälä1-8/+9
Streamline the code a bit by using intel_ types instead of drm_ types in intel_atomic_track_fbs(). Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Imre Deak <[email protected]>
2019-07-11drm/i915: Polish intel_shared_dpll_swap_state()Ville Syrjälä3-15/+9
Use swap() instead of hand rolling it in intel_shared_dpll_swap_state(), and pass in the intel_atomic_state instead of drm_atomic_state. Makes the code less convoluted. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Imre Deak <[email protected]>
2019-07-11drm/i915: Simplify modeset_get_crtc_power_domains() argumentsVille Syrjälä1-11/+10
Pass just the crtc state to modeset_get_crtc_power_domains(). We can get the crtc from therein. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Imre Deak <[email protected]>
2019-07-11drm/i915: Use the "display core" power domain in vlv/chv set_cdclk()Ville Syrjälä1-6/+6
The PFI credit programming performed during cdclk change on vlv/chv requires access to a register in the disp2d power well. So far we've abused pipe-A power domain for this, but now we have the more appropriate "display core" domain so let's make use of it. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Imre Deak <[email protected]>
2019-07-11drm/i915/sdvo: Fix handling if zero hbuf sizeVille Syrjälä1-13/+19
The spec says: "A value of 0 indicates that this buffer does not exist" So we should not convert a hbuf_size of 0 into 1. Also pull the relevant code into a helper to avoid making the same mistake multiple times. And while at it fix the debug prints to not say "hbuf_len" twice. v2: s/%i/%u/ in the debug (Imre) Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Imre Deak <[email protected]>
2019-07-10drm/i915/ehl: Enable DDI-DMatt Roper1-0/+1
EHL has four DDI's (DDI-A and DDI-D share combo PHY A). Cc: José Roberto de Souza <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-10drm/i915: Transition port type checks to phy checksMatt Roper6-55/+55
Transition the remaining uses of intel_port_is_* over to the equivalent intel_phy_is_* functions and drop the port functions. v5: Fix a call in a debug function that's only called when CONFIG_DRM_I915_DEBUG_RUNTIME_PM is on. (CI) Cc: José Roberto de Souza <[email protected]> Cc: Lucas De Marchi <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-10drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespaceMatt Roper7-175/+176
Convert the code that operates directly on gen11 combo PHY's to use the new namespace. Combo PHY registers are those named "ICL_PORT_*" plus ICL_DPHY_CHKN. Note that a lot of the PHY programming happens in the MIPI DSI code. For clarity I've added a for_each_dsi_phy() to loop over the phys used by DSI. Since DSI always uses A & B on gen11, port=phy in all cases so it doesn't actually matter which form we use in the DSI code. I've used the phy iterator in code that's explicitly working with the combo PHY, but left the rest of the DSI code using the port iterator and namespace to minimize patch deltas. We can switch the rest of the DSI code over to use phy terminology later if this winds up being too confusing. v6: Drop an include of drm/i915_drm.h; that was previously included just for the definition of 'enum port' which this patch removes the need for. (Jose) Cc: José Roberto de Souza <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-10drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHYMatt Roper3-39/+59
Although the register name implies that it operates on DDI's, DPCLKA_CFGCR0_ICL actually needs to be programmed according to the PHY that's in use. I.e., when using EHL's DDI-D on combo PHY A, the bits described as "port A" in the bspec are what we need to set. The bspec clarifies: "[For EHL] DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA Clock Select chooses the PLL for both DDIA and DDID and drives port A in all cases." Also, since the CNL DPCLKA_CFGCR0 bit defines are still port-based, we create separate ICL-specific defines that accept the PHY rather than trying to share the same bit definitions between CNL and ICL. v5: Make icl_dpclka_cfgcr0_clk_off() take phy rather than port. When splitting the original patch the hunk to handle this wound up too late in the series. (Sparse) v6: Since we're already changing this code, s/DPCLKA_CFGCR0_ICL/ICL_DPCLKA_CFGCR0/ for consistency. (Jose) Bspec: 33148 Cc: José Roberto de Souza <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-10drm/i915/gen11: Start distinguishing 'phy' from 'port'Matt Roper2-1/+47
Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping. Because of this, both the bspec documentation and our i915 code has used the term "port" when talking about either DDI's or PHY's; it was always easy to tell what terms like "Port A" were referring to from the context. Unfortunately this is starting to break down now that EHL allows PHY-A to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving PHY-A considered "Port A" or "Port D?" The answer depends on which register we're working with, and even the bspec doesn't do a great job of clarifying this. Let's try to be more explicit about whether we're talking about the DDI or the PHY on gen11+ by using 'port' to refer to the DDI and creating a new 'enum phy' namespace to refer to the PHY in use. This patch just adds the new PHY namespace, new phy-based versions of intel_port_is_*(), and a helper to convert a port to a PHY. Transitioning various areas of the code over to using the PHY namespace will be done in subsequent patches to make review easier. We'll remove the intel_port_is_*() functions at the end of the series when we transition all callers over to using the PHY-based versions. v2: - Convert a few more 'port' uses to 'phy.' (Sparse) v3: - Switch DDI_CLK_SEL() back to 'port.' (Jose) - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use PHY for its bit definitions, even though the register description is given in terms of DDI. - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to using port and create separate ICL+ definitions that work in terms of PHY. v4: - Rebase and resolve conflicts with Imre's TC series. - This patch now just adds the namespace and a few convenience functions; the important changes are now split out into separate patches to make review easier. Suggested-by: Ville Syrjala <[email protected]> Cc: José Roberto de Souza <[email protected]> Cc: Lucas De Marchi <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: Imre Deak <[email protected]> Cc: Jani Nikula <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-10drm/i915: move intel_ddi_set_fia_lane_count to intel_tc.cLucas De Marchi3-42/+42
PORT_TX_DFLEXDPMLE1 is a FIA register so move it to intel_tc.c where we access other FIA registers. In Tiger Lake we have multiple/modular FIAs so it makes sense to start moving all access to their registers to a common place. While at it, make it clear that we will only ever call this function for ports with TC phy. Previously we were relying on tc_mode being TC_PORT_TBT_ALT for combo phy ports. However it's confusing since in this same function we have checks for is_tc_port. Also, if we manage to make each phy access only their own field, we may in future add them as a union inside intel_digital_port. v2: Fix coding style while moving the code Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-10drm/i915: fix include order in intel_tc.*Lucas De Marchi2-2/+3
Separate local includes with a blank line and sort the groups alphabetically. v2: don't make intel_tc.h be the first include v3: don't make local includes be included first Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-10drm/i915: make new intel_tc.c use uncore accessorsLucas De Marchi1-26/+31
Let's make the just created intel_tc.c already follow the trend of using i915 instead of dev_priv and calling the intel_uncore_*() functions. Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-10Merge drm/drm-next into drm-intel-next-queuedRodrigo Vivi5-14/+20
Catch-up with 5.2. Specially to remove a drm-tip merge fixup around intel_workarounds. Signed-off-by: Rodrigo Vivi <[email protected]>
2019-07-10drm/i915/icl: Fixed Input CSC Co-efficients for BT601/709Uma Shankar1-12/+12
Input CSC Co-efficients for BT601 and BT709 YCbCR to RGB conversion were slightly off. Fixed the same. v2: Fixed the co-eficients as there was issue with reference matrix, spotted by Ville. v3: Rebase Signed-off-by: Uma Shankar <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-10drm/i915/icl: Fix Y pre-offset for Full Range YCbCrUma Shankar1-2/+5
Fixed Y Pre-offset in case of Full Range YCbCr. v2: Rebase Reviewed-by: Ville Syrjälä <[email protected]> Suggested-by: Ville Syrjälä <[email protected]> Signed-off-by: Uma Shankar <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-10drm/i915/icl: Handle YCbCr to RGB conversion for BT2020 caseUma Shankar1-0/+24
Currently input csc for YCbCR to RGB conversion handles only BT601 and Bt709. Extending it to support BT2020 as well. v2: Fixed the co-efficients for LR to FR conversion, as suggested by Ville. v3: Fixed Y Pre-offset in case of Full Range YCbCr as suggested by Ville. v4: Split the v2 and v3 changes. v5: Rebase v6: Fix a rebase fumble. Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Uma Shankar <[email protected]> Signed-off-by: Shashank Sharma <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-09drm/i915/icl: Clear the shared port PLLs from the new crtc stateImre Deak1-5/+7
For consistency clear the icl_port_dplls from the new crtc state, when releasing the DPLLs from the old crtc state. Leaving them set could result in releasing the same PLLs multiple times from the same CRTC state incorrectly (if the same CRTC was first used for a TypeC port then for a combo PHY port). Leaving the stale pointers behind happens not to cause a problem atm (since the incorrect releasing will be a NOP), but we need to fix that for consistency. Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-09drm/i915: Clear the shared PLL from the put_dplls() hookImre Deak2-8/+14
For symmetry with the get_dplls() hook which sets the shared_dpll pointer clear the same pointer from the put_dplls() hook. While at it also constify the old crtc state. v2: - Constify the old crtc state. (Ville) Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-09drm/i915/sdvo: Add helpers to get the cmd/status stringVille Syrjälä1-10/+30
Add sdvo_cmd_name() and sdvo_cmd_status() helpers to avoid bothering the callers with the implementation details of the storage for these strings. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2019-07-09drm/i915/sdvo: Shrink sdvo_cmd_names[] stringsVille Syrjälä1-108/+111
Drop the redundant "SDVO_CMD_" prefix from the command name strings in sdvo_cmd_names[]. While at it throw away the unused struct name, and undef SDVO_CMD_NAME_ENTRY() when we're done. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2019-07-09drm/i915/sdvo: Remove duplicate SET_INPUT_TIMINGS_PART1 cmd name stringVille Syrjälä1-1/+0
sdvo_cmd_names[] contains two entries for SET_INPUT_TIMINGS_PART1. Remove one of them. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2019-07-09drm/i915/sdvo: Use named initializers for the SDVO command namesVille Syrjälä1-8/+8
Use named initializers to make it easier to associate the SDVO debug prints with the SDVO command defines. Also switch to using ARRAY_SIZE() instead of assuming that SDVO_CMD_STATUS_SCALING_NOT_SUPP is the last command type. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2019-07-09drm/i915: Add icl mipi dsi propertiesVandita Kulkarni2-2/+24
Add scaling and panel orientation properties for icl mipi dsi. v2: Add platform specific function (Ville) v3: Remove redundant check and update scaler call (Jani, Ville) Signed-off-by: Vandita Kulkarni <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-09drm/i915/hdcp: debug logs for sink related failuresRamalingam C1-3/+9
Adding few more debug logs to identify the sink specific HDCP failures along with a out of mem failure. v2: Capturing the Bug and a-b Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110991 Signed-off-by: Ramalingam C <[email protected]> Signed-off-by: Uma Shankar <[email protected]> cc: Daniel Vetter <[email protected]> Acked-by: Daniel Vetter <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-05drm/i915: Remove set but not used variable 'intel_dig_port'YueHaibing1-2/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/i915/display/intel_ddi.c: In function 'intel_ddi_get_config': drivers/gpu/drm/i915/display/intel_ddi.c:3774:29: warning: variable 'intel_dig_port' set but not used [-Wunused-but-set-variable] struct intel_digital_port *intel_dig_port; It is never used, so can be removed. Signed-off-by: YueHaibing <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-05drm/i915: Remove set but not used variable 'encoder'YueHaibing1-5/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/i915/display/intel_dp.c: In function 'intel_dp_set_drrs_state': drivers/gpu/drm/i915/display/intel_dp.c:6623:24: warning: variable 'encoder' set but not used [-Wunused-but-set-variable] It's never used, so can be removed.Also remove related variable 'dig_port' Signed-off-by: YueHaibing <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-05drm/i915/ehl: Add support for DPLL4 (v10)Vivek Kasireddy5-4/+60
This patch adds support for DPLL4 on EHL that include the following restrictions: - DPLL4 cannot be used with DDIA (combo port A internal eDP usage). DPLL4 can be used with other DDIs, including DDID (combo port A external usage). - DPLL4 cannot be enabled when DC5 or DC6 are enabled. - The DPLL4 enable, lock, power enabled, and power state are connected to the MGPLL1_ENABLE register. v2: (suggestions from Bob Paauwe) - Rework ehl_get_dpll() function to call intel_find_shared_dpll() and iterate twice: once for Combo plls and once for MG plls. - Use MG pll funcs for DPLL4 instead of creating new ones and modify mg_pll_enable to include the restrictions for EHL. v3: Fix compilation error v4: (suggestions from Lucas and Ville) - Treat DPLL4 as a combo phy PLL and not as MG PLL - Disable DC states when this DPLL is being enabled - Reuse icl_get_dpll instead of creating a separate one for EHL v5: (suggestion from Ville) - Refcount the DC OFF power domains during the enabling and disabling of this DPLL. v6: rebase v7: (suggestion from Imre) - Add a new power domain instead of iterating over the domains assoicated with DC OFF power well. v8: (Ville and Imre) - Rename POWER_DOMAIN_DPLL4 TO POWER_DOMAIN_DPLL_DC_OFF - Grab a reference in intel_modeset_setup_hw_state() if this DPLL was already enabled perhaps by BIOS. - Check for the port type instead of the encoder v9: (Ville) - Move the block of code that grabs a reference to the power domain POWER_DOMAIN_DPLL_DC_OFF to intel_modeset_readout_hw_state() to ensure that there is a reference present before this DPLL might get disabled. v10: rebase Cc: José Roberto de Souza <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: Matt Roper <[email protected]> Cc: Imre Deak <[email protected]> Signed-off-by: Vivek Kasireddy <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-05drm/i915: Clean up skl vs. icl plane formatsVille Syrjälä1-67/+66
Split the format lists for different planes on skl/icl more cleanly. On skl+ we have just two types of planes: those can do planar and those that can't. On icl we have three types of planes: hdr planes, sdr planes that can do planar, and sdr planes that can't do planar. Those latter two are the same set of planes we must when choose from when picking the UV vs. Y plane for planar scanout. So we shall just designate them sdr uv planes and sdr y planes. Reviewed-by: Maarten Lankhorst <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-05drm/i915: Cosmetic fix for skl+ plane switch statementVille Syrjälä1-2/+2
One of the switch cases has the byte order vs. format bits reversed to all the other cases. Appease the ocd and reorder them. Reviewed-by: Maarten Lankhorst <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-05drm/i915: Program plane gamma rampsVille Syrjälä1-0/+142
All sprite planes have a progammable gamma ramp. Set it up with a linear ramp on all platforms. This actually matches the reset value but soon we'll want to reprogram this ramp on some machines, so let's just set it up across the board. Note that on pre-IVB the hardware bypasses the gamma unit unless a YCbCr pixel format is used. v2: Add parens around << in ilk_linear_gamma() Skip gamma programming for RGB on pre-IVB s/DVSGAMC/DVSGAMC_G4X/ Reviewed-by: Maarten Lankhorst <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-05drm/i915: Disable sprite gamma on ivb-bdwVille Syrjälä1-0/+2
We don't currently have any use for the sprite gamma on ivb-bdw. Let's disable it. We already do that on skl+. On pre-ivb there is no way to disable the sprite gamma, and it only affects YCbCr pixel formats, whereas on ivb+ it also affects RGB formats. Reviewed-by: Maarten Lankhorst <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-05drm/i915: Add windowing for primary planes on gen2/3 and chvVille Syrjälä1-9/+31
Plane B and C (note that we don't actually expose plane C currently) on gen2/3 have a window generator, as does the primary plane on CHV pipe B. So let's allow positioning of these planes freely within the pipe source area. Plane A on gen2/3 seems to have some kind of partial window generator which would allow you to cut the plane off midway through the scanout, but it would still have to start at the top-left corner of the pipe, and it would have to be full width. That's doesn't sound all that useful, so for simplicity let's just keep to the idea that plane A has to be fullscreen. Gen4 removed the plane A/B windowing support entirely, and it wasn't reintroduced until SKL (apart from the CHV pipe B special case). v2: s/plane/i9xx_plane/ etc. (James) v3: Make it less confusing v4: Deal with IS_GEN() Reviewed-by: Maarten Lankhorst <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-04drm/i915/overlay: Stash the kernel context on initialisationChris Wilson1-3/+7
Simplify runtime request creation by storing the context we need to use during initialisation. This allows us to remove one more hardcoded engine lookup. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-03drm/i915: Add N & CTS values for 10/12 bit deep colorAditya Swarup1-11/+68
Adding N & CTS values for 10/12 bit deep color from Appendix C table in HDMI 2.0 spec. The correct values for N is not chosen automatically by hardware for deep color modes. v2: Remove unnecessary initialization of size Signed-off-by: Aditya Swarup <[email protected]> Cc: Clint Taylor <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-03drm/i915: Use port clock to set correct N valueAditya Swarup1-3/+1
Use port_clock to check the clock values in n/cts lookup table instead of crtc_clock. As port_clock is already adjusted based on color mode set (8 bit or deep color), this will help in checking clock values for deep color modes from n/cts lookup table. Signed-off-by: Aditya Swarup <[email protected]> Cc: Clint Taylor <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-03drm/i915: Deal with machines that expose less than three QGV pointsVille Syrjälä1-5/+10
When SAGV is forced to disabled/min/med/max in the BIOS pcode will only hand us a single QGV point instead of the normal three. Fix the code to deal with that instead declaring the bandwidth limit to be 0 MB/s (and thus preventing any planes from being enabled). Also shrink the max_bw sturct a bit while at it, and change the deratedbw type to unsigned since the code returns the bw as an unsigned int. Since we now keep track of how many qgv points we got from pcode we can drop the earlier check added for the "pcode doesn't support the memory subsystem query" case. Cc: [email protected] Cc: Mark Janes <[email protected]> Cc: Matt Roper <[email protected]> Cc: Clint Taylor <[email protected]> Fixes: c457d9cf256e ("drm/i915: Make sure we have enough memory bandwidth on ICL") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110838 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Matt Roper <[email protected]>
2019-07-03drm/i915/display: Handle lost primary_port across suspendChris Wilson1-9/+4
icl-dsi is dying on suspend/resume at RIP: 0010:icl_update_active_dpll+0x2c/0xa0 [i915] which appears due to the loss of the time primary_port across suspend. Protect against the potential NULL dereference by assuming ICL_PORT_DPLL_DEFAULT unless the port is actively specified otherwise. Fixes: 24a7bfe0c2d7 ("drm/i915: Keep the TypeC port mode fixed when the port is active") Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-03drm/i915: synchronize_irq() against the actual irqVille Syrjälä2-2/+2
When eliminating our use of drm_irq_install() I failed to convert all our synchronize_irq() calls to consult pdev->irq instead of dev_priv->drm.irq. As we no longer populate dev_priv->drm.irq we're no longer synchronizing against anything. v2: Add intel_syncrhonize_irq() (Chris) Cc: Chris Wilson <[email protected]> Reported-by: Imre Deak <[email protected]> Fixes: b318b82455bd ("drm/i915: Nuke drm_driver irq vfuncs") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111012 Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-01drm/i915/ehl: Don't program PHY_MISC on EHL PHY CMatt Roper1-3/+25
Although EHL added a third combo PHY, no PHY_MISC register was added for PHY C. The bspec indicates that there's no need to program the "DE to IO Comp Pwr Down" setting for this PHY that we usually need to set in PHY_MISC. v2: - Add IS_ELKHARTLAKE() guards since future platforms that have a PHY C are likely to reinstate the PHY_MISC register. (Jose) - Use goto's to skip PHY_MISC programming & minimize code deltas. (Jose) Bspec: 33148 Cc: José Roberto de Souza <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: José Roberto de Souza <[email protected]>
2019-07-01drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans()Matt Roper1-6/+6
The port parameter hasn't been used since the last bspec phy programming update. Drop it to make some upcoming changes simpler. References: 9659c1af451a ("drm/i915/icl: combo port vswing programming changes per BSPEC") Cc: Clint Taylor <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Clint Taylor <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-01drm/i915: WARN about invalid lane reversal in TBT-alt/DP-alt modesImre Deak1-0/+2
Lane reversal happens only in the FIA module for TBT-alt/DP-alt mode, so WARN if lane reversal is attempted at a different level. See the BSpec DDI_BUF_CTL register description. Cc: Manasi Navare <[email protected]> Cc: José Roberto de Souza <[email protected]> Cc: Rodrigo Vivi <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-01drm/i915: Remove unneeded disconnect in TypeC legacy port modeImre Deak3-23/+4
Disconnecting the TypeC PHY when the port is in legacy mode is not necessary: - BSpec doesn't specify a disconnect sequence for legacy mode. - The use of the PHY is dedicated for the display in legacy mode. - We keep the PHY always connected during runtime as well in legacy mode. We disconnect the PHY when needed during a disabling modeset for the port, so we can also remove the disconnect call from the destroy hook. Cc: José Roberto de Souza <[email protected]> Cc: Rodrigo Vivi <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-01drm/i915: Add state verification for the TypeC port modeImre Deak3-9/+98
Add state verification for the TypeC port mode wrt. the port's AUX power well enabling/disabling. Also check the correctness of changing the port mode: - When enabling/disabling the AUX power well for a TypeC port we must hold the TypeC port lock - the case for AUX transfers - or hold a Type C port link reference - the case for modeset enabling/disabling. - When changing the TypeC port mode the port's AUX power domain must be disabled. v2: (Ville) - Simplify power_well_async_ref_count(). - Fix the commit log, clarifying what are the valid conditions to enable/disable the AUX power wells. Cc: José Roberto de Souza <[email protected]> Cc: Rodrigo Vivi <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-01drm/i915: Keep the TypeC port mode fixed when the port is activeImre Deak6-30/+239
The TypeC port mode needs to stay fixed whenever the port is active. Do that by introducing a tc_link_refcount to account for active ports, avoiding changing the port mode if a reference is held. During the modeset commit phase we also have to reset the port mode and update the active PLL reflecting the new port mode. We can do this only once the port and its old PLL has been already disabled. Add the new encoder update_prepare/complete hooks that are called around the whole enabling sequence. The TypeC specific hooks of these will reset the port mode, update the active PLL if the port will be active and ensure that the port mode will stay fixed for the duration of the whole enabling sequence by holding a tc_link_refcount. During the port enabling, the pre_pll_enable/post_pll_disable hooks will take/release a tc_link_refcount to ensure the port mode stays fixed while the port is active. Changing the port mode should also be avoided during connector detection and AUX transfers if the port is active, we'll do that by checking the port's tc_link_refcount. When resetting the port mode we also have to take into account the maximum lanes provided by the FIA. It's guaranteed to be 4 in TBT-alt and legacy modes, but there may be less lanes available in DP-alt mode, in which case we have to fall back to TBT-alt mode. While at it also update icl_tc_phy_connect()'s code comment, reflecting the current way of switching the port mode. v2: - Add the update_prepare/complete hooks to the encoder instead of the connector. (Ville) - Simplify intel_connector_needs_modeset() by removing redundant if. (Ville) v3: - Fix sparse warning, marking static functions as such. v4: - Rebase on drm-tip. Cc: Ville Syrjälä <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Maarten Lankhorst <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-01drm/i915/icl: Reserve all required PLLs for TypeC portsImre Deak3-42/+131
When enabling a TypeC port we need to reserve all the required PLLs for it, the TBT PLL for TBT-alt and the MG PHY PLL for DP-alt/legacy sinks. We can select the proper PLL for the current port mode from the reserved PLLs only once we selected and locked down the port mode for the whole duration of the port's active state. Resetting and locking down the port mode can in turn happen only during the modeset commit phase once we disabled the given port and the PLL it used. To support the above reserve-and-select PLL semantic we store the reserved PLLs along with their HW state in the CRTC state and provide a way to select the active PLL from these. The selected PLL along with its HW state will be pointed at by crtc_state->shared_dpll/dpll_hw_state as in the case of other port types. Besides reserving all required PLLs no functional changes. v2: - Fix releasing the ICL PLLs, not clearing the PLLs from the old crtc_state. - Init port_dpll to ICL_PORT_DPLL_DEFAULT closer to where port_dpll is used for symmetry with the corresponding ICL_PORT_DPLL_MG_PHY init. (Ville) v3: - Add FIXME: for clearing the ICL port PLLs from the new crtc state. Cc: Ville Syrjälä <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Maarten Lankhorst <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-01drm/i915/icl: Split getting the DPLLs to port type specific functionsImre Deak1-34/+66
For clarity factor out the combo PHY and TypeC PHY specific code from icl_get_dplls() into their own functions. No functional changes. Cc: Ville Syrjälä <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Maarten Lankhorst <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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