aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/display
AgeCommit message (Collapse)AuthorFilesLines
2019-08-22drm/i915: Do not unmask PSR interruption in IRQ postinstallJosé Roberto de Souza2-3/+4
No need to unmask PSR interrutpion if PSR is not enabled, better move the call to intel_psr_enable_source(). v2: Renamed intel_psr_irq_control() to psr_irq_control() (Lucas) Cc: Rodrigo Vivi <[email protected]> Cc: Dhinakaran Pandiyan <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-22drm/i915: Add transcoder restriction to PSR2José Roberto de Souza1-0/+15
According to PSR2_CTL definition in BSpec there is only one instance of PSR2_CTL. Platforms gen < 12 with EDP transcoder only support PSR2 on TRANSCODER_EDP while on TGL PSR2 is only supported by TRANSCODER_A. Since BDW PSR is allowed on any port, but we need to restrict by transcoder. v8: Renamed _psr2_supported_in_trans() to psr2_supported() (Lucas) v9: Renamed psr2_supported() to transcoder_has_psr2() (Ville) BSpec: 7713 BSpec: 20584 Cc: Dhinakaran Pandiyan <[email protected]> Cc: Rodrigo Vivi <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Anshuman Gupta <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-22drm/i915/psr: Make PSR registers relative to transcodersJosé Roberto de Souza1-45/+59
PSR registers are a mess, some have the full address while others just have the additional offset from psr_mmio_base. For BDW+ psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET + 0x800 and using it makes more difficult for people with an PSR register address or PSR register name from from BSpec as i915 also don't match the BSpec names. For HSW psr_mmio_base is _DDI_BUF_CTL_A + 0x800 and PSR registers are only available in DDIA. Other reason to make relative to transcoder is that since BDW every transcoder have PSR registers, so in theory it should be possible to have PSR enabled in a non-eDP transcoder. So for BDW+ we can use _TRANS2() to get the register offset of any PSR register in any transcoder while for HSW we have _HSW_PSR_ADJ that will calculate the register offset for the single PSR instance, noting that we are already guarded about trying to enable PSR in other port than DDIA on HSW by the 'if (dig_port->base.port != PORT_A)' in intel_psr_compute_config(), this check should only be valid for HSW and will be changed in future. PSR2 registers and PSR_EVENT was added after Haswell so that is why _PSR_ADJ() is not used in some macros. The only registers that can not be relative to transcoder are PSR_IMR and PSR_IIR that are not relative to anything, so keeping it hardcoded. That changed for TGL but it will be handled in another patch. Also removing BDW_EDP_PSR_BASE from GVT because it is not used as it is the only PSR register that GVT have. v5: - Macros changed to be more explicit about HSW (Dhinakaran) - Squashed with the patch that added the tran parameter to the macros (Dhinakaran) v6: - Checking for interruption errors after module reload in the transcoder that will be used (Dhinakaran) - Using lowercase to the registers offsets v7: - Removing IS_HASWELL() from registers macros(Jani) Cc: Dhinakaran Pandiyan <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: Zhi Wang <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-22drm/i915: Replace i915_vma_put_fence()Chris Wilson1-4/+0
Avoid calling i915_vma_put_fence() by using our alternate paths that bind a secondary vma avoiding the original fenced vma. For the few instances where we need to release the fence (i.e. on binding when the GGTT range becomes invalid), replace the put_fence with a revoke_fence. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-22Merge drm/drm-next into drm-intel-next-queuedRodrigo Vivi4-30/+70
We need the rename of reservation_object to dma_resv. The solution on this merge came from linux-next: From: Stephen Rothwell <[email protected]> Date: Wed, 14 Aug 2019 12:48:39 +1000 Subject: [PATCH] drm: fix up fallout from "dma-buf: rename reservation_object to dma_resv" Signed-off-by: Stephen Rothwell <[email protected]> --- drivers/gpu/drm/i915/gt/intel_engine_pool.c | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pool.c b/drivers/gpu/drm/i915/gt/intel_engine_pool.c index 03d90b49584a..4cd54c569911 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_pool.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_pool.c @@ -43,12 +43,12 @@ static int pool_active(struct i915_active *ref) { struct intel_engine_pool_node *node = container_of(ref, typeof(*node), active); - struct reservation_object *resv = node->obj->base.resv; + struct dma_resv *resv = node->obj->base.resv; int err; - if (reservation_object_trylock(resv)) { - reservation_object_add_excl_fence(resv, NULL); - reservation_object_unlock(resv); + if (dma_resv_trylock(resv)) { + dma_resv_add_excl_fence(resv, NULL); + dma_resv_unlock(resv); } err = i915_gem_object_pin_pages(node->obj); which is a simplified version from a previous one which had: Reviewed-by: Christian König <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2019-08-21drm/i915: Do not create a new max_bpc prop for MST connectorsVille Syrjälä1-1/+9
We're not allowed to create new properties after device registration so for MST connectors we need to either create the max_bpc property earlier, or we reuse one we already have. Let's do the latter apporach since the corresponding SST connector already has the prop and its min/max are correct also for the MST connector. The problem was highlighted by commit 4f5368b5541a ("drm/kms: Catch mode_object lifetime errors") which results in the following spew: [ 1330.878941] WARNING: CPU: 2 PID: 1554 at drivers/gpu/drm/drm_mode_object.c:45 __drm_mode_object_add+0xa0/0xb0 [drm] ... [ 1330.879008] Call Trace: [ 1330.879023] drm_property_create+0xba/0x180 [drm] [ 1330.879036] drm_property_create_range+0x15/0x30 [drm] [ 1330.879048] drm_connector_attach_max_bpc_property+0x62/0x80 [drm] [ 1330.879086] intel_dp_add_mst_connector+0x11f/0x140 [i915] [ 1330.879094] drm_dp_add_port.isra.20+0x20b/0x440 [drm_kms_helper] ... Cc: [email protected] Cc: Lyude Paul <[email protected]> Cc: [email protected] Cc: Daniel Vetter <[email protected]> Cc: Sean Paul <[email protected]> Fixes: 5ca0ef8a56b8 ("drm/i915: Add max_bpc property for DP MST") Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: José Roberto de Souza <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2019-08-21drm/i915/hdmi: make hdcp2_msg_data constJani Nikula1-1/+1
It's static const data, make it so. Cc: Ramalingam C <[email protected]> Reviewed-by: Ramalingam C <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-21drm/i915/hdmi: stylistic cleanup around hdcp2_msg_dataJani Nikula1-20/+19
Split struct declaration and array definition. Fix indents and whitespace. No functional changes. Cc: Ramalingam C <[email protected]> Reviewed-by: Ramalingam C <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-21drm/i915/dp: make hdcp2_dp_msg_data constJani Nikula1-5/+5
It's static const data, make it so. Cc: Ramalingam C <[email protected]> Reviewed-by: Ramalingam C <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-21drm/i915/dp: avoid shadowing variablesJani Nikula1-4/+4
Everything seems to be all right, but shadowing is to be avoided. Cc: Ramalingam C <[email protected]> Reviewed-by: Ramalingam C <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-21drm/i915/dp: stylistic cleanup around hdcp2_msg_dataJani Nikula1-34/+36
Split struct declaration and array definition. Fix indents and whitespace. No functional changes. Cc: Ramalingam C <[email protected]> Reviewed-by: Ramalingam C <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-21drm/i915: Fix HW readout for crtc_clock in HDMI modeImre Deak1-2/+2
The conversion during HDMI HW readout from port_clock to crtc_clock was missed when HDMI 10bpc support was added, so fix that. v2: - Unscrew the non-HDMI case. Fixes: cd9e11a8bf25 ("drm/i915/icl: Add 10-bit support for hdmi") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109593 Cc: Radhakrishna Sripada <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit 2969a78aead38b49e80c821a5c683544ab16160d) Signed-off-by: Jani Nikula <[email protected]>
2019-08-21Merge tag 'drm-misc-next-2019-08-19' of ↵Dave Airlie1-2/+2
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.4: UAPI Changes: Cross-subsystem Changes: Core Changes: - dma-buf: add reservation_object_fences helper, relax reservation_object_add_shared_fence, remove reservation_object seq number (and then restored) - dma-fence: Shrinkage of the dma_fence structure, Merge dma_fence_signal and dma_fence_signal_locked, Store the timestamp in struct dma_fence in a union with cb_list Driver Changes: - More dt-bindings YAML conversions - More removal of drmP.h includes - dw-hdmi: Support get_eld and various i2s improvements - gm12u320: Few fixes - meson: Global cleanup - panfrost: Few refactors, Support for GPU heap allocations - sun4i: Support for DDC enable GPIO - New panels: TI nspire, NEC NL8048HL11, LG Philips LB035Q02, Sharp LS037V7DW01, Sony ACX565AKM, Toppoly TD028TTEC1 Toppoly TD043MTEA1 Signed-off-by: Dave Airlie <[email protected]> [airlied: fixup dma_resv rename fallout] From: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20190819141923.7l2adietcr2pioct@flea
2019-08-20drm/i915: Fix DP-MST crtc_maskVille Syrjälä1-1/+1
Each fake MST encoder is tied to a specific pipe. Fix the encoder's crtc_mask to reflect that fact. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Dhinakaran Pandiyan <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-20drm/i915/tgl: Move transcoders to pipes' powerwellsJosé Roberto de Souza1-2/+2
When trying to read registers from transcoder C and D while PG3 is ON it causes unclaimed access warnings. Adding the powerwells for the pipes fixes the issue, but doesn't match the spec. Signed-off-by: José Roberto de Souza <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-20drm/i915/tgl: disable DDICLucas De Marchi1-2/+1
The current SKUs added for Tiger Lake don't have DDIC hooked up, even though it is supported by the SoC. The current state for these SKUs is problematic since while enabling the combo phy, PORT_COMP_DW* return 0xFFFFFFFF, which is invalid per register definition. During initialization we check what phys are not yet enabled by reading PHY_MISC_C and try to enable it by toggling the "DE to IO Comp Pwr Down" bit. But after that any read to the PORT_COMP_DW* returns invalid results. This removes the following warning [56997.634353] Missing case (val == 4294967295) [56997.639241] WARNING: CPU: 5 PID: 768 at drivers/gpu/drm/i915/display/intel_combo_phy.c:54 cnl_get_procmon_ref_values+0xc9/0xf0 [i915] [56997.639808] Modules linked in: i915(+) prime_numbers x86_pkg_temp_thermal coretemp kvm_intel kvm irqbypass crct10dif_pclmul crc32_pclmul ghash_clmulni_intel e1000e [last unloaded: prime_numbers] [56997.639808] CPU: 5 PID: 768 Comm: insmod Tainted: G U W 5.2.0-demarchi+ #65 [56997.639808] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWI1.R00.2252.A03.1906270154 06/27/2019 [56997.639808] RIP: 0010:cnl_get_procmon_ref_values+0xc9/0xf0 [i915] [56997.639808] Code: 2c a0 85 c9 74 e0 81 f9 00 00 00 01 75 09 48 c7 c0 0c a4 2c a0 eb cf 48 c7 c6 3c 3a 31 a0 48 c7 c7 40 3a 31 a0 e8 6b 4d ea e0 <0f> 0b 48 c7 c0 00 a4 2c a0 eb b1 48 c7 c0 24 a4 2 c a0 eb a8 e8 be [56997.639808] RSP: 0018:ffffc9000068f8a8 EFLAGS: 00010286 [56997.639808] RAX: 0000000000000000 RBX: ffff88848fa90000 RCX: 0000000000000000 [56997.639808] RDX: ffff8884a08b5ef8 RSI: ffff8884a08a6658 RDI: 00000000ffffffff [56997.639808] RBP: 0000000000000002 R08: 0000000000000000 R09: 0000000000000000 [56997.639808] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88848fa90000 [56997.639808] R13: 0000000000000000 R14: 0000000000000002 R15: 0006c00000162000 [56997.639808] FS: 00007f61ca3d12c0(0000) GS:ffff8884a0880000(0000) knlGS:0000000000000000 [56997.639808] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [56997.639808] CR2: 00007f71be6a92c0 CR3: 0000000494750006 CR4: 0000000000760ee0 [56997.639808] PKRU: 55555554 [56997.639808] Call Trace: [56997.639808] cnl_verify_procmon_ref_values+0x36/0xf0 [i915] [56997.639808] ? rcu_read_lock_sched_held+0x6f/0x80 [56997.639808] ? gen11_fwtable_read32+0x257/0x290 [i915] [56997.639808] icl_combo_phy_verify_state.part.0+0x22/0xa0 [i915] [56997.639808] intel_combo_phy_init+0x17e/0x3e0 [i915] [56997.639808] ? icl_display_core_init+0x2c/0x1a0 [i915] [56997.639808] ? _raw_spin_unlock_irqrestore+0x4c/0x60 [56997.639808] icl_display_core_init+0x34/0x1a0 [i915] [56997.639808] intel_power_domains_init_hw+0x200/0x570 [i915] [56997.639808] i915_driver_probe+0x103b/0x17e0 [i915] [56997.639808] ? printk+0x53/0x6a [56997.639808] i915_pci_probe+0x3b/0x190 [i915] We may or may not need to change the implementation to account for DDIC being available on other SKUs. For now I think the best thing to do is to just disable the port. Cc: José Roberto de Souza <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-20drm/i915: Sanitize PHY state during display core uninitImre Deak1-6/+11
To work around a DMC/Punit issue on ICL where the driver's ICL_PORT_COMP_DW8/IREFGEN PHY setting is lost when entering/exiting DC6 state, make sure to reinit the PHY whenever disabling DC states. Similarly the driver's PHY/DBUF/CDCLK settings should have been preserved across DC5/6 transitions, so check this on all platforms. This gets rid of the following WARN during suspend: Combo PHY A HW state changed unexpectedly Signed-off-by: Imre Deak <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-20drm/i915: Fix HW readout for crtc_clock in HDMI modeImre Deak2-3/+3
The conversion during HDMI HW readout from port_clock to crtc_clock was missed when HDMI 10bpc support was added, so fix that. v2: - Unscrew the non-HDMI case. Fixes: cd9e11a8bf25 ("drm/i915/icl: Add 10-bit support for hdmi") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109593 Cc: Radhakrishna Sripada <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-19drm/i915/gen11: Allow usage of all GPIO pinsMatt Roper3-50/+3
Our pin mapping tables for ICP and MCC currently only list the standard GPIO pins used for various output ports. Even through ICP's standard pin usage only utilizes pins 1, 2, and 9-12, and MCC's standard pin usage only uses pins 1, 2, and 9, these platforms do still have GPIO registers to address pins in the range 1-3 and 9-14. OEM's may remap GPIO usage in non-standard ways (and provide the actual mapping via VBT settings), so we shouldn't exclude pins on these platforms just because they aren't part of the standard mappings. TGP's standard pin tables contains all the possible pins, so let's rename them to "icp" and use them for all PCH >= PCH_ICP. This will prevent intel_gmbus_is_valid_pin from rejecting non-standard pin usage that an OEM specifies via the VBT. Note that this will cause pin 9 to be labeled as "tc1" instead of "dpc" in debug messages on platforms with the MCC PCH, but that may actually help avoid confusion since the text strings will now be the same on all gen11+ platforms instead of being different on just EHL. v2: Drop now-unused MCC_DDC_BUS_DDI_* names. v3: We want to compare against INTEL_PCH_TYPE, not INTEL_PCH_ID. Bspec: 8417 Cc: José Roberto de Souza <[email protected]> Cc: Lucas De Marchi <[email protected]> Cc: Vivek Kasireddy <[email protected]> Cc: Jani Nikula <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-16drm/i915: Wrappers for display register waitsDaniele Ceraolo Spurio16-233/+113
To reduce the number of explicit dev_priv->uncore calls in the display code ahead of the introduction of dev_priv->de_uncore, this patch introduces a wrapper for one of the main usages of it, the register waits. When we transition to the new uncore, we can just update the wrapper to point to the appropriate structure. Since the vast majority of waits are on a set or clear of a bit or mask, add set & clear flavours of the wrapper to simplify the code. Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Ville Syrjälä <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-16drm/i915: Move gmbus definitions out of i915_reg.hDaniele Ceraolo Spurio1-0/+22
They're not related to registers, so move them to the more appropriate intel_gmbus.h Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Jani Nikula <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-16drm/i915: Move i915_power_well_id out of i915_reg.hDaniele Ceraolo Spurio3-0/+23
It has nothing to do with registers, so move it to the more appropriate intel_display_power.h Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Imre Deak <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-16drm/i915: Markup expected timeline locks for i915_activeChris Wilson1-1/+1
As every i915_active_request should be serialised by a dedicated lock, i915_active consists of a tree of locks; one for each node. Markup up the i915_active_request with what lock is supposed to be guarding it so that we can verify that the serialised updated are indeed serialised. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-16drm/i915: Extract intel_frontbuffer active trackingChris Wilson6-160/+284
Move the active tracking for the frontbuffer operations out of the i915_gem_object and into its own first class (refcounted) object. In the process of detangling, we switch from low level request tracking to the easier i915_active -- with the plan that this avoids any potential atomic callbacks as the frontbuffer tracking wishes to sleep as it flushes. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-14drm/i915: Disregard drm_mode_config.fb_baseChris Wilson2-7/+5
The fb_base is only used for communicating the GTT BAR from one piece of the display code (kms setup) to another (fbdev). What is required in the fbdev is just the aperture address which should be derived from the bo we allocate for the framebuffer directly. The same appears true for drm/; it is not used by the core or the uAPI, it is merely for conveniently passing a device address from bit of display management code to another. v2: Note that since we only expose enough of a system map to cover our single framebuffer, the screen_base/size and the smem are one and the same. Signed-off-by: Chris Wilson <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Maarten Lankhorst <[email protected]> Cc: Anusha Srivatsa <[email protected]> Reviewed-by: Anusha Srivatsa <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-13dma-buf: rename reservation_object to dma_resvChristian König1-2/+2
Be more consistent with the naming of the other DMA-buf objects. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/323401/
2019-08-12drm/i915/overlay: Switch to using i915_active trackingChris Wilson1-65/+64
Remove the raw i915_active_request tracking in favour of the higher level i915_active tracking for the sole purpose of making the lockless transition easier in later patches. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-12drm/i915/tgl: Fixing up list of PG3 power domains.Anshuman Gupta1-6/+0
The DDI-IO power wells (PWR_WELL_CTL_DDI) are backing the IO/PHY functionality, which doesn't need the PG3 power power well. Accordingly fixing up the list of PG3 power domains. Cc: Imre Deak <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Anshuman Gupta <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-12drm/i915/icl: Remove DDI IO power domain from PG3 power domainsAnshuman Gupta1-5/+0
The DDI-IO power wells (PWR_WELL_CTL_DDI) are backing the IO/PHY functionality, which doesn't need the PG3 power power well. Accordingly fixing up the list of PG3 power domains. v2: Removed "DDI E/F IO"power domain as well [Imre] Cc: Imre Deak <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Anshuman Gupta <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-09drm/i915: move I915_STATE_WARN() and _ON() to intel_display.hJani Nikula1-0/+18
It's for display. Seems like a better fit. Reduce clutter in i915_drv.h. Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/8fefcf69b6dcdb7b9c920aeded35c5f8928b9602.1565271681.git.jani.nikula@intel.com
2019-08-09drm/i915: remove unused dev_priv->no_aux_handshakeJani Nikula1-4/+0
The last user of dev_priv->no_aux_handshake was removed in commit 3cf2efb1a7c6 ("Revert "drm/i915/dp: use VBT provided eDP params if available""). Finally remove the leftovers. Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/f1f0830bb43ddc6857d6a43e51c14b2f0c58c4e0.1565271681.git.jani.nikula@intel.com
2019-08-09Merge tag 'drm-misc-next-2019-08-08' of ↵Dave Airlie3-27/+67
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.4: UAPI Changes: - HDCP: Add a Content protection type property Cross-subsystem Changes: Core Changes: - Continue to rework the include dependencies - fb: Remove the unused drm_gem_fbdev_fb_create function - drm-dp-helper: Make the link rate calculation more tolerant to non-explicitly defined, yet supported, rates - fb-helper: Map DRM client buffer only when required, and instanciate a shadow buffer when the device has a dirty function or says so - connector: Add a helper to link the DDC adapter used by that connector to the userspace - vblank: Switch from DRM_WAIT_ON to wait_event_interruptible_timeout - dma-buf: Fix a stack corruption - ttm: Embed a drm_gem_object struct to make ttm_buffer_object a superclass of GEM, and convert drivers to use it. - hdcp: Improvements to report the content protection type to the userspace Driver Changes: - Remove drm_gem_prime_import/export from being defined in the drivers - Drop DRM_AUTH usage from drivers - Continue to drop drmP.h - Convert drivers to the connector ddc helper - ingenic: Add support for more panel-related cases - komeda: Support for dual-link - lima: Reduce logging - mpag200: Fix the cursor support - panfrost: Export GPU features register to userspace through an ioctl - pl111: Remove the CLD pads wiring support from the DT - rockchip: Rework to use DRM PSR helpers, fix a bug in the VOP_WIN_GET macro - sun4i: Improve support for color encoding and range - tinydrm: Rework SPI support, improve MIPI-DBI support, move to drm/tiny - vkms: Rework of the CRC tracking - bridges: - sii902x: Add support for audio graph card - tc358767: Rework AUX data handling code - ti-sn65dsi86: Add Debugfs and proper DSI mode flags support - panels - Support for GiantPlus GPM940B0, Sharp LQ070Y3DG3B, Ortustech COM37H3M, Novatek NT39016, Sharp LS020B1DD01D, Raydium RM67191, Boe Himax8279d, Sharp LD-D5116Z01B - Conversion of the device tree bindings to the YAML description - jh057n00900: Rework the enable / disable path - fbdev: - ssd1307fb: Support more devices based on that controller Signed-off-by: Dave Airlie <[email protected]> From: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20190808121423.xzpedzkpyecvsiy4@flea
2019-08-08drm/i915/tgl: Fix the read of the DDI that transcoder is attached toJosé Roberto de Souza1-3/+2
On TGL this register do not map directly to port, it was already handled when setting it(TGL_TRANS_DDI_SELECT_PORT()) but not when reading it. To make it consisntent adding a macro for the older gens too. v2: Adding TGL_PORT_TRANS_DDI_SELECT() so all future users can reuse it (Lucas) v3: Missed parentheses arround val (Jose) v4: Renamed TGL_PORT_TRANS_DDI_SELECT to TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT (Lucas) Added TRANS_DDI_FUNC_CTL_VAL_TO_PORT (Lucas) Reviewed-by: Lucas De Marchi <[email protected]> Cc: Lucas De Marchi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-08drm/i915: Get transcoder power domain before reading its registerJosé Roberto de Souza1-0/+8
When getting the pipes attached to encoder if it is not a eDP encoder it iterates over all pipes and read a transcoder register. But it should not read a transcoder register before get its power domain. It was not a issue in gens older than 12 because if it only had port A connected it would be attached to EDP and it would skip all the transcoders readout, if it had more than one port connected, pipe B would cause PG3 to be on and it contains all other transcoders. But on gen 12 there is no EDP transcoder so it is always iterating over all pipes and if only one sink is connected, PG3 is kept off and reading other transcoders registers would cause a unclaimed read warning. So here getting the power domain of the transcoder only if it is enabled, otherwise it is not connected to the DDI. Reviewed-by: Lucas De Marchi <[email protected]> Cc: Lucas De Marchi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-08drm/i915/tgl/dsi: Enable blanking packets during BLLP for video modeVandita Kulkarni1-0/+5
Blanking packet bit will control whether the transcoder allows the link to enter the LP state during BLLP regions (assuming there is enough time), or whether it will keep the link in the HS state with a Blanking Packet Signed-off-by: Vandita Kulkarni <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Uma Shankar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-08drm/i915/tgl: Add mipi dsi support for TGLVandita Kulkarni1-0/+1
Most of the functions and mipi dsi sequence remains same as of ICL for TGL. Hence extending the support to TGL. Signed-off-by: Vandita Kulkarni <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Uma Shankar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-08drm/i915/tgl/dsi: Gate the ddi clocks after pll mappingVandita Kulkarni1-2/+8
For TGL, there is no need to keep DDI clock on till IO enabling for mipi dsi. Signed-off-by: Vandita Kulkarni <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Uma Shankar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-08drm/i915/tgl/dsi: Do not override TA_SUREVandita Kulkarni1-12/+14
Do not override TA_SURE timing parameter to zero for DSI 8X frequency 800MHz or below on TGL. Signed-off-by: Vandita Kulkarni <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Uma Shankar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-08drm/i915/tgl/dsi: Set latency PCS_DW1 for tglVandita Kulkarni1-2/+2
Latency programming remains same as that of ICL and setting latency otimization for PCS_DW1 lanes is same as that of EHL, hence extending it to TGL. Signed-off-by: Vandita Kulkarni <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Uma Shankar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-08drm/i915/tgl/dsi: Program TRANS_VBLANK registerVandita Kulkarni1-0/+9
Program vblank register for mipi dsi in video mode on TGL. Signed-off-by: Vandita Kulkarni <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Uma Shankar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-07drm/i915: abstract display suspend/resume operationsRodrigo Vivi2-25/+72
Increase abstraction of display suspend/resume operations by providing higher level functions, and hiding the details inside intel_display_power.c. v2: Make checkpatch happy: - braces {} are not necessary for single statement blocks v3: Also move hsw/bdw PC8 sequences since they are related to display PM anyways. (Ville) v4: Rebase after a long time, plus Move functions to the new intel_display_power so we can stop exporting platform specific functions as pointed by Jani. v5: Remove unnecessary braces. v6 by Jani: make this purely non-functional cleanup, make functions static Cc: Chris Wilson <[email protected]> Cc: José Roberto de Souza <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-07drm/i915: move property enums to intel_display_types.hJani Nikula1-0/+14
Move the property enums closer to home. Acually make the broadcast macros an enum while at it. Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/589d5449a504ec9742dc1fa8d4871d0d6d0cddca.1565085692.git.jani.nikula@intel.com
2019-08-07drm/i915: rename intel_drv.h to display/intel_display_types.hJani Nikula52-53/+1564
Everything about the file is about display, and mostly about types related to display. Move under display/ as intel_display_types.h to reflect the facts. There's still plenty to clean up, but start off with moving the file where it logically belongs and naming according to contents. v2: fix the include guard name in the renamed file Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-07drm/i915: avoid including intel_drv.h via i915_drv.h->i915_trace.hJani Nikula4-0/+4
Disentangle i915_drv.h from intel_drv.h, which gets included via i915_trace.h. This necessitates including i915_trace.h wherever it's needed. Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/ed82bf259d3b725a1a1a3c3e9d6fb5c08bc4d489.1565085691.git.jani.nikula@intel.com
2019-08-07drm/i915/tc: un-inline intel_tc_port_ref_held()Jani Nikula2-7/+9
Avoid including the intel_drv.h mega header from other header files to make further header cleanup easier. v2: restore the over-eagerly dropped <linux/types.h> (Imre) Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-08-07drm/i915/mst: un-inline intel_dp_mst_encoder_active_links()Jani Nikula2-7/+8
Avoid including the intel_drv.h mega header from other header files to make further header cleanup easier. Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/ae8f7a9514a9e952e1e0dba411aeb42293d1e183.1565085691.git.jani.nikula@intel.com
2019-08-07drm/i915/bw: make intel_atomic_get_bw_state() staticJani Nikula2-15/+14
No need for this function to be accessible outside of intel_bw.c. Avoid including the i915_drv.h mega header from other header files to make further header cleanup easier. Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/6c898ec6511af47c1c5b679e516dc757cd207146.1565085691.git.jani.nikula@intel.com
2019-08-07drm/i915/sprite: un-inline icl_is_hdr_plane()Jani Nikula2-7/+7
Avoid including the i915_drv.h mega header from other header files to make further header cleanup easier. Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/5f998c72018c0f1cc5cdb239327a1281d21f4c0e.1565085691.git.jani.nikula@intel.com
2019-08-07drm/i915: move intel_display.c function declarationsJani Nikula1-0/+171
Move the declarations of functions in intel_display.c to intel_display.h. There is still plenty of cleanup to do in intel_display.[ch], but one step at a time. Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/ebe19d3c508faa82e651ab3c8eb7a0975bfa52b7.1565085691.git.jani.nikula@intel.com
2019-08-06drm/i915: update the hdcp state with ueventRamalingam C1-5/+3
drm function to update the content protection property state and to generate a uevent is invoked from the intel hdcp property work. Hence whenever kernel changes the property state, userspace will be updated with a uevent. v2: state update is moved into drm function [daniel] Signed-off-by: Ramalingam C <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Acked-by: Pekka Paalanen <[email protected]> Acked-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/320965/?series=57232&rev=14
Powered by cgit, Gruvboxed by Blaster4385.