| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2024-04-16 | drm/amdgpu: validate the parameters of bo mapping operations more clearly | xinhui pan | 1 | -26/+46 | |
| Verify the parameters of amdgpu_vm_bo_(map/replace_map/clearing_mappings) in one common place. Fixes: dc54d3d1744d ("drm/amdgpu: implement AMDGPU_VA_OP_CLEAR v2") Cc: [email protected] Reported-by: Vlad Stolyarov <[email protected]> Suggested-by: Christian König <[email protected]> Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amdgpu: add new aca smu callback func parse_error_code() | Yang Wang | 3 | -15/+22 | |
| add new aca smu callback parse_error_code{} to avoid specific asic check in amdgpu_aca.c file Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: 3.2.281 | Aric Cyr | 1 | -1/+1 | |
| This version brings along following fixes: * Expand dmub_cmd operations. * Update DVI configuration. * Modify power sequence. * Enable Z10 flag for IPS. * Multiple code cleanups. Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Add missing replay field | Rodrigo Siqueira | 1 | -0/+2 | |
| Reviewed-by: Leo Li <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Add missing callback for init_watermarks in DCN 301 | Rodrigo Siqueira | 1 | -0/+1 | |
| Reviewed-by: Leo Li <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Update DCN201 link encoder registers | Rodrigo Siqueira | 1 | -1/+13 | |
| Add some missing registers expansion in the dcn201_link_encoder file. Reviewed-by: Leo Li <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Move REG sequence from program ogam to idle before connect | Rodrigo Siqueira | 1 | -6/+4 | |
| Fill ring buffer before offload. Reviewed-by: Leo Li <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Rework dcn10_stream_encoder header | Rodrigo Siqueira | 1 | -7/+3 | |
| This commit remove some unused code and also rename one of the define. Reviewed-by: Leo Li <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Update FMT settings for 4:2:0 | Eric Bernstein | 2 | -1/+10 | |
| [Why] Update FMT_CONTROL settings based on HW spec [How] Update FMT settings for 4:2:0 Reviewed-by: Leo Li <[email protected]> Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amdgpu: increase mes submission timeout | Jonathan Kim | 1 | -1/+1 | |
| MES internally has a timeout allowance of 2 seconds. Increase driver timeout to 3 seconds to be safe. Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Remove unnecessary code | Rodrigo Siqueira | 5 | -30/+0 | |
| This commit groups many parts of the code that are redundant or not used and drops all of them. Reviewed-by: Leo Li <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Update some comments to improve the code readability | Rodrigo Siqueira | 3 | -6/+11 | |
| This commit updates some comments to be more precise and adds another small comment to some other parts to improve the code readability. Reviewed-by: Leo Li <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Replace int with unsigned int | Rodrigo Siqueira | 1 | -1/+1 | |
| Reviewed-by: Leo Li <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Group scl_data together in resource_build_scaling_params | Rodrigo Siqueira | 1 | -3/+2 | |
| Move the scl_data.format to be close to other similar parts. Reviewed-by: Leo Li <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Fix PSR command version passed | Mikita Lipski | 1 | -0/+1 | |
| [why] Driver was passing a wrong command version which to DMCUB which caused the DMCUB to treat it as 0, so it wouldn't support dual eDP and would override the panel index to 0 instead of choosing between 0/1. [how] Use DMUB_CMD_PSR_CONTROL_VERSION_1 instead of PSR_VERSION_1. Reviewed-by: Leo Li <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Improve the log precision | Ethan Bitnun | 1 | -1/+1 | |
| The previous assumption that there will be an optimize_bandwidth call following every prepare_bandwidth call was incorrect and caused small inaccuracies in logging, as some info was only updated in later prepare calls. Reviewed-by: Leo Li <[email protected]> Signed-off-by: Ethan Bitnun <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Adjust headers | Rodrigo Siqueira | 3 | -4/+1 | |
| Update headers by removing two unecessary headers and include a new one. Reviewed-by: Leo Li <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Use dce_version instead of chip_id | Rodrigo Siqueira | 1 | -1/+1 | |
| The chip ID DEVICE_ID_NV_13FE is not meaningful and represents a legacy way of dealing with chip ID. This commit uses dc_version instead of chip_id and also DCN_VERSION_2_01 instead of DEVICE_ID_NV_13FE. Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Leo Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | Revert "drm/amd/display: fix USB-C flag update after enc10 feature init" | Alex Deucher | 2 | -7/+5 | |
| This reverts commit b5abd7f983e14054593dc91d6df2aa5f8cc67652. This change breaks DSC on 4k monitors at 144Hz over USB-C. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3254 Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: Muhammad Ahmed <[email protected]> Cc: Tom Chung <[email protected]> Cc: Charlene Liu <[email protected]> Cc: Hamza Mahfooz <[email protected]> Cc: Harry Wentland <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Expand dmub_cmd operations | Anthony Koo | 1 | -1/+52 | |
| Update dmub_cmd to manipulate SDP control in replay FSM, add command for panel_cntl, expand link rate enum, and increase the reserve byte. Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amdgpu: add missing vbios version from devcoredump | Sunil Khatri | 1 | -4/+5 | |
| Add vbios version in the devcoredump along with formatting the information with proper alignment. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Sunil Khatri <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amdgpu/gfx11: properly handle regGRBM_GFX_CNTL in soft reset | Alex Deucher | 1 | -10/+5 | |
| Need to take the srbm_mutex and while we are here, use the helper function soc21_grbm_select(); Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Rework power sequence and resource allocation logic | Sung Joon Kim | 3 | -45/+5 | |
| Rework part of the modifications made to the power sequence and resource allocation logic. Reviewed-by: Xi (Alex) Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Enable Z10 flag for IPS FSM | Sung Joon Kim | 1 | -2/+2 | |
| [why] IPS FSM requires Z10 flag to be enabled to do save and restore the registers properly. [how] Enable Z10 and use the correct function to determine Z10 capability Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Fix incorrect pointer assignment | Chaitanya Dhere | 1 | -5/+5 | |
| [Why] Pointer initialization and assignment for dml2_options is not done correctly. While this works for some compilers, others give an error. [How] Modify dc_state_create code to correctly initialize the dml2_opt pointer and pass it to dml2_create. Also update the code with correct derefrence operations. Reviewed-by: Aurabindo Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Chaitanya Dhere <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Pass sequential ONO bit to DMCUB boot options | Nicholas Kazlauskas | 3 | -0/+11 | |
| [Why] IPS ono sequence ordering differs based on the ASIC. [How] Detect the ASIC ID revision and set the boot option accordingly. Feed it through the DCN35 DMUB functions. Reviewed-by: Sung joon Kim <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: add support for chroma offset | Samson Tam | 2 | -0/+10 | |
| [Why] Adding support for chroma subsampling offset (cositing) in scaler calculations to adjust reference point where we determine post-scaling chroma value in YUV420 surfaces. [How] Add support for cositing options: NONE, LEFT and TOPLEFT Add debug option force_cositing and set default to TOPLEFT to maintain same behaviour as without offset support. Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Samson Tam <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: limit the code change to ips enabled asic | Charlene Liu | 1 | -1/+6 | |
| Limit the code change for ips enable to reduce the impact for now. Also exit_ips first before dc_power_down to avoid 0x9f. Reviewed-by: Chris Park <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-16 | drm/amd/display: Modify resource allocation logic | Sung Joon Kim | 4 | -3/+48 | |
| To reduce the complexity of pipe resource allocation for different use-cases, now we search for any free pipe sequentially rather than from bottom up. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amd/display: Add a function for checking tmds mode | Chris Park | 1 | -0/+13 | |
| [Why] DVI is TMDS signal like HDMI but without audio. Current signal check does not correctly reflect DVI clock programming. [How] Define a new signal check for TMDS that includes DVI to HDMI TMDS programming. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Chris Park <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amd/display: Modify power sequence | Sung Joon Kim | 5 | -12/+247 | |
| Need to update the power sequence to help prevent potential issues like multi-display or multi-plane. Reviewed-by: Duncan Ma <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amd/display: 3.2.280 | Aric Cyr | 1 | -1/+1 | |
| This version brings along the following: - DCN10 fixes - DCN316 fixes - DML2 fixes - DWB fixes - Expanded FAMS support - Misc code style fixes - ODM fixes - VSC SDP fixes Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amd/display: Reorganize dwb header | Rodrigo Siqueira | 1 | -11/+19 | |
| This commit makes some small adjustments in the dwb header. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amdkfd: Fix memory leak in create_process failure | Felix Kuehling | 1 | -2/+2 | |
| Fix memory leak due to a leaked mmget reference on an error handling code path that is triggered when attempting to create KFD processes while a GPU reset is in progress. Fixes: 0ab2d7532b05 ("drm/amdkfd: prepare per-process debug enable and disable") CC: Xiaogang Chen <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Tested-by: Harish Kasiviswanthan <[email protected]> Reviewed-by: Mukul Joshi <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amd/display: Change DPCD address range | Rodrigo Siqueira | 1 | -1/+1 | |
| Change DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT with DP_PHY_REPEATER_128B132B_RATES. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amd/display: Add fallback configuration for set DRR in DCN10 | Rodrigo Siqueira | 1 | -3/+12 | |
| Set OTG/OPTC parameters to 0 if something goes wrong on DCN10. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amd/display: Add fallback configuration when set DRR | Rodrigo Siqueira | 1 | -2/+9 | |
| Set OTG/OPTC parameter to 0 if failed to set DRR. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amd/display: Update DCN10 resource | Rodrigo Siqueira | 1 | -0/+2 | |
| Update DCN10 to use legacy fast update and ensure that the MPCC count is the same as the pipe_count. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amd/display: Disable P010 Support of DCN 1.0 | Rodrigo Siqueira | 1 | -1/+1 | |
| [WHY] DCN 1.0 is not ready for the P010 support. [HOW] 1. Set the P010 plan_cap of DCN 1.0 to be false. 2. Let the DM do the plan cap initialization of DCN 1.0. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Figo Wang <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amd/display: Update resource capabilities and debug struct for DCN201 | Rodrigo Siqueira | 1 | -1/+3 | |
| Some of the resource capabilities for DCN201 and the debug default option are outdated. This commit just set some of the missing configurations for DCN201. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amd/display: Drop legacy code | Rodrigo Siqueira | 4 | -53/+1 | |
| This commit removes code that are not used by display anymore. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amd/display: Adjust some includes used by display | Rodrigo Siqueira | 7 | -7/+1 | |
| Some of the includes used in the DC can be removed and others need to be update. This commit adjusts some of those headers in the display code. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amd/display: Add comments to improve the code readability | Rodrigo Siqueira | 3 | -1/+3 | |
| This commit just introduce some basic comments that helps to understand the overall behavior of some structs. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amdgpu: remove invalid resource->start check v2 | Christian König | 1 | -4/+0 | |
| The majority of those where removed in the commit aed01a68047b ("drm/amdgpu: Remove TTM resource->start visible VRAM condition v2") But this one was missed because it's working on the resource and not the BO. Since we also no longer use a fake start address for visible BOs this will now trigger invalid mapping errors. v2: also remove the unused variable Signed-off-by: Christian König <[email protected]> Fixes: aed01a68047b ("drm/amdgpu: Remove TTM resource->start visible VRAM condition v2") CC: [email protected] Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amdgpu/sdma6: set sdma hang watchdog | Jack Xiao | 1 | -0/+7 | |
| Set SDMAx_WATCHDOG_CNTL.QUEUE_HANG_COUNT registers to improve SDMA reliability. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | drm/amd/amdgpu: Update PF2VF Header | Luqmaan Irshad | 1 | -1/+3 | |
| Adding a new field for GPU Capacity to align the header with the host. Signed-off-by: Luqmaan Irshad <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-12 | amdkfd: use calloc instead of kzalloc to avoid integer overflow | Dave Airlie | 1 | -2/+2 | |
| This uses calloc instead of doing the multiplication which might overflow. Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]> | |||||
| 2024-04-10 | drm/amdgpu: differentiate external rev id for gfx 11.5.0 | Yifan Zhang | 1 | -1/+4 | |
| This patch to differentiate external rev id for gfx 11.5.0. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] | |||||
| 2024-04-09 | drm/amd/display: Adjust dprefclk by down spread percentage. | Zhongwei | 2 | -4/+54 | |
| [Why] OLED panels show no display for large vtotal timings. [How] Check if ss is enabled and read from lut for spread spectrum percentage. Adjust dprefclk as required. DP_DTO adjustment is for edp only. Cc: [email protected] Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Zhongwei <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||
| 2024-04-09 | drm/amd/display: Set VSC SDP Colorimetry same way for MST and SST | Harry Wentland | 1 | -9/+3 | |
| The previous check for the is_vsc_sdp_colorimetry_supported flag for MST sink signals did nothing. Simplify the code and use the same check for MST and SST. Cc: [email protected] Reviewed-by: Agustin Gutierrez <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]> | |||||