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2022-11-15drm/amdgpu: move non-DC vblank handling out of irq codeAlex Deucher8-57/+95
Move it into the DCE code for each generation. This avoids confusion with the different display paths. v2: no need for a hotplug worker for vkms Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-15drm/amdgpu: rework SR-IOV virtual display handlingAlex Deucher4-7/+32
virtual display is enabled unconditionally in SR-IOV, but without specifying the virtual_display module, the number of crtcs defaults to 0. Set a single display by default for SR-IOV if the virtual_display parameter is not set. Only enable virtual display by default on SR-IOV on asics which actually have display hardware. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-15drm/amdgpu: use proper DC check in amdgpu_display_supported_domains()Alex Deucher1-1/+1
amdgpu_device_asic_has_dc_support() just checks the asic itself. amdgpu_device_has_dc_support() is a runtime check which not only checks the asic, but also other things in the driver like whether virtual display is enabled. We want the latter here. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-15drm/amdgpu: Remove programming GCMC_VM_FB_LOCATION* on gfxhub_v3_0_3 in VFYifan Zha1-12/+0
[Why] GCMC_VM related registers should be programmed by PSP on host side. L1 and RLCG will block these regisers on VF. [How] Remove programming GCMC_VM_FB_LOCATION_BASE/TOP on gfxhub_v3_0_3 under SRIOV VF. Signed-off-by: Yifan Zha <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-15drm/amdgpu: Stop clearing kiq position during unloadYuBiao Wang2-10/+10
Do not clear kiq position in RLC_CP_SCHEDULER so that CP could perform IDLE-SAVE after VF fini. CPG also needs to be active in save command. v2: drop unused variable (Alex) Signed-off-by: YuBiao Wang <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-10drm/amdgpu: Fix memory leak in amdgpu_cs_pass1Dong Chenchen1-2/+4
When p->gang_size equals 0, amdgpu_cs_pass1() will return directly without freeing chunk_array, which will cause a memory leak issue, this patch fixes it. Fixes: 4624459c84d7 ("drm/amdgpu: add gang submit frontend v6") Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Dong Chenchen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-10drm/amd/display: delete the duplicate .set_odm_bypass initialization in ↵Liu Jian1-1/+0
dcn314_tg_funcs Fix below sparse warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_optc.c:244:18: warning: Initializer entry defined twice drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_optc.c:257:18: also defined here Fixes: 5ade1b951dec ("drm/amd/display: Add OTG/ODM functions") Signed-off-by: Liu Jian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-10drm/amdgpu: Replace one-element array with flex-array memberPaulo Miguel Almeida2-11/+10
One-element arrays are deprecated, and we are replacing them with flexible array members instead. So, replace one-element array with flexible-array member in structs _ATOM_CONNECTOR_DEVICE_TAG_RECORD, _ATOM_OBJECT_GPIO_CNTL_RECORD, _ATOM_BRACKET_LAYOUT_RECORD, _ATOM_BRACKET_LAYOUT_RECORD, _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3, _ATOM_FUSION_SYSTEM_INFO_V3, _ATOM_I2C_DATA_RECORD, _ATOM_I2C_DEVICE_SETUP_INFO, _ATOM_ASIC_MVDD_INFO and refactor the rest of the code accordingly. While at it, removed a redundant casting. Important to mention is that doing a build before/after this patch results in no binary output differences. This helps with the ongoing efforts to tighten the FORTIFY_SOURCE routines on memcpy() and help us make progress towards globally enabling -fstrict-flex-arrays=3 [1]. Link: https://github.com/KSPP/linux/issues/79 Link: https://github.com/KSPP/linux/issues/238 Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101836 [1] Signed-off-by: Paulo Miguel Almeida <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-10drm/amdgpu: Use drm_mode_init() for on-stack modesVille Syrjälä1-1/+2
Initialize on-stack modes with drm_mode_init() to guarantee no stack garbage in the list head, or that we aren't copying over another mode's list head. Based on the following cocci script, with manual fixups: @decl@ identifier M; expression E; @@ - struct drm_display_mode M = E; + struct drm_display_mode M; @@ identifier decl.M; expression decl.E; statement S, S1; @@ struct drm_display_mode M; ... when != S + drm_mode_init(&M, &E); + S1 @@ expression decl.E; @@ - &*E + E Cc: Harry Wentland <[email protected]> Cc: Leo Li <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-10drm/amdgpu: Ignore stop rlc on SRIOV environment.Gavin Wan1-1/+1
For SRIOV, the guest driver should not do stop rlc. The host handles programing RLC. On SRIOV, the stop rlc will be hang (RLC related registers are blocked by policy) when the RLCG interface is not enabled. Reviewed-by: Yang Wang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Gavin Wan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-10drm/amdgpu: add vram reservation based on vram_usagebyfirmware_v2_2Tong Liu014-32/+191
Move TMR region from top of FB to 2MB for FFBM, so we need to reserve TMR region firstly to make sure TMR can be allocated at 2MB Signed-off-by: Tong Liu01 <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-10drm/amdgpu: remove the check of init status in psp_ras_initializeTao Zhou1-5/+3
The initialized status indicates RAS TA is loaded, but in some cases (such as RAS fatal error) RAS TA could be destroyed although it's not unloaded. Hence we load RAS TA unconditionally here. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Candice Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-10drm/amd/pm: skip disabling all smu features on smu_v13_0_10 in suspendKenneth Feng1-0/+1
skip disabling all smu features on smu_v13_0_10 in suspend Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-10drm/amdgpu: force read discovery file if set discovery=2Yifan Zhang1-2/+7
If discovery is set to 2 in module parameters explicitly, the intention is to use the discovery file in FW rather than the one in BIOS, usually because the latter is incorrect. This patch to force read discovery file if set discovery=2. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-10drm: Move radeon and amdgpu Kconfig options into their directoriesAndrew Davis1-0/+29
Most Kconfig options to enable a driver are in the Kconfig file inside the relevant directory, move these two to the same. Signed-off-by: Andrew Davis <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amdgpu: Set MTYPE in PTE based on BO flagsFelix Kuehling5-60/+96
The same BO may need different MTYPEs and SNOOP flags in PTEs depending on its current location relative to the mapping GPU. Setting MTYPEs from clients ahead of time is not practical for coherent memory sharing. Instead determine the correct MTYPE for the desired coherence model and current BO location when updating the page tables. To maintain backwards compatibility with MTYPE-selection in AMDGPU_VA_OP_MAP, the coherence-model-based MTYPE selection is only applied if it chooses an MTYPE other than MTYPE_NC (the default). Add two AMDGPU_GEM_CREATE_... flags to indicate the coherence model. The default if no flag is specified is non-coherent (i.e. coarse-grained coherent at dispatch boundaries). Update amdgpu_amdkfd_gpuvm.c to use this new method to choose the correct MTYPE depending on the current memory location. v2: * check that bo is not NULL (e.g. PRT mappings) * Fix missing ~ bitmask in gmc_v11_0.c v3: * squash in "drm/amdgpu: Inherit coherence flags on dmabuf import" Suggested-by: Christian König <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: only fill dirty rectangles when PSR is enabledHamza Mahfooz1-3/+4
Currently, we are calling fill_dc_dirty_rects() even if PSR isn't supported by the relevant link in amdgpu_dm_commit_planes(), this is undesirable especially because when drm.debug is enabled we are printing messages in fill_dc_dirty_rects() that are only useful for debugging PSR (and confusing otherwise). So, we can instead limit the filling of dirty rectangles to only when PSR is enabled. Reviewed-by: Leo Li <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Have risk for memory exhaustionLongJun Tang8-0/+8
In dcn*_clock_source_create when dcn*_clk_src_construct fails allocated clk_src needs release. A local attack could use this to cause memory exhaustion. Signed-off-by: LongJun Tang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amdgpu: Replace 1-element array with flexible-array memberPaulo Miguel Almeida2-12/+19
One-element arrays are deprecated, and we are replacing them with flexible array members instead. So, replace one-element array with flexible-array member in structs _ATOM_GPIO_PIN_ASSIGNMENT, _ATOM_DISPLAY_OBJECT_PATH, _ATOM_DISPLAY_OBJECT_PATH_TABLE, _ATOM_OBJECT_TABLE and refactor the rest of the code accordingly. Important to mention is that doing a build before/after this patch results in no functional binary output differences. This helps with the ongoing efforts to tighten the FORTIFY_SOURCE routines on memcpy() and help us make progress towards globally enabling -fstrict-flex-arrays=3 [1]. Link: https://github.com/KSPP/linux/issues/79 Link: https://github.com/KSPP/linux/issues/238 Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101836 [1] Signed-off-by: Paulo Miguel Almeida <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amdgpu: complete gfxoff allow signal during suspend without delayHarsh Jain1-3/+7
change guarantees that gfxoff is allowed before moving further in s2idle sequence to add more reliablity about gfxoff in amdgpu IP's suspend flow Signed-off-by: Harsh Jain <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amdgpu: Decouple RAS EEPROM addresses from chipsLuben Tuikov1-12/+11
Abstract RAS I2C EEPROM addresses from chip names, and set their macro definition names to the address they set, not the chip they attach to. Since most chips either use I2C EEPROM address 0 or 40000h for the RAS table start offset, this leaves us with only two macro definitions as opposed to five, and removes the redundancy of four. Cc: Candice Li <[email protected]> Cc: Tao Zhou <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Kent Russell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amdgpu: Remove redundant I2C EEPROM addressLuben Tuikov2-3/+23
Remove redundant EEPROM_I2C_MADDR_54H address, since we already have it represented (ARCTURUS), and since we don't include the I2C device type identifier in EEPROM memory addresses, i.e. that high up in the device abstraction--we only use EEPROM memory addresses, as memory is continuously represented by EEPROM device(s) on the I2C bus. Add a comment describing what these memory addresses are, how they come about and how they're usually extracted from the device address byte. Cc: Candice Li <[email protected]> Cc: Tao Zhou <[email protected]> Cc: Alex Deucher <[email protected]> Fixes: c9bdc6c3cf39df ("drm/amdgpu: Add EEPROM I2C address support for ip discovery") Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amdkfd: Make kfd_fill_cache_non_crat_info() as staticMa Jun1-1/+1
kfd_fill_cache_non_crat_info() is only used in kfd_topology.c, so make it as static. Signed-off-by: Ma Jun <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reported-by: kernel test robot <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/pm: enable mode1 reset on smu_v13_0_10Kenneth Feng5-2/+77
enable mode1 reset and prioritize debug port on smu_v13_0_10 as a more reliable message processing v2 - move mode1 reset callback to smu_v13_0_0_ppt.c Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Yang Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amdkfd: Fix the memory overrunMa Jun1-1/+1
Fix the memory overrun issue caused by wrong array size. Signed-off-by: Ma Jun <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reported-by: coverity-bot <[email protected]> Addresses-Coverity-ID: 1527133 ("Memory - corruptions") Fixes: c0cc999f3c32e6 ("drm/amdkfd: Fix the warning of array-index-out-of-bounds") Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amdgpu: disable BACO on special BEIGE_GOBY cardGuchun Chen1-1/+3
Still avoid intermittent failure. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amdgpu: Drop eviction lock when allocating PT BOPhilip Yang3-26/+28
Re-take the eviction lock immediately again after the allocation is completed, to fix circular locking warning with drm_buddy allocator. Move amdgpu_vm_eviction_lock/unlock/trylock to amdgpu_vm.h as they are called from multiple files. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amdgpu: Unlock bo_list_mutex after error handlingPhilip Yang1-0/+1
Get below kernel WARNING backtrace when pressing ctrl-C to kill kfdtest application. If amdgpu_cs_parser_bos returns error after taking bo_list_mutex, as caller amdgpu_cs_ioctl will not unlock bo_list_mutex, this generates the kernel WARNING. Add unlock bo_list_mutex after amdgpu_cs_parser_bos error handling to cleanup bo_list userptr bo. WARNING: kfdtest/2930 still has locks held! 1 lock held by kfdtest/2930: (&list->bo_list_mutex){+.+.}-{3:3}, at: amdgpu_cs_ioctl+0xce5/0x1f10 [amdgpu] stack backtrace: dump_stack_lvl+0x44/0x57 get_signal+0x79f/0xd00 arch_do_signal_or_restart+0x36/0x7b0 exit_to_user_mode_prepare+0xfd/0x1b0 syscall_exit_to_user_mode+0x19/0x40 do_syscall_64+0x40/0x80 Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: 3.2.211Aric Cyr1-1/+1
DC version 3.2.211 brings along the following fixes: - Wait for VBLANK during pipe programming - Adding HDMI SCDC DEVICE_ID define - Cursor update refactor: PSR-SU support condition - Update 709 gamma to 2.222 as stated in the standerd - Consider dp cable id only when data is non zero - Waiting for 1 frame to fix the flash issue on PSR1 - Update SR watermarks for DCN314 - Allow tuning DCN314 bounding box - Zeromem mypipe heap struct before using it - Use min transition for SubVP into MPO - Disable phantom OTG after enable for plane disable - Disable DRR actions during state commit - Fix fallback issues for DP LL 1.4a tests - Fix FCLK deviation and tool compile issues - Fix reg timeout in enc314_enable_fifo - Fix gpio port mapping issue - Only update link settings after successful MST link train - Enforce minimum prefetch time for low memclk on DCN32 - Set correct EOTF and Gamut flag in VRR info - Add margin for max vblank time for SubVP + DRR - Populate DP2.0 output type for DML pipe Acked-by: Alan Liu <[email protected]> Reviewed-by: Alan Liu <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09Revert "drm/amdgpu: Revert "drm/amdgpu: getting fan speed pwm for vega10 ↵Asher Song1-13/+12
properly"" This reverts commit 4545ae2ed3f2f7c3f615a53399c9c8460ee5bca7. The origin patch "drm/amdgpu: getting fan speed pwm for vega10 properly" works fine. Test failure is caused by test case self. Signed-off-by: Asher Song <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amdgpu: Fix the kerneldoc descriptionRajneesh Bhardwaj1-2/+3
amdgpu_ttm_tt_set_userptr() is also called by the KFD as part of initializing the user pages for userptr BOs and also while initializing the GPUVM for a KFD process so update the function description. Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Rajneesh Bhardwaj <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Populate DP2.0 output type for DML pipeGeorge Shen1-0/+2
[Why] DCN3.2 DML logic uses a new output type for DP2.0, which will enable validation to pass for higher BW timings that require DP2.0 link rates. [How] Populate the DML pipe with DP2.0 output type if the signal type of the pipe_ctx is 128b/132b. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Add margin for max vblank time for SubVP + DRRAlvin Lee4-2/+13
[Description] - Incorporate FW delays as port of max VTOTAL calculated for SubVP + DRR cases (since it is part of the microschedule). - Also add margin for the max VTOTAL possible for SubVP + DRR cases. - Due to rounding errors in FW (integer arithmetic), the microschedule calculation can get pushed to the next frame (incorrectly) in cases where we use the max VTOTAL possible to complete the MCLK switch. - When the rounding error occurs, we are only off by 1-2 lines, use 40us margin which is working consistently. Reviewed-by: Jun Lei <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Set correct EOTF and Gamut flag in VRR infoMike Hsieh1-4/+4
[Why] FreeSync always use G2.2 EOTF and Native gamut [How] Set EOTF and Gamut flags accordingly Reviewed-by: Krunoslav Kovac <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Mike Hsieh <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Enforce minimum prefetch time for low memclk on DCN32Dillon Varone10-2/+26
[WHY?] Data return times when using lowest memclk can be <= 60us, which can cause underflow on high bandwidth displays with a workload. [HOW?] Enforce a minimum prefetch time during validation for low memclk modes. Reviewed-by: Jun Lei <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Only update link settings after successful MST link trainMichael Strauss4-2/+22
[WHY] Currently driver reduces verified link caps on DPIA devices if a link is trained at a link rate below the max rate verified during link detection. This blocks high bandwidth modes after setting a low bandwidth mode. [HOW] Only update link rate after a successful link train if link is MST. Reviewed-by: Mustapha Ghaddar <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Fix gpio port mapping issueSteve Su2-3/+20
[Why] 1. Port of gpio has different mapping. [How] 1. Add a dummy entry in mapping table. 2. Fix incorrect mask bit field access. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Steve Su <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Fix reg timeout in enc314_enable_fifoNicholas Kazlauskas1-6/+18
[Why] The link enablement sequence can end up resetting the encoder while the PHY symclk isn't yet on. This means that waiting for symclk on will timeout, along with the reset bit never asserting high. This causes unnecessary delay when enabling the link and produces a warning affecting multiple IGT tests. [How] Don't wait for the symclk to be on here because firmware already does. Don't wait for reset if we know the symclk isn't on. Split the reset into a helper function that checks the bit and decides whether or not a delay is sufficient. Reviewed-by: Roman Li <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Fix FCLK deviation and tool compile issuesChaitanya Dhere2-2/+2
[Why] Recent backports from open source do not have header inclusion pattern that is consistent with inclusion style in the rest of the file. This breaks the internal tool builds as well. A recent commit erronously modified the original DML formula for calculating ActiveClockChangeLatencyHidingY. This resulted in a FCLK deviation from the golden values. [How] Change the way in which display_mode_vba.h is included so that it is consistent with the inclusion style in rest of the file which also fixes the tool build. Restore the DML formula to its original state to fix the FCLK deviation. Reviewed-by: Aurabindo Pillai <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Chaitanya Dhere <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Fix fallback issues for DP LL 1.4a testsMustapha Ghaddar3-8/+30
[WHY] Unlike DP or USBC, the USB4 link does not get its own encoder and has to share therefore verify_caps is skipped. [HOW] Fix the fallback logic for automated tests and take that into consideration for LT and LS. Reviewed-by: Jun Lei <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Mustapha Ghaddar <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Disable DRR actions during state commitWesley Chalmers1-3/+0
[WHY] Committing a state while performing DRR actions can cause underflow. [HOW] Disabled features performing DRR actions during state commit. Need to follow-up on why DRR actions affect state commit. Reviewed-by: Jun Lei <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Wesley Chalmers <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Disable phantom OTG after enable for plane disableAlvin Lee3-1/+22
[Description] - Need to disable phantom OTG after it's enabled in order to restore it to it's original state. - If it's enabled and then an MCLK switch comes in we may not prefetch the correct data since the phantom OTG could already be in the middle of the frame. Reviewed-by: Jun Lei <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Use min transition for SubVP into MPOAlvin Lee1-23/+20
[Description] - For SubVP transitioning into MPO, we want to use a minimal transition to prevent transient underflow - Transitioning a phantom pipe directly into a "real" pipe can result in underflow due to the HUBP still having it's "phantom" programming when HUBP is unblanked (have to wait for next VUPDATE of the new OTG) - Also ensure subvp pipe lock is acquired early enough for programming in dc_commit_state_no_check - When disabling phantom planes, enable phantom OTG first so the disable gets the double buffer update Reviewed-by: Aric Cyr <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Zeromem mypipe heap struct before using itAurabindo Pillai1-0/+1
[Why&How] Bug was caused when moving variable from stack to heap because it was reusable and garbage was left over, so we need to zero mem. Reviewed-by: Martin Leung <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Martin Leung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Allow tuning DCN314 bounding boxNicholas Kazlauskas1-5/+2
[Why] We're missing the helpers from dcn20 that would allow overriding these with DC debug options. [How] Use dcn20_patch_bounding_box to support overriding all the relevant values. Reviewed-by: Jun Lei <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Update SR watermarks for DCN314Nicholas Kazlauskas2-18/+18
[Why & How] New values requested by hardware after fine-tuning. Update for all memory types. Reviewed-by: Jun Lei <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Waiting for 1 frame to fix the flash issue on PSR1Ryan Lin2-1/+10
[Why] Needs more frames waiting before the PSR_Exit sending for the specific TCON. [How] Add relock_delay_frame_cnt to control how many frames waiting are needed before the PSR_Exit sending. The default value is 0. The Driver side can set this variable for specific TCONs. Reviewed-by: Robin Chen <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Ryan Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Consider dp cable id only when data is non zeroWenjing Liu1-4/+18
Cable ID is a DP2 feature to identify max certified link rate that a cable can carry. The cable identification method requires both cable and display hardware support. Since the specs comes late, it is anticipated that the first round of DP2 cables and displays may not be fully compatible to reliably return cable ID data. Therefore the decision of our cable id policy is that if the cable can return non zero cable id data, we will take cable's link rate capability into account. However if we get zero data, the cable link rate capability is considered inconclusive. In this case, we will not take cable's capability into account to avoid of over limiting hardware capability from users. The max overall link rate capability is still determined after actual dp pre-training. Cable id is considered as an auxiliary method of determining max link bandwidth capability. Reviewed-by: George Shen <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Update 709 gamma to 2.222 as stated in the standerdNawwar Ali1-1/+1
[WHY] Previously driver use gamma 2.2 for 709 color space, but the standard is to use gamma of 2.222 [HOW] Change it gamma to 2.222 Reviewed-by: Krunoslav Kovac <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Nawwar Ali <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amd/display: Cursor update refactor: PSR-SU support conditionMax Tseng1-0/+48
[Why] PSR-SU requires extra conditions while cursor update. Reviewed-by: Robin Chen <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Max Tseng <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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