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Hook up the amdgpu thermal control callbacks for powerplay.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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This adds the interface needed to expose powerplay fan control to sysfs
via hwmon.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Implement thermal and fan control for tonga.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Add thermal handling to the event manager.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Thermal controller interface.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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submodule.
Redefine interrupt callback function in accordance with cgs.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Add the interface for fan and thermal control.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Implement clock and power gating support for tonga. On Tonga
this is handles by the SMU rather than direct register settings
in the driver.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Add callbacks interface for clock and powergating.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Interface for clock and power gating handling.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Implement displaygap programming for tonga. This is
required for properly mclk switching.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Add support for display configuration changes to the event manager.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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This allows the eventmgr to properly update the displaygap on
certain power events.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Displaygap support is required for proper mclk switching.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Switch over to handling in the powerplay module.
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Eric Huang <[email protected]>
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This option can be used to enable the new powerplay implementation,
and it is disabled by default.
Signed-off-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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This enabled DPM support for Fiji. DPM is dynamic
clock and voltage scaling.
v2: rename fiji_hwmgr_early_init to fiji_hwmgr_init
v3: (agd) fold in endian fix, additional function addition
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Eric Huang <[email protected]>
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Add support for the SMU manager for Fiji. This handles the
firmware loading for other IP blocks (GFX, SDMA, etc.).
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Eric Huang <[email protected]>
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Add some new functions to support Fiji. Split out
from the previous patch.
Reviewed-by: Jammy Zhou <[email protected]>
Signed-off-by: Eric Huang <[email protected]>
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New headers for Fiji.
Reviewed-by: Jammy Zhou <[email protected]>
Signed-off-by: Eric Huang <[email protected]>
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This implements DPM for tonga. DPM handles dynamic
clock and voltage scaling.
v2: merge all the patches related with tonga dpm
v3: merge dpm force level fix, cgs display fix, spelling fix
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Signed-off-by: yanyang1 <[email protected]>
Signed-off-by: Rex Zhu <[email protected]>
Signed-off-by: Eric Huang <[email protected]>
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The SMU manager handles firmware loading for other IP
blocks (GFX, SDMA, etc.). This implements it for Tonga.
v3: delete peci sub-module
v2: use cgs interface directly
Signed-off-by: Young Yang <[email protected]>
Signed-off-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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These headers provide the SMU interface used by the driver.
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: yanyang1 <[email protected]>
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Move smu7.h, smu7_discrete.h and smu7_fusion.h from amdgpu to powerplay.
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: yanyang1 <[email protected]>
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Add ixSWRST_COMMAND_1 in bif_5_0_d.h. Required by
new powerplay code for tonga and fiji.
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: yanyang1 <[email protected]>
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This is the common interface for interacting with the powerplay
module.
v2: squash in fixes
Signed-off-by: Rex Zhu <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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The event manager handles power related driver events.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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This adds clock and powergating support for CZ.
v2: squash in fixes
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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This patch enables basic DPM support for Carrizo.
DPM handles dynamic clock and voltage scaling.
v3: delete peci sub-module
v2: use cgs interface directly
correct define SMU_EnabledFeatureScoreboard_SclkDpmOn
Signed-off-by: Rex Zhu <[email protected]>
Signed-off-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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This implements the SMU firmware manager interface for CZ.
Some header files are moved from amdgpu folder to powerplay as well.
v3: delete peci sub-module.
v2: use cgs interface directly
add load_mec_firmware function
Signed-off-by: Rex Zhu <[email protected]>
Signed-off-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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The hwmgr handles all hardware related calls, including clock/power
gating control, DPM, read and parse PPTable, etc.
v5: squash in fixes
v4: implement acpi's atcs function use cgs interface
v3: fix code style error and add big-endian mode support.
v2: use cgs interface directly in hwmgr sub-module
Signed-off-by: Rex Zhu <[email protected]>
Signed-off-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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The SMUMGR is one sub-component of powerplay for SMU firmware support.
The SMU handles firmware loading for other IP blocks (GFX, SDMA, etc.)
on VI parts. The adds the core powerplay infrastructure to handle that.
v3: direct use printk in powerplay module.
v2: direct use cgs_read/write_register functions in smu-modules
Signed-off-by: Rex Zhu <[email protected]>
Signed-off-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Update amdgpu to deal with the new powerplay module properly.
v2: squash in fixes
v3: squash in Rex's power state reporting fix
Signed-off-by: Rex Zhu <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Powerplay will use a different interface once it's integrated. These
legacy pathes will be removed once powerplay is enabled by default.
Signed-off-by: Rex Zhu <[email protected]>
Signed-off-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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amdgpu_pp_ip_funcs is introduced to handle the two code paths,
the legacy one and the new powerplay implementation.
CONFIG_DRM_AMD_POWERPLAY kernel configuration option is
introduced for the powerplay component.
v4: squash in fixes
v3: register debugfs file when powerplay module enable
v2: add amdgpu_ucode_init_bo in hw init when amdgpu_powerplay enable.
Signed-off-by: Rex Zhu <[email protected]>
Signed-off-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Add new CGS interfaces to query display info across modules.
This is nedded by the powerplay module for synchronizing with
the display module.
v2: (agd): fold in refresh rate fix, rebase
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Add a query to get the bus number and function of the
device.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
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Add a new driver internal interface for accessing ACPI
methods. These will be used by various new components
including powerplay.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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This will be shared with the new powerplay module.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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These will be shared with the new powerplay module.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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rename amdgpu_pm_state_type to amd_pm_state_type
Signed-off-by: Rex Zhu <[email protected]>
Acked-by: Jammy Zhou <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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eaddr is sometimes treated as the last address inside the address
range, and sometimes as the first address outside the range. This
was resulting in errors when a test filled up the entire address
space. Make it consistent to always be the last address within the
range.
Signed-off-by: Felix.Kuehling <[email protected]>
Reviewed-by: Christian König <[email protected]>
Cc: [email protected]
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Need to properly handle the max link rate in the dpcd.
This prevents some cases where 5.4 Ghz is selected when
it shouldn't be.
v2: simplify logic, add array bounds check
Reviewed-by: Tom St Denis <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This avoids allocating it on the fly.
v2: fix grammar in comment
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Chunming Zhou <[email protected]>
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This way we avoid the extra allocation for the page directory entry.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Chunming Zhou <[email protected]>
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They share the reservation object with the page directory anyway.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Chunming Zhou <[email protected]>
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Signed-off-by: Chunming Zhou <[email protected]>
Reviewed-by: Christian König <[email protected]>
CC: [email protected]
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In some cases the amount of vram may be less than the BAR size,
if so, limit visible vram to the amount of actual vram, not the
BAR size.
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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