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path: root/drivers/gpu/drm/amd
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2018-05-17drm/amdgpu/sdma4: Add clockgating support for vega20Feifei Xu1-0/+1
Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/sdma4: Add vega20 golden settings (v3)Feifei Xu1-0/+27
v2: squash in updates (Alex) v3: squash in more updates (Alex) Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/sdma4: Specify vega20 firmwareFeifei Xu1-0/+5
Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/mmhub: Add clockgating support for vega20Feifei Xu1-0/+1
Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/gmc9: Add vega20 supportFeifei Xu1-0/+3
Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/virtual_dce: Add vega20 supportFeifei Xu1-0/+1
Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu: Specify vega20 vce firmwareFeifei Xu1-0/+5
Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu: Specify vega20 uvd firmwareFeifei Xu1-0/+5
Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu: Add vega20 ucode loading methodFeifei Xu1-0/+1
The same as vega10. Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/psp: Add initial psp support for vega20Feifei Xu2-0/+4
The same as vega10 for now. Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/powerplay: Add initial vega20 support v2Feifei Xu1-0/+1
Initial powerplay support the same as vega10 for now. Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu: Add smu firmware support for vega20Feifei Xu2-0/+4
Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu: set asic family for vega20.Feifei Xu1-0/+1
Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu: Add gpu_info firmware for vega20. (v2)Feifei Xu1-0/+1
vega20_gpu_info firmware stores gpu configuration for vega20. v2: drop gpu info firmware for vega20 Squash of: drm/amdgpu: Add gpu_info firmware for vega20. drm/amdgpu: drop gpu_info firmware for vega20 Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu: Add vega20 to asic_type enum.Feifei Xu1-0/+1
Add vega20 to amd_asic_type enum and amdgpu_asic_name[]. Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amd/include/vg20: adjust VCE_BASE to reuse vce 4.0 header filesJames Zhu1-1/+2
Vega20 uses vce 4.1 engine, all the registers have the same absolute offset with vce 4.0. By adjusting vega20 VCE_BASE, vce 4.1 can reuse vce 4.0 header files. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amd: Add vega20_ip_offset.h headerfile for vega20. (v2)Feifei Xu1-0/+1050
This headerfile contains vega20's ip base addresses. v2: squash in MP1_BASE fix Acked-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu: Fix hardcoded base offset of vram pagesFeifei Xu1-4/+1
In gmc_v9_0_vram_gtt_location(),the vram_base_offset is hardcoded to 0 in dGPU. Fix it by reading mmMC_VM_FB_OFFSET or return zfb_phys_addr if ZFB is enabled. Signed-off-by: Feifei Xu <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu: Drop the unused header files in soc15.c.Feifei Xu1-2/+0
Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amd/powerplay: add a framework for perfroming pre displayEvan Quan4-0/+14
configuration change settings Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amd/powerplay: new framework to honour DAL clock limitsEvan Quan4-0/+20
This is needed for vega12 and vega20 which do not support legacy powerstate. With this new framework, the DAL clocks limits can also be honored on these asics. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/gfx9: Update golden setting for gfx9_0.Feifei Xu1-12/+5
Update golden_settings_gc_9_0[]. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu: include pagemap.h for release_pages()Stephen Rothwell1-0/+1
Fixes: 5ae0283e831a ("drm/amdgpu: Add userptr support for KFD" Cc: Felix Kuehling <[email protected]> Cc: Oded Gabbay <[email protected]> Signed-off-by: Stephen Rothwell <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2018-05-16Merge branch 'drm-next-4.18' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie230-4441/+14177
into drm-next Main changes for 4.18. I'd like to do a separate pull for vega20 later this week or next. Highlights: - Reserve pre-OS scanout buffer during init for seemless transition from console to driver - VEGAM support - Improved GPU scheduler documentation - Initial gfxoff support for raven - SR-IOV fixes - Default to non-AGP on PowerPC for radeon - Fine grained clock voltage control for vega10 - Power profiles for vega10 - Further clean up of powerplay/driver interface - Underlay fixes - Display link bw updates - Gamma fixes - Scatter/Gather display support on CZ/ST - Misc bug fixes and clean ups [airlied: fixup v3d vs scheduler API change] Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Dave Airlie <[email protected]>
2018-05-15drm/scheduler: remove unused parameterNayan Deshmukh8-9/+9
this patch also effect the amdgpu and etnaviv drivers which use the function drm_sched_entity_init Signed-off-by: Nayan Deshmukh <[email protected]> Suggested-by: Christian König <[email protected]> Acked-by: Lucas Stach <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amdgpu: print the BO flags in the gem debugfs entryChristian König1-0/+15
Quite useful to know. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amdgpu: drop printing the BO offset in the gem debugfs (v2)Christian König1-5/+0
It is meaningless anyway. v2: remove unused variable (Alex) Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amdgpu: Add support to change mtype for 2nd part of gart BOs on GFX9Yong Zhao2-12/+47
This change prepares for a workaround in amdkfd for a GFX9 HW bug. It requires the control stack memory of compute queues, which is allocated from the second page of MQD gart BOs, to have mtype NC, rather than the default UC. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/powerplay: Add notify PWE function to SMU10Mikita Lipski2-0/+9
Functionality to message smc to enable pwe after gpu suspense. It is used in case when display resumes from S3 and wants to start audio driver by enabling pwe. Signed-off-by: Mikita Lipski <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/display: remove need of modeset flag for overlay planes (V2)Shirish S1-3/+5
This patch is in continuation to the "843e3c7 drm/amd/display: defer modeset check in dm_update_planes_state" where we started to eliminate the dependency on DRM_MODE_ATOMIC_ALLOW_MODESET to be set by the user space, which as such is not mandatory. After deferring, this patch eliminates the dependency on the flag for overlay planes. This has to be done in stages as its a pretty complex and requires thorough testing before we free primary planes as well from dependency on modeset flag. V2: Simplified the plane type check. Signed-off-by: Shirish S <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amdgpu: fix null pointer for bo unmap trace functionJunwei Zhang1-1/+1
fix crash in trace. Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amdgpu/gmc9: remove unused register defsAlex Deucher1-14/+0
These got moved to the new df module so no longer used in this file. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amdgpu: add HDP flush dummy for UVD 6/7Christian König2-3/+26
The UVD firmware doesn't seem to like the HDP flush here. This worked for years without HDP flush, so just skip it. Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amdgpu: set ttm bo priority before initializationJunwei Zhang1-3/+2
Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: David Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/pp: Fix performance drop on FijiRex Zhu1-3/+1
The performance drop if the default TDP more than 256 Watt Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/pp: Implement force_clock_level for RVRex Zhu1-0/+45
under manual dpm mode, user can set gfx/mem clock through sysfs pp_dpm_sclk/mclk on Rv. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/powerplay: add PME smu message for ravenJunwei Zhang1-1/+2
Used for working around an audio bug on some platforms. Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/display: clean up assignment of amdgpu_crtcColin Ian King1-1/+1
The declaration of pointer amdgpu_crtc has a redundant assignment to amdgpu_crtc. Clean this up by removing it. Detected by CoverityScan, CID#1460299 ("Evaluation order violation") Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/powerplay: fix spelling mistake: "contruct" -> "construct"Colin Ian King2-2/+2
Trivial fix to spelling mistake in PP_ASSERT_WITH_CODE message text Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/pp: Refine the output of pp_power_profile_mode on VIRex Zhu2-30/+23
In order to keep consist with Vega, the output format of the pp_power_profile_mode would be <integer><mode name string>< “*” for current profile>:"detail settings" and remove the "CURRENT" mode line. for example: NUM MODE_NAME SCLK_UP_HYST SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL MCLK_UP_HYST MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL 0 3D_FULL_SCREEN: 0 100 30 0 100 10 1 POWER_SAVING: 10 0 30 - - - 2 VIDEO: - - - 10 16 31 3 VR: 0 11 50 0 100 10 4 COMPUTE: 0 5 30 - - - 5 CUSTOM *: 0 5 30 0 100 10 NUM MODE_NAME SCLK_UP_HYST SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL MCLK_UP_HYST MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL 0 3D_FULL_SCREEN: 0 100 30 0 100 10 1 POWER_SAVING *: 10 0 30 0 100 10 2 VIDEO: - - - 10 16 31 3 VR: 0 11 50 0 100 10 4 COMPUTE: 0 5 30 - - - 5 CUSTOM: - - - - - - Reviewed-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amdgpu: invalidate parent bo when shadow bo was invalidatedChunming Zhou1-0/+4
Shadow BO is located on GTT and its parent (PT and PD) BO could located on VRAM. In some case, the BO on GTT could be evicted but the parent did not. This may cause the shadow BO not be put in the evict list and could not be invalidate correctly. v2: suggested by Christian Signed-off-by: Chunming Zhou <[email protected]> Reported-by: Shaoyun Liu <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amdgpu: abstract bo_base init functionChunming Zhou1-35/+38
Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/amdgpu: Add some documentation to the debugfs entriesTom St Denis1-4/+189
Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/amdgpu: vcn10 Add callback for emit_reg_write_reg_waitTom St Denis1-0/+1
The callback .emit_reg_write_reg_wait was missing for vcn decode which resulted in a kernel oops. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amdgpu: Fix display corruption on CI with dpm enabledRex Zhu1-16/+16
with dpm enabled, need to get active crtcs in dc/no-dc mode. caused by 'commit ebb649667a31 ("drm/amdgpu: Set pm_display_cfg in non-dc mode")' Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/pp: Skip fan attributes if fan not presentRex Zhu2-13/+11
With powerplay enabled, also need to skip fan attributes if no fan present. Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amdgpu: Switch to interruptable wait to recover from ring hang.Andrey Grodzovsky1-2/+4
v2: Use dma_fence_wait instead of dma_fence_wait_timeout(...,MAX_SCHEDULE_TIMEOUT) Avoid printing error message for ERESTARTSYS Originally-by: David Panariti <[email protected]> Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/display: disable FBC on underlay pipeShirish S1-1/+6
FBC is not applicable for the underlay pipe, hence disallow enabling and disabling of the same. This also fixes the BUG hit of calling sleep in atomic context. Signed-off-by: Shirish S <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/display: Use kvzalloc for potentially large allocationsMichel Dänzer2-41/+45
Allocating up to 32 physically contiguous pages can easily fail (and has failed for me), and isn't necessary anyway. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amdgpu/uvd7: add emit_reg_write_reg_wait ring callbackXiaojie Yuan1-0/+1
Fix the NULL pointer dereference while running amdgpu_test: [ 54.972246] BUG: unable to handle kernel NULL pointer dereference at 0000000000000000 [ 54.972265] IP: (null) [ 54.972273] PGD 0 P4D 0 [ 54.972280] Oops: 0010 [#1] SMP PTI [ 54.972288] Modules linked in: amdkfd amd_iommu_v2 amdgpu(OE) chash gpu_sched ttm drm_kms_helper drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect sysimgblt snd_hda_codec_realtek snd_hda_codec_generic snd_hda_codec_hdmi snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep intel_rapl snd_pcm snd_seq_midi snd_seq_midi_event snd_rawmidi x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel snd_seq snd_seq_device kvm irqbypass snd_timer crct10dif_pclmul crc32_pclmul ghash_clmulni_intel pcbc snd soundcore joydev input_leds aesni_intel aes_x86_64 crypto_simd glue_helper cryptd idma64 virt_dma mei_me intel_lpss_pci serio_raw intel_cstate intel_rapl_perf shpchp intel_pch_thermal mei mac_hid intel_lpss acpi_pad parport_pc ppdev nfsd lp auth_rpcgss nfs_acl lockd grace sunrpc parport autofs4 hid_generic [ 54.972434] usbhid mxm_wmi e1000e psmouse ahci hid libahci wmi pinctrl_sunrisepoint video pinctrl_intel [ 54.972457] CPU: 6 PID: 1393 Comm: uvd Tainted: G OE 4.16.0-rc7-27fb84fda777 #1 [ 54.972473] Hardware name: MSI MS-7984/Z170 KRAIT GAMING (MS-7984), BIOS B.80 05/11/2016 [ 54.972489] RIP: 0010: (null) [ 54.972497] RSP: 0018:ffffaea002c8bcc0 EFLAGS: 00010202 [ 54.972508] RAX: 0000000000000000 RBX: ffff9d30d3c56f60 RCX: 00000000007c0002 [ 54.972522] RDX: 000000000001a6fb RSI: 000000000001a6e9 RDI: ffff9d30d3c56f60 [ 54.972536] RBP: ffffaea002c8bd10 R08: 0000000000000002 R09: ffffffffc06977d0 [ 54.972550] R10: 0000000000000040 R11: 0000000000000000 R12: 0000000000000002 [ 54.972564] R13: ffff9d30d3c5001c R14: ffff9d30d3c50000 R15: 0000000000000006 [ 54.972579] FS: 0000000000000000(0000) GS:ffff9d30eed80000(0000) knlGS:0000000000000000 [ 54.972594] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 54.972606] CR2: 0000000000000000 CR3: 00000002dbc0a001 CR4: 00000000003606e0 [ 54.972620] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 54.972634] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 54.972648] Call Trace: [ 54.972685] ? gmc_v9_0_emit_flush_gpu_tlb+0x111/0x140 [amdgpu] [ 54.972721] uvd_v7_0_ring_emit_vm_flush+0x31/0x70 [amdgpu] [ 54.972751] amdgpu_vm_flush+0x5dc/0x6c0 [amdgpu] [ 54.972787] ? pp_dpm_powergate_uvd+0x50/0x80 [amdgpu] [ 54.972816] amdgpu_ib_schedule+0x120/0x4e0 [amdgpu] [ 54.972850] amdgpu_job_run+0x17b/0x1c0 [amdgpu] [ 54.972861] drm_sched_main+0x2cc/0x490 [gpu_sched] [ 54.972873] ? wait_woken+0x80/0x80 [ 54.972882] kthread+0x121/0x140 [ 54.972891] ? drm_sched_job_finish+0xf0/0xf0 [gpu_sched] [ 54.972902] ? kthread_create_worker_on_cpu+0x70/0x70 [ 54.972914] ret_from_fork+0x35/0x40 [ 54.972922] Code: Bad RIP value. [ 54.972932] RIP: (null) RSP: ffffaea002c8bcc0 [ 54.972943] CR2: 0000000000000000 [ 54.972951] ---[ end trace 5feb349263bbf633 ]--- Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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