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path: root/drivers/gpu/drm/amd
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2021-02-09drm/amdgpu: add generic pci reset as an optionAlex Deucher3-3/+17
This allows us to use generic PCI reset mechanisms (FLR, SBR) as a reset mechanism to verify that the generic PCI reset mechanisms are working properly. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu/vi: minor clean up of reset codeAlex Deucher1-22/+14
Drop duplicate reset method logging, whitespace changes. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu/cik: minor clean up of reset codeAlex Deucher1-22/+11
Drop duplicate reset method logging, whitespace changes. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu/si: minor clean up of reset codeAlex Deucher1-5/+2
Drop duplicate reset method logging, whitespace changes. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/pm: add support for hwmon control of slow and fast PPT limit on vangoghXiaomeng Hou6-18/+204
Implement hwmon API for reading/setting slow and fast PPT limit. APU power is managed to system-level requirements through the PPT (package power tracking) feature. PPT is intended to limit power to the requirements of the power source and could be dynamically updated to maximize APU performance within the system power budget. Here FAST_PPT_LIMIT manages the ~10 ms moving average of APU power, while SLOW_PPT_LIMIT manages the configurable, thermally significant moving average of APU power (default ~5000 ms). User could read slow/fast ppt limit using command "cat power*_cap" or "sensors" in the hwmon device directory. User could adjust values of slow/fast ppt limit as needed depending on workloads through command "echo ## > power*_cap". Example: $ echo 15000000 > power1_cap $ echo 18000000 > power2_cap $ sensors amdgpu-pci-0300 Adapter: PCI adapter slowPPT: 9.04W (cap = 15.00 W) fastPPT: 9.04W (cap = 18.00 W) v2: align with existing interfaces for the getting/setting of PPT limits. Encode the upper 8 bits of limit value to distinguish slow and fast power limit type. Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/pm: modify the power limit level parameter from bool to enum typeXiaomeng Hou3-5/+21
The original smu_get_power_limit callback accepts the power limit level parameter as bool which limits to max and current. For possible needs to retrieve other level like min, extend the parameter type using enum. Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/pm: update the smu v11.5 smc header for vangoghXiaomeng Hou2-1/+9
Add PP messages for reading/setting Fast PPT and Slow PPT limit. Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: enable wave limit on non high prio cs pipesNirmoy Das2-2/+94
To achieve the best QoS for high priority compute jobs it is required to limit waves on other compute pipes as well. This patch will set min value in non high priority mmSPI_WCL_PIPE_PERCENT_CS[0-3] registers to minimize the impact of normal/low priority compute jobs over high priority compute jobs. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: Add otg vertical interrupt0 support in DCN1.0Wayne Lin3-0/+54
[Why & How] On DCN1.0, need otg vertical line interrupt to get appropriate timing to achieve specific feature request. Add otg vertical interrupt0 support for registers which operation is vertical sensitive. Signed-off-by: Wayne Lin <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: Add otg vertical IRQ SourceWayne Lin1-0/+1
[Why & How] In order to get appropriate timing for registers which read/write is vertical line sensitive, add new IRQ source variable. This interrupt is triggered by specific vertical line, Signed-off-by: Wayne Lin <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: optimize list operation in amdgpu_xgmiKevin Wang1-6/+4
simplify the list operation. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/pm/swsmu: unify the init soft gpu metrics functionKevin Wang11-47/+45
the soft gpu metrics is not asic related data structure. unify them to reduce duplicate code. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: support rom clockgating related function for NV familyLikun Gao2-0/+40
Add functions to support enable/disable rom clock gating and get rom clock gating status. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: switch to use smuio callbacks for NV familyLikun Gao1-3/+15
Switch to smuio callbacks: use smuio v11_0_6 callbacks for Sienna_cichlid and forward ASIC, use smuio v11_0 callbacks for the other NV family ASIC. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: implement smuio v11_0_6 callbacksLikun Gao3-1/+73
Implement smuio v11_0_6 callbacks which will used by Sienna_Cichlid and forward ASIC. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: add SMUIO 11.0.6 register headersLikun Gao2-0/+76
Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: support ASPM for some specific ASICLikun Gao3-6/+124
Support to program ASPM and LTR for Sienna Cichlid and forward ASIC. Disable ASPM for Sienna Cichlid and forward ASIC by default. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/pm: enable DCSKenneth Feng3-2/+12
Enable DCS V1: Enable Async DCS. V2: Add the ppfeaturemask bit to enable from the modprobe parameter. V3: 1. add the flag to skip APU support. 2. remove the hunk for workload selection since it doesn't impact the function. Signed-off-by: Kenneth Feng <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu/gmc9: fix mmhub client mapping for arcturusAlex Deucher1-34/+32
The hw interface changed on arcturus so the old numbering scheme doesn't work. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu/smu12: fix power reporting on renoirAlex Deucher1-1/+1
Align with Vangogh. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1467 Acked-by: Nirmoy Das <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdkfd: Get unique_id dynamically v2Kent Russell2-4/+3
Instead of caching the value during amdgpu_device_init, just call the function directly. This avoids issues where the unique_id hasn't been saved by the time that KFD's topology snapshot is done (e.g. Arcturus). KFD's topology information from the amdgpu_device was initially cached at KFD initialization due to amdkfd and amdgpu being separate modules. Now that they are combined together, we can directly call the functions that we need and avoid this unnecessary duplication and complexity. As a side-effect of this change, we also remove unique_id=0 for CPUs, which is obviously not unique. v2: Drop previous patch printing unique_id in hex Signed-off-by: Kent Russell <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/pm: enable ACDC featureKenneth Feng1-0/+3
The power limit and clock ragne are different in AC mode and DC mode. Firmware does the setting after this feature is enabled. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: enable gfx wave limiting for high priority compute jobsNirmoy Das1-0/+9
Enable gfx wave limiting for gfx jobs before pushing high priority compute jobs so that high priority compute jobs gets more resources to finish early. v2: use ring priority instead of job priority. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: add wave limit functionality for gfx8,9Nirmoy Das3-2/+38
Wave limiting can be use to load balance high priority compute jobs along with gfx jobs. When enabled, this will reserve ~75% of waves for compute jobs. We do not need this from gfx10 onwards because >=gfx10 has asynchronous compute tunneling to replace wave limit requirement. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: enable only one high prio compute queueNirmoy Das5-21/+15
For high priority compute to work properly we need to enable wave limiting on gfx pipe. Wave limiting is done through writing into mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high priority compute queue to avoid race condition between multiple high priority compute queues writing that register simultaneously. Signed-off-by: Nirmoy Das <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: cleanup struct amdgpu_ringNirmoy Das2-11/+3
This patch consist of below related changes: 1 Rename ring->priority to ring->hw_prio. 2 Assign correct hardware ring priority. 3 Remove ring->priority_mutex as ring priority remains unchanged after initialization. 4 Remove unused ring->num_jobs. v3: remove ring->num_jobs. v2: remove ring->priority_mutex. Fixes: 33abcb1f5a17 ("drm/amdgpu: set compute queue priority at mqd_init") Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: Fix unused variable warningBhawanpreet Lakha1-2/+0
[Why] The dm struct is only being used if DCN config is defined and this causes a unused variable warning if DCN option is not set. [How] Remove the compile flag so the variable is used (there also seems to be a duplicate guard due to a bad rebase) so remove the outer guard to fix the warning. Fixes this warning drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c: In function 'dm_set_vblank': drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:5380:33: warning: unused variable 'dm' [-Wunused-variable] Fixes: 98ab5f3513f9 ("drm/amd/display: Fix deadlock during gpu reset v3") Cc: Alex Deucher <[email protected]> Cc: Nicholas Kazlauskas <[email protected]> Cc: Stephen Rothwell <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09Revert "drm/amd/display: fix unused variable warning"Alex Deucher1-2/+0
This reverts commit 4c3a3292730c56591472717d8c5c0faf74f6c6bb. Bhawan's fix is better (less ifdefs), so revert this and apply Bhawan's. Signed-off-by: Alex Deucher <[email protected]>
2021-02-05drm/amd/display: fix unused variable warningArnd Bergmann1-0/+2
After all users of the 'dm' warnings got hidden in an #ifdef, the compiler started warning about it being unused: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5380:33: error: unused variable 'dm' [-Werror,-Wunused-variable] Add another such #ifdef. Fixes: 98ab5f3513f9 ("drm/amd/display: Fix deadlock during gpu reset v3") Signed-off-by: Arnd Bergmann <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-02drm/amd/display: Decrement refcount of dc_sink before reassignmentVictor Lu1-1/+3
[why] An old dc_sink state is causing a memory leak because it is missing a dc_sink_release before a new dc_sink is assigned back to aconnector->dc_sink. [how] Decrement the dc_sink refcount before reassigning it to a new dc_sink. Signed-off-by: Victor Lu <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amd/display: Free atomic state after drm_atomic_commitVictor Lu1-8/+6
[why] drm_atomic_commit was changed so that the caller must free their drm_atomic_state reference on successes. [how] Add drm_atomic_commit_put after drm_atomic_commit call in dm_force_atomic_commit. Signed-off-by: Victor Lu <[email protected]> Reviewed-by: Roman Li <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amd/display: Fix dc_sink kref count in emulated_link_detectVictor Lu1-2/+2
[why] prev_sink is not used anywhere else in the function and the reference to it from dc_link is replaced with a new dc_sink. [how] Change dc_sink_retain(prev_sink) to dc_sink_release(prev_sink). Signed-off-by: Victor Lu <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amd/display: Release DSC before acquiringMikita Lipski1-1/+5
[why] Need to unassign DSC from pipes that are not using it so other pipes can acquire it. That is needed for asic's that have unmatching number of DSC engines from the number of pipes. [how] Before acquiring dsc to stream resources, first remove it. Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Eryk Brol <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amd/display: Revert "Fix EDID parsing after resume from suspend"Stylon Wang1-2/+0
This reverts commit b24bdc37d03a0478189e20a50286092840f414fa. It caused memory leak after S3 on 4K HDMI displays. Signed-off-by: Stylon Wang <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-02-02drm/amd/display: Add more Clock Sources to DCN2.1Sung Lee1-0/+10
[WHY] When enabling HDMI on ComboPHY, there are not enough clock sources to complete display detection. [HOW] Initialize more clock sources. Signed-off-by: Sung Lee <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amd/display: reuse current context instead of recreating oneBhawanpreet Lakha3-23/+30
[Why] Currently we discard the current context and recreate it. The current context is what is applied to the HW so we should be re-using this rather than creating a new context. Recreating the context can lead to mismatch between new context and the current context For example: gsl groups get changed when we create a new context this can cause issues in a multi display config (with flip immediate) because we don't align the existing gsl groups in the new and current context. If we reuse the current context the gsl group assignment stays the same. [How] Instead of discarding the current context, we instead just copy the current state and add/remove planes and streams. Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amd/display: Fix DPCD translation for LTTPR AUX_RD_INTERVALGeorge Shen1-3/+3
[Why] The translation between the DPCD value and the specified AUX_RD_INTERVAL in the DP spec do not match. [How] Update values to match the spec. Signed-off-by: George Shen <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amdgpu: enable freesync for A+A configsChristian König2-3/+7
Some newer APUs can scanout directly from GTT, that saves us from allocating another bounce buffer in VRAM and enables freesync in such configurations. Without this patch creating a framebuffer from the imported BO will fail and userspace will fall back to a copy. Signed-off-by: Christian König <[email protected]> Reviewed-by: Shashank Sharma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amd/pm: fill in the data member of v2 gpu metrics table for vangoghXiaojian Du1-0/+3
This patch is to fill in the data member of v2 gpu metrics table for vangogh. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amdgpu/gfx10: update CGTS_TCC_DISABLE and CGTS_USER_TCC_DISABLE register ↵chen gong1-2/+16
offsets for VGH For Vangogh: The offset of the CGTS_TCC_DISABLE is 0x5006 by calculation. The offset of the CGTS_USER_TCC_DISABLE is 0x5007 by calculation. Signed-off-by: chen gong <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amdkfd: fix null pointer panic while free buffer in kfdHuang Rui1-10/+6
In drm_gem_object_free, it will call funcs of drm buffer obj. So kfd_alloc should use amdgpu_gem_object_create instead of amdgpu_bo_create to initialize the funcs as amdgpu_gem_object_funcs. [ 396.231390] amdgpu: Release VA 0x7f76b4ada000 - 0x7f76b4add000 [ 396.231394] amdgpu: remove VA 0x7f76b4ada000 - 0x7f76b4add000 in entry 0000000085c24a47 [ 396.231408] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 396.231445] #PF: supervisor read access in kernel mode [ 396.231466] #PF: error_code(0x0000) - not-present page [ 396.231484] PGD 0 P4D 0 [ 396.231495] Oops: 0000 [#1] SMP NOPTI [ 396.231509] CPU: 7 PID: 1352 Comm: clinfo Tainted: G OE 5.11.0-rc2-custom #1 [ 396.231537] Hardware name: AMD Celadon-RN/Celadon-RN, BIOS WCD0401N_Weekly_20_04_0 04/01/2020 [ 396.231563] RIP: 0010:drm_gem_object_free+0xc/0x22 [drm] [ 396.231606] Code: eb ec 48 89 c3 eb e7 0f 1f 44 00 00 55 48 89 e5 48 8b bf 00 06 00 00 e8 72 0d 01 00 5d c3 0f 1f 44 00 00 48 8b 87 40 01 00 00 <48> 8b 00 48 85 c0 74 0b 55 48 89 e5 e8 54 37 7c db 5d c3 0f 0b c3 [ 396.231666] RSP: 0018:ffffb4704177fcf8 EFLAGS: 00010246 [ 396.231686] RAX: 0000000000000000 RBX: ffff993a0d0cc400 RCX: 0000000000003113 [ 396.231711] RDX: 0000000000000001 RSI: e9cda7a5d0791c6d RDI: ffff993a333a9058 [ 396.231736] RBP: ffffb4704177fdd0 R08: ffff993a03855858 R09: 0000000000000000 [ 396.231761] R10: ffff993a0d1f7158 R11: 0000000000000001 R12: 0000000000000000 [ 396.231785] R13: ffff993a0d0cc428 R14: 0000000000003000 R15: ffffb4704177fde0 [ 396.231811] FS: 00007f76b5730740(0000) GS:ffff993b275c0000(0000) knlGS:0000000000000000 [ 396.231840] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 396.231860] CR2: 0000000000000000 CR3: 000000016d2e2000 CR4: 0000000000350ee0 [ 396.231885] Call Trace: [ 396.231897] ? amdgpu_amdkfd_gpuvm_free_memory_of_gpu+0x24c/0x25f [amdgpu] [ 396.232056] ? __dynamic_dev_dbg+0xcd/0x100 [ 396.232076] kfd_ioctl_free_memory_of_gpu+0x91/0x102 [amdgpu] [ 396.232214] kfd_ioctl+0x211/0x35b [amdgpu] [ 396.232341] ? kfd_ioctl_get_queue_wave_state+0x52/0x52 [amdgpu] Fixes: 246cb7e49a70 ("drm/amdgpu: Introduce GEM object functions") Reviewed-by: Felix Kuehling <[email protected]> Tested-by: Changfeng <[email protected]> Signed-off-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-02-02drm/amdgpu: fix the issue that retry constantly once the buffer is oversizeHuang Rui1-1/+1
We cannot modify initial_domain every time while the retry starts. That will cause the busy waiting that unable to switch to GTT while the vram is not enough. Fixes: f8aab60422c3 ("drm/amdgpu: Initialise drm_gem_object_funcs for imported BOs") Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-02-02drm/amdgpu: Prevent shift wrapping in amdgpu_read_mask()Dan Carpenter1-3/+3
If the user passes a "level" value which is higher than 31 then that leads to shift wrapping. The undefined behavior will lead to a syzkaller stack dump. Fixes: 5632708f4452 ("drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)") Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02amd/display: remove unneeded variable: "pattern"Bernard Zhao1-3/+1
Remove unneeded variable: "pattern". Signed-off-by: Bernard Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amd/pm: Disable GFXOFF when GFX DPM or PG disabledJinzhou Su1-4/+10
Check GFX DPM and PG bit before enable GFXOFF on Vangogh smu post init. Signed-off-by: Jinzhou Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amd/display: 3.2.121Aric Cyr1-1/+1
This version brings along following fixes: - Better handling of dummy p-state table - Workaround for some legacy DP-VGA dongles - Add Freesync HDMI support to DMCU - Enable "trigger_hotplug" debugfs on all outputs - fix initial bounding box values for dcn3.02 - implement support for DID2.0 dsc passthrough - fix calculation for the pwl backlight curve - Fix multiple memory leaks Signed-off-by: Aric Cyr <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amd/display: [FW Promotion] Release 0.0.50Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amd/display: Reject too small viewport size when validating planeNikola Cornij3-3/+29
[why] Overlay won't move to a new positon if viewport size is smaller than what can be handled. It'd either disappear or stay at the old position. This condition is for example hit if overlay is moved too much outside of left or top edge of the screen, but it applies to any non-cursor plane type. [how] Reject this contidion at validation time. This gives the calling level a chance to handle this gracefully and avoid inconsistent behaivor. Signed-off-by: Nikola Cornij <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amd/display: Better handling of dummy p-state tableJoshua Aberback1-7/+5
[Why] Some scenarios where we use a UCLK frequency in between dummy p-state table entries result in a p-state hang, due to the table not having a close enough match, so the default DPM0 latency is used, which can be too long to support dummy p-state switching in these scenarios. [How] - old: match if current freq is within +- margin of table entry - new: find largest table entry that is lower than current freq + margin - lower than DPM0 will still use DPM0 Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-02drm/amd/display: Workaround for some legacy DP-VGA donglesTaimur Hassan1-1/+12
[Why] Maximum resolution is 1440*900 when connecting to FHD monitor via some DP-VGA dongles. The display EDID reading fails over AUX/I2C via DP->VGA dongle, and this leads to the maximum resolution 1920*1080 cannot be obtained from EDID. [How] Provide a workaround for some legacy DP-VGA dongles with a longer aux delay. Signed-off-by: Taimur Hassan <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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