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2021-01-25drm/amd/display: fix 64-bit division issue on 32-bit OSLang Yu1-6/+6
Replace "/" with div_u64 for 32-bit OS. On 32-bit OS, the use of "/" for 64-bit division will cause build error, i.e. "__udivdi3/__divdi3 undefined!". Fixes: ea7154d8d9fb26 ("drm/amd/display: Update dcn30_apply_idle_power_optimizations() code") Signed-off-by: Lang Yu <[email protected]> Acked-by: Huang Rui <[email protected]> Reviewed-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-25Revert "drm/amd/display: Tune min clk values for MPO for RV"Pratik Vishwakarma1-27/+3
This reverts commit 57eeaf47a613c67d0380cf0afad73d8f52df2670. Original issue of flash line when MPO enabled on idle screen was fixed by raising clocks. This had negative effect of extra power being drained. With the upstream commit 9d03bb102028 ("drm/amd/display: disable dcn10 pipe split by default") flash line issue was fixed and had positive effect for battery life. Hence this patch is no more required. Signed-off-by: Pratik Vishwakarma <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-25drm/amdgpu: race issue when jobs on 2 ring timeoutHorace Chen1-10/+59
Fix a racing issue when jobs on 2 rings timeout simultaneously. If 2 rings timed out at the same time, the amdgpu_device_gpu_recover will be reentered. Then the adev->gmc.xgmi.head will be grabbed by 2 local linked list, which may cause wild pointer issue in iterating. lock the device earily to prevent the node be added to 2 different lists. also increase karma for the skipped job since the job is also timed out and should be guilty. Signed-off-by: Horace Chen <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-25drm/amdgpu: Make contiguous pinning optionalFelix Kuehling1-1/+6
Enable pinning of VRAM without forcing it to be contiguous. When memory is already pinned, make sure it's contiguous if requested. Suggested-by: Christian König <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3Aaron Liu1-23/+61
Starting from vangogh, the ATCL2 and DAGB0 registers relative to mgcg/ls has changed. For MGCG: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. For MGLS: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. Add DAGB0_(WR/RD)_CGTT_CLK_CTRL registers. Signed-off-by: Aaron Liu <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu: modify GCR_GENERAL_CNTL for VangoghJinzhou Su1-1/+3
GCR_GENERAL_CNTL is defined differently in gc_10_1_0_offset.h and gc_10_3_0_offset.h. Update GCR_GENERAL_CNTL for Vangogh. Signed-off-by: Jinzhou Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu/pm: no need GPU status set since ↵Prike Liang1-1/+1
mmnbif_gpu_BIF_DOORBELL_FENCE_CNTL added in FSDL In the renoir there is no need GpuChangeState message set to exit gfxoff in the s0i3 resume since mmnbif_gpu_BIF_DOORBELL_FENCE_CNTL has been added in the s0i3 FSDL. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-01-21drm/amd/display: Fixed corruptions on HPDRX link loss restoreVladimir Stempen1-2/+2
[why] Heavy corruption or blank screen reported on wake, with 6k display connected and FEC enabled [how] When Disable/Enable stream for display pipes on HPDRX, DC should take into account ODM split pipes. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Vladimir Stempen <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amd/display: Use hardware sequencer functions for PG controlNicholas Kazlauskas2-6/+21
[Why & How] These can differ per ASIC or not be present. Don't call the dcn20 ones directly but rather the ones defined by the ASIC init table. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amd/display: Change function decide_dp_link_settings to avoid infinite ↵Bing Guo1-0/+3
looping Why: Function decide_dp_link_settings() loops infinitely when required bandwidth can't be supported. How: Check the required bandwidth against verified_link_cap before trying to find a link setting for it. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Bing Guo <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amd/display: Allow PSTATE chnage when no displays are enabledAric Cyr1-2/+4
[Why] When no displays are currently enabled, display driver should not disallow PSTATE switching. [How] Allow PSTATE switching if either the active configuration supports it, or there are no active displays. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amd/display: Update dram_clock_change_latency for DCN2.1Jake Wang1-1/+1
[WHY] dram clock change latencies get updated using ddr4 latency table, but that update does not happen before validation. This value should not be the default and should be number received from df for better mode support. This may cause a PState hang on high refresh panels with short vblanks such as on 1080p 360hz or 300hz panels. [HOW] Update latency from 23.84 to 11.72. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Jake Wang <[email protected]> Reviewed-by: Sung Lee <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu: remove gpu info firmware of green sardineHuang Rui1-1/+0
The ip discovery is supported on green sardine, it doesn't need gpu info firmware anymore. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 5.10.x
2021-01-21drm/amd/display: DCN2X Find Secondary Pipe properly in MPO + ODM CaseSung Lee1-3/+4
[WHY] Previously as MPO + ODM Combine was not supported, finding secondary pipes for each case was mutually exclusive. Now that both are supported at the same time, both cases should be taken into account when finding a secondary pipe. [HOW] If a secondary pipe cannot be found based on previous bottom pipe, search for a second pipe using next_odm_pipe instead. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Sung Lee <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 5.10.x
2021-01-21drm/amdgpu: remove gpu info firmware of green sardineHuang Rui1-1/+0
The ip discovery is supported on green sardine, it doesn't need gpu info firmware anymore. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdkfd: Enable userptr support when KFD is enabledFelix Kuehling1-0/+2
ROCm user mode depends on userptr support. Without it, KFD is basically useless. Make sure HSA_AMD selects the same options as DRM_AMDGPU_USERPTR to avoid broken configurations where userptr gets enabled but its dependencies are disabled. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Philip Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amd/pm: print the timeout of smc messageHuang Rui1-3/+8
This patch is to help firmware designer to know the smc message timeout status. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu:Add pcie gen5 support in pcie capability.Feifei Xu2-2/+16
Add PCIE_SPEED_32_0GT and PCIE GEN5 support for amdgpu. Signed-off-by: Feifei Xu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu: Allow GfxOff on Vangogh as defaultJinzhou Su1-0/+1
Send allow GfxOff message to SMU to enter GfxOff mode as default. Signed-off-by: Jinzhou Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu: Assign boolean values to a bool variableJiapeng Zhong1-16/+16
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c: 1009:6-16: WARNING: Assignment of 0/1 to bool variable. ./drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c: 200:2-10: WARNING: Assignment of 0/1 to bool variable. Reviewed-by: Harry Wentland <[email protected]> Reported-by: Abaci Robot <[email protected]> Signed-off-by: Jiapeng Zhong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amd/display: Fix spelling mistake of function nameColin Ian King1-2/+2
There are two spelling mistakes of the function name, fix this by using __func__ instead of a hard coded name string. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amd/display: Update dcn30_apply_idle_power_optimizations() codeBhawanpreet Lakha4-39/+129
Update the function for idle optimizations -remove hardcoded size -enable no memory-request case -add cursor copy -update mall eligibility check case Signed-off-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amd/display: Dynamic cursor cache size for MALL eligibility checkBhawanpreet Lakha6-9/+33
[Why] Currently we use the maximum possible cursor cache size when deciding if we should attempt to enable MALL, but this prevents us from enabling the feature for certain key use cases. [How] - consider cursor bpp when calculating if the cursor fits Signed-off-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amd/display: Enable programing of MALL watermarksBhawanpreet Lakha1-9/+9
-Uncomment watermark set d -This populates the wm table so that it can be sent to PMFW -This watermark table is used when we are in mall stutter Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3Aaron Liu1-23/+61
Starting from vangogh, the ATCL2 and DAGB0 registers relative to mgcg/ls has changed. For MGCG: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. For MGLS: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. Add DAGB0_(WR/RD)_CGTT_CLK_CTRL registers. Signed-off-by: Aaron Liu <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu: Add RLC_PG_DELAY_3 for VangoghJinzhou Su1-0/+15
Driver should enable the CGPG feature for RLC in safe mode to prevent any misalignment or conflict in middle of any power feature entry/exit sequence. Achieved by setting RLC_PG_CNTL.GFX_POWER_GATING_ENABLE = 0x1, and RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value in refclk count. Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Jinzhou Su <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu/pm: no need GPU status set since ↵Prike Liang1-1/+1
mmnbif_gpu_BIF_DOORBELL_FENCE_CNTL added in FSDL In the renoir there is no need GpuChangeState message set to exit gfxoff in the s0i3 resume since mmnbif_gpu_BIF_DOORBELL_FENCE_CNTL has been added in the s0i3 FSDL. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amdgpu: modify GCR_GENERAL_CNTL for VangoghJinzhou Su1-1/+3
GCR_GENERAL_CNTL is defined differently in gc_10_1_0_offset.h and gc_10_3_0_offset.h. Update GCR_GENERAL_CNTL for Vangogh. Signed-off-by: Jinzhou Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amdgpu: Remove GFXOFF MASK for VangoghJinzhou Su1-3/+0
1. Remove PP_GFXOFF_MASK and then GFXOFF can be enabled by user space. 2. GFXOFF is still disabled on Vangogh by default. 3. When GFXOFF feature on Vangogh landed, will enable GFXOFF by default. 4. GFXOFF can be enabled by debugfs interface amdgpu_gfxoff. Signed-off-by: Jinzhou Su <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/display: 3.2.119Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/display: [FW Promotion] Release 0.0.48Anthony Koo1-2/+2
Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/display: Update dram_clock_change_latency for DCN2.1Jake Wang1-1/+1
[WHY] dram clock change latencies get updated using ddr4 latency table, but that update does not happen before validation. This value should not be the default and should be number received from df for better mode support. This may cause a PState hang on high refresh panels with short vblanks such as on 1080p 360hz or 300hz panels. [HOW] Update latency from 23.84 to 11.72. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Jake Wang <[email protected]> Reviewed-by: Sung Lee <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/display: Allow PSTATE chnage when no displays are enabledAric Cyr1-2/+4
[Why] When no displays are currently enabled, display driver should not disallow PSTATE switching. [How] Allow PSTATE switching if either the active configuration supports it, or there are no active displays. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/display: Fix dml20v2_ModeSupportAndSystemConfigurationFull() to ↵Bing Guo1-38/+79
check DesiredBPP. Why: dml20v2_ModeSupportAndSystemConfigurationFull() didn't check against DesiredBPP, so it doesn't work correctly when DesiredBPP can't be satisfied. How: Port the TruncToValidBPP() version from display_mode_vba_21.c to display_mode_vba_20v2.c. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Bing Guo <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/display: Log link/connector info provided in BIOS object tableGeorge Shen3-0/+30
[Why/How] Add logging statements to assist in debugging errors in the BIOS object table. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: George Shen <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/display: Allow dmu_stg to support cached inbox for dmubWyatt Wood1-2/+9
[Why] FW version check doesn't allow dmu_stg to support cached inbox, which yields much better performance than region 4. [How] Check a range of fw versions, rather than a simple greater than check. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Wyatt Wood <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/display: Change function decide_dp_link_settings to avoid infinite ↵Bing Guo1-0/+3
looping Why: Function decide_dp_link_settings() loops infinitely when required bandwidth can't be supported. How: Check the required bandwidth against verified_link_cap before trying to find a link setting for it. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Bing Guo <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/display: Fix reset sequence with driver direct DMCUB fw loadNicholas Kazlauskas1-3/+3
[Why] DMCUB encounters a page fault/double exception with driver direct load because DMCUB is not held in soft reset after releasing secure reset. The clean shutdown sequence via GPINT is also not executed in this sequence which leaves hardware behavior in an indeterminate state. [How] Move reset earlier in the sequence. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/display: Guard against NULL pointer deref when get_i2c_info failsNicholas Kazlauskas1-0/+5
[Why] If the BIOS table is invalid or corrupt then get_i2c_info can fail and we dereference a NULL pointer. [How] Check that ddc_pin is not NULL before using it and log an error if it is because this is unexpected. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/display: Allow dmub srv hardware reset before HW initNicholas Kazlauskas1-3/+0
[Why] We need hardware reset before hardware init for backdoor loading when we're reusing the framebuffer memory. [How] This doesn't run if the hardware isn't already in reset from software perspective. The reset function has register level checks so just remove the software one here. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/display: Report Freesync to vrr_range debugfs entry in DRMStylon Wang1-0/+4
[Why] Since Linux 5.9.0, DRM has provided vrr_range debugfs for all connectors. Reporting Freesync capability to vrr_range debugfs entry registered in Linux DM no longer works. [How] Report min/max vertical frequency to vrr_range debugfs entrry created by DRM connectors. Remove vrr_range debugfs entry from Linux DM. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Stylon Wang <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/display: Use hardware sequencer functions for PG controlNicholas Kazlauskas2-6/+21
[Why & How] These can differ per ASIC or not be present. Don't call the dcn20 ones directly but rather the ones defined by the ASIC init table. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/display: DCN2X Find Secondary Pipe properly in MPO + ODM CaseSung Lee1-3/+4
[WHY] Previously as MPO + ODM Combine was not supported, finding secondary pipes for each case was mutually exclusive. Now that both are supported at the same time, both cases should be taken into account when finding a secondary pipe. [HOW] If a secondary pipe cannot be found based on previous bottom pipe, search for a second pipe using next_odm_pipe instead. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Sung Lee <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/display: disable FEC while using eDPMike Hsieh1-2/+3
[Why] FEC over eDP support is incomplete. [How] Disable FEC over eDP. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Mike Hsieh <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/display: Fixed corruptions on HPDRX link loss restoreVladimir Stempen1-2/+2
[why] Heavy corruption or blank screen reported on wake, with 6k display connected and FEC enabled [how] When Disable/Enable stream for display pipes on HPDRX, DC should take into account ODM split pipes. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Vladimir Stempen <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/amdgpu: remove redundant flush_delayed_workJingwen Chen1-1/+0
When using cancel_delayed_work_sync, there's no need to flush_delayed_work first. This sequence can lead to a redundant loop of work executing. Signed-off-by: Jingwen Chen <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/pm: remove unused message SMU_MSG_SpareXKevin Wang3-6/+0
the SpareX is reserved by SMU firmware, the driver is never use it. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20Merge tag 'amd-drm-next-5.12-2021-01-20' of ↵Daniel Vetter140-1101/+1936
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.12-2021-01-20: amdgpu: - Fix non-x86 build - W=1 fixes from Lee Jones - Enable GPU reset on Navy Flounder - Kernel doc fixes - SMU workload profile fixes for APUs - Display updates - SR-IOV fixes - Vangogh SMU feature enablment and bug fixes - GPU reset support for Vangogh - Misc cleanups Conflicts: drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c Resolve the conflict by picking the initialization value from amd from f03e80d2e82c ("drm/amd/display: Initialize stack variable") over the one Linus picked in 61d791365b72 ("drm/amd/display: avoid uninitialized variable warning"). It shouldn't matter. From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Daniel Vetter <[email protected]>
2021-01-20Merge tag 'drm-misc-next-2021-01-19' of ↵Daniel Vetter6-27/+28
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v5.12: UAPI Changes: - Fix fourcc macro for amlogic video fbc. Cross-subsystem Changes: - Export pci_rebar_bytes_to_size. - Add a PCI quirk to increase bar0 for RX 5600 XT Pulse to max possible size. - Convert devicetree bindings to use the OF graph schema. - Update s6e63m0 bindings. - Make omapfb2 DSI_CM incompatible with drm/omap2 DSI-CM because of module conflicts. - Add Zack Rusin as vmwgfx maintainer. - Add CONFIG_DMABUF_DEBUG for validating dma-buf users don't loo kat struct page when importing or detaching. Core Changes: - Remove references to drm_device.pdev - Fix regression in ttm_bo_move_to_lru_tail(). - Assorted docbook updates. - Do not send dp-mst hotplug events on error when probing. - Move some agp macros to agpsupport.c, so it's not always compiled. - Move drm_need_swiotlb.h to drm_cache.c - Only build drm_memory.o for legacy drivers, and move CONFIG_DRM_VM to legacy. - Nuke drm_device.hose - Warn when the ttm resource manager is non-empty when disabling. - Assorted small fixes. Driver Changes: - Small assorted fixes in radeon, v3d, hisilicon, mipi-dbi, panfrost, hibmc, vc4, amdgpu, vkms, vmwgfx. - Move hisilicon to use simple encode. - Add writeback connector to vkms. - Add support for BT2020 to DE3. - Use gem prime mmap helpers in vc4, and move the mmap function upwards. - Use managed drm device, and cleanup error paths and display registers in vmwgfx. - Use correct bus_format and connector_type for innolux_n116bge. - Fix a lot of warnings with W=1 (Lee Jones) Signed-off-by: Daniel Vetter <[email protected]> From: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-19drm/amdgpu: fix build error without x86 kconfig (v2)Huang Rui3-7/+16
This patch is to fix below build error while we are using the kconfig without x86. drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c: In function 'vangogh_get_smu_metrics_data': drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c:300:10: error: 'boot_cpu_data' undeclared (first use in this function); did you mean 'boot_cpuid'? 300 | boot_cpu_data.x86_max_cores * sizeof(uint16_t)); | ^~~~~~~~~~~~~ | boot_cpuid drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c: In function 'vangogh_read_sensor': drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c:1320:11: error: 'boot_cpu_data' undeclared (first use in this function); did you mean 'boot_cpuid'? 1320 | *size = boot_cpu_data.x86_max_cores * sizeof(uint16_t); | ^~~~~~~~~~~~~ | boot_cpuid drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c: In function 'vangogh_od_edit_dpm_table': drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c:1460:19: error: 'boot_cpu_data' undeclared (first use in this function); did you mean 'boot_cpuid'? 1460 | if (input[0] >= boot_cpu_data.x86_max_cores) { | ^~~~~~~~~~~~~ | boot_cpuid v2: fix #ifdef and add comment for APU only Reported-by: Stephen Rothwell <[email protected]> Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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