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2024-04-12drm/amd/display: Add fallback configuration for set DRR in DCN10Rodrigo Siqueira1-3/+12
Set OTG/OPTC parameters to 0 if something goes wrong on DCN10. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-12drm/amd/display: Add fallback configuration when set DRRRodrigo Siqueira1-2/+9
Set OTG/OPTC parameter to 0 if failed to set DRR. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-12drm/amd/display: Update DCN10 resourceRodrigo Siqueira1-0/+2
Update DCN10 to use legacy fast update and ensure that the MPCC count is the same as the pipe_count. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-12drm/amd/display: Disable P010 Support of DCN 1.0Rodrigo Siqueira1-1/+1
[WHY] DCN 1.0 is not ready for the P010 support. [HOW] 1. Set the P010 plan_cap of DCN 1.0 to be false. 2. Let the DM do the plan cap initialization of DCN 1.0. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Figo Wang <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-12drm/amd/display: Update resource capabilities and debug struct for DCN201Rodrigo Siqueira1-1/+3
Some of the resource capabilities for DCN201 and the debug default option are outdated. This commit just set some of the missing configurations for DCN201. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-12drm/amd/display: Drop legacy codeRodrigo Siqueira4-53/+1
This commit removes code that are not used by display anymore. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-12drm/amd/display: Adjust some includes used by displayRodrigo Siqueira7-7/+1
Some of the includes used in the DC can be removed and others need to be update. This commit adjusts some of those headers in the display code. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-12drm/amd/display: Add comments to improve the code readabilityRodrigo Siqueira3-1/+3
This commit just introduce some basic comments that helps to understand the overall behavior of some structs. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-12drm/amdgpu: remove invalid resource->start check v2Christian König1-4/+0
The majority of those where removed in the commit aed01a68047b ("drm/amdgpu: Remove TTM resource->start visible VRAM condition v2") But this one was missed because it's working on the resource and not the BO. Since we also no longer use a fake start address for visible BOs this will now trigger invalid mapping errors. v2: also remove the unused variable Signed-off-by: Christian König <[email protected]> Fixes: aed01a68047b ("drm/amdgpu: Remove TTM resource->start visible VRAM condition v2") CC: [email protected] Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-12drm/amdgpu/sdma6: set sdma hang watchdogJack Xiao1-0/+7
Set SDMAx_WATCHDOG_CNTL.QUEUE_HANG_COUNT registers to improve SDMA reliability. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-12drm/amd/amdgpu: Update PF2VF HeaderLuqmaan Irshad1-1/+3
Adding a new field for GPU Capacity to align the header with the host. Signed-off-by: Luqmaan Irshad <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-12amdkfd: use calloc instead of kzalloc to avoid integer overflowDave Airlie1-2/+2
This uses calloc instead of doing the multiplication which might overflow. Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]>
2024-04-10drm/amdgpu: differentiate external rev id for gfx 11.5.0Yifan Zhang1-1/+4
This patch to differentiate external rev id for gfx 11.5.0. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2024-04-09drm/amd/display: Adjust dprefclk by down spread percentage.Zhongwei2-4/+54
[Why] OLED panels show no display for large vtotal timings. [How] Check if ss is enabled and read from lut for spread spectrum percentage. Adjust dprefclk as required. DP_DTO adjustment is for edp only. Cc: [email protected] Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Zhongwei <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Set VSC SDP Colorimetry same way for MST and SSTHarry Wentland1-9/+3
The previous check for the is_vsc_sdp_colorimetry_supported flag for MST sink signals did nothing. Simplify the code and use the same check for MST and SST. Cc: [email protected] Reviewed-by: Agustin Gutierrez <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Program VSC SDP colorimetry for all DP sinks >= 1.4Harry Wentland1-2/+5
In order for display colorimetry to work correctly on DP displays we need to send the VSC SDP packet. We should only do so for panels with DPCD revision greater or equal to 1.4 as older receivers might have problems with it. Cc: [email protected] Cc: Joshua Ashton <[email protected]> Cc: Xaver Hugl <[email protected]> Cc: Melissa Wen <[email protected]> Cc: Agustin Gutierrez <[email protected]> Reviewed-by: Agustin Gutierrez <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: fix disable otg wa logic in DCN316Fudongwang1-7/+12
[Why] Wrong logic cause screen corruption. [How] Port logic from DCN35/314. Cc: [email protected] Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Fudongwang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Do not recursively call manual trigger programmingDillon Varone1-3/+0
[WHY&HOW] We should not be recursively calling the manual trigger programming function when FAMS is not in use. Cc: [email protected] Reviewed-by: Alvin Lee <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: always reset ODM mode in context when adding first planeWenjing Liu1-0/+9
[why] In current implemenation ODM mode is only reset when the last plane is removed from dc state. For any dc validate we will always remove all current planes and add new planes. However when switching from no planes to 1 plane, ODM mode is not reset because no planes get removed. This has caused an issue where we kept ODM combine when it should have been remove when a plane is added. The change is to reset ODM mode when adding the first plane. Cc: [email protected] Reviewed-by: Alvin Lee <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: fix incorrect number of active RBs for gfx11Tim Huang1-1/+1
The RB bitmap should be global active RB bitmap & active RB bitmap based on active SA. Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2024-04-09drm/amd/display: Return max resolution supported by DWBAlex Hung1-4/+2
mode_config's max width x height is 4096x2160 and is higher than DWB's max resolution 3840x2160 which is returned instead. Cc: [email protected] Reviewed-by: Harry Wentland <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09amd/amdkfd: sync all devices to wait all processes being evictedZhigang Luo1-11/+6
If there are more than one device doing reset in parallel, the first device will call kfd_suspend_all_processes() to evict all processes on all devices, this call takes time to finish. other device will start reset and recover without waiting. if the process has not been evicted before doing recover, it will be restored, then caused page fault. Signed-off-by: Zhigang Luo <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: clear set_q_mode_offs when VM changedZhenGuo Yin1-0/+1
[Why] set_q_mode_offs don't get cleared after GPU reset, nexting SET_Q_MODE packet to init shadow memory will be skiped, hence there has a page fault. [How] VM flush is needed after GPU reset, clear set_q_mode_offs when emitting VM flush. Fixes: 8bc75586ea01 ("drm/amdgpu: workaround to avoid SET_Q_MODE packets v2") Reviewed-by: Christian König <[email protected]> Signed-off-by: ZhenGuo Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2024-04-09drm/amdgpu: Fix VCN allocation in CPX partitionLijo Lazar1-4/+11
VCN need not be shared in CPX mode always for all GFX 9.4.3 SOC SKUs. In certain configs, VCN instance can be exclusively allocated to a partition even under CPX mode. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: James Zhu <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/pm: fix the high voltage issue after unloadKenneth Feng4-14/+48
fix the high voltage issue after unload on smu 13.0.10 Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Skip on writeback when it's not applicableAlex Hung1-1/+8
[WHY] dynamic memory safety error detector (KASAN) catches and generates error messages "BUG: KASAN: slab-out-of-bounds" as writeback connector does not support certain features which are not initialized. [HOW] Skip them when connector type is DRM_MODE_CONNECTOR_WRITEBACK. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3199 Reviewed-by: Harry Wentland <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2Tao Zhou1-13/+3
SDMA_CNTL is not set in some cases, driver configures it by itself. v2: simplify code Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: add smu 14.0.1 discovery supportYifan Zhang1-0/+1
This patch to add smu 14.0.1 support Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/swsmu: Update smu v14.0.0 headers to be 14.0.1 compatiblelima10026-43/+413
update ppsmc.h pmfw.h and driver_if.h for smu v14_0_1 Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: lima1002 <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu : Increase the mes log buffer size as per new MES FW versionshaoyunl2-3/+3
From MES version 0x54, the log entry increased and require the log buffer size to be increased. The 16k is maximum size agreed Signed-off-by: shaoyunl <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu : Add mes_log_enable to control mes log featureshaoyunl4-3/+20
The MES log might slow down the performance for extra step of log the data, disable it by default and introduce a parameter can enable it when necessary Signed-off-by: shaoyunl <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11Tim Huang1-1/+11
While doing multiple S4 stress tests, GC/RLC/PMFW get into an invalid state resulting into hard hangs. Adding a GFX reset as workaround just before sending the MP1_UNLOAD message avoids this failure. Signed-off-by: Tim Huang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: add DCN 351 version for microcode loadLi Ma1-1/+6
There is a new DCN veriosn 3.5.1 need to load Signed-off-by: Li Ma <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: Reset dGPU if suspend got abortedLijo Lazar1-0/+25
For SOC21 ASICs, there is an issue in re-enabling PM features if a suspend got aborted. In such cases, reset the device during resume phase. This is a workaround till a proper solution is finalized. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2024-04-09drm/amdgpu/umsch: reinitialize write pointer in hw initLang Yu1-0/+2
Otherwise the old one will be used during GPU reset. That's not expected. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2024-04-09drm/amdgpu: Refine IB schedule error loggingLijo Lazar1-2/+5
Downgrade to debug information when IBs are skipped. Also, use dev_* to identify the device. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: always force full reset for SOC21Alex Deucher1-2/+0
There are cases where soft reset seems to succeed, but does not, so always use mode1/2 for now. Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2024-04-09drm/amdkfd: Reset GPU on queue preemption failureHarish Kasiviswanathan1-0/+1
Currently, with F32 HWS GPU reset is only when unmap queue fails. However, if compute queue doesn't repond to preemption request in time unmap will return without any error. In this case, only preemption error is logged and Reset is not triggered. Call GPU reset in this case also. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Harish Kasiviswanathan <[email protected]> Reviewed-by: Mukul Joshi <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2024-04-09drm/amdgpu: differentiate external rev id for gfx 11.5.0Yifan Zhang1-1/+4
This patch to differentiate external rev id for gfx 11.5.0. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: delete the redundant initialization in dcn3_51_socXiang Yang1-1/+0
the dram_clock_change_latency_us in dcn3_51_soc is initialized twice, so delete one of them. Acked-by: Alex Deucher <[email protected]> Signed-off-by: Xiang Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Add V_TOTAL_REGS to dcn10Rodrigo Siqueira1-0/+3
DCN10 OPTC is used by other DCNs, and in some cases it might be useful to have V_TOTAL_REGS available. This commit add V_TOTAL_REGS as part of the TG field. Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: [FW Promotion] Release 0.0.212.0Anthony Koo1-0/+1
- Add boot option to change the ONO powerup flow, impacting the order of power domains to power up or down first Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09Revert "drm/amd/display: Enabling urgent latency adjustment for DCN35"Qili Lu1-2/+2
This reverts commit b72a7e0fd0f8d235f885f84642e5c71f4e058c4b. It causes a dead loop in dml_prefetch_check. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Qili Lu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Rebuild test pattern params for DP_TEST_PATTERN_VIDEO_MODEGeorge Shen2-3/+3
[Why] For video mode test pattern (i.e. test pattern disable), the call to rebuild test pattern params for the pipe is skipped. This causes dynamic disablement of test pattern to not work, as the test_pattern_params of the pipe will not be updated and retain the values of the previously enabled test pattern. [How] Rebuild test pattern params even when test pattern is video mode, allowing the pipe to have updated test_pattern_params values. Reviewed-by: Nevenko Stupar <[email protected]> Reviewed-by: Chaitanya Dhere <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: George Shen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Adjust dprefclk by down spread percentage.Zhongwei2-4/+54
[Why] OLED panels show no display for large vtotal timings. [How] Check if ss is enabled and read from lut for spread spectrum percentage. Adjust dprefclk as required. DP_DTO adjustment is for edp only. Cc: [email protected] Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Zhongwei <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Set VSC SDP Colorimetry same way for MST and SSTHarry Wentland1-9/+3
The previous check for the is_vsc_sdp_colorimetry_supported flag for MST sink signals did nothing. Simplify the code and use the same check for MST and SST. Cc: [email protected] Reviewed-by: Agustin Gutierrez <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Program VSC SDP colorimetry for all DP sinks >= 1.4Harry Wentland1-2/+5
In order for display colorimetry to work correctly on DP displays we need to send the VSC SDP packet. We should only do so for panels with DPCD revision greater or equal to 1.4 as older receivers might have problems with it. Cc: [email protected] Cc: Joshua Ashton <[email protected]> Cc: Xaver Hugl <[email protected]> Cc: Melissa Wen <[email protected]> Cc: Agustin Gutierrez <[email protected]> Reviewed-by: Agustin Gutierrez <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: add dwb support to dml2Charlene Liu7-1/+119
[why] dwb was not POR previosly. now need to enable dwb in dml2. Limitation: HW DML assumes only one DWB one set of watermark for all 4 watermark sets one stream has one DWB only. WB scaling dml input has one set of scaling tap. (no chroma so far) needs to follow up Reviewed-by: Chris Park <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: refactor vpg.hParandhaman K4-23/+57
why and how: as part of cleanup, need to refactor vpg. It was improperly referenced as a dcn specfic part of link. the dcn agnostic code needed was ripped out and put into vpg.h, now in dc/inc/hw. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Parandhaman K <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: expand the non standard link rate for testingAllen Pan1-0/+5
[Why] 6.75 Gbps link rate training for DP_TEST_LINK_RATE_RATE_8 Reviewed-by: Charlene Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Allen Pan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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