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2021-06-18drm/display: Fix duplicated argumentWan Jiabing1-1/+1
Fix coccicheck warning: ./drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c: 55:12-42: duplicated argument to && or || Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Wan Jiabing <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amd/display: Remove the repeated dpp1_full_bypass declarationShaokun Zhang1-2/+0
Function 'dpp1_full_bypass' is declared twice, so remove the repeated declaration and unnessary blank line. Cc: Harry Wentland <[email protected]> Cc: Leo Li <[email protected]> Cc: Alex Deucher <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Shaokun Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amd/display: Fix fall-through warning for ClangGustavo A. R. Silva1-1/+1
In preparation to enable -Wimplicit-fallthrough for Clang, fix the following warning by replacing a /* fall through */ comment with the new pseudo-keyword macro fallthrough: rivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.c:672:4: warning: unannotated fall-through between switch labels [-Wimplicit-fallthrough] case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER: ^ Notice that Clang doesn't recognize /* fall through */ comments as implicit fall-through markings, so in order to globally enable -Wimplicit-fallthrough for Clang, these comments need to be replaced with fallthrough; in the whole codebase. Link: https://github.com/KSPP/linux/issues/115 Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Gustavo A. R. Silva <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amd/display: remove unused variable 'dc'Pu Lehui1-2/+0
GCC reports the following warning with W=1: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_psr.c:70:13: warning: variable ‘dc’ set but not used [-Wunused-but-set-variable] 70 | struct dc *dc = NULL; | ^~ This variable is not used in function, this commit remove it to fix the warning. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Pu Lehui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amd/display: Fix gcc unused variable warningPu Lehui1-0/+4
GCC reports the following warning with W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:3635:17: warning: variable ‘status’ set but not used [-Wunused-but-set-variable] 3635 | enum dc_status status = DC_ERROR_UNEXPECTED; | ^~~~~~ The variable should be used for error check, let's fix it. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Pu Lehui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amdkfd: Walk through list with dqm lock holdxinhui pan1-10/+12
To avoid any list corruption. Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amd/amdgpu: Use IP discovery data to determine VCN enablement instead of ↵Bokun Zhang5-39/+61
MMSCH In the past, we use MMSCH to determine whether a VCN is enabled or not. This is not reliable since after a FLR, MMSCH may report junk data. It is better to use IP discovery data. Signed-off-by: Bokun Zhang <[email protected]> Signed-off-by: Peng Ju Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amdgpu: remove unused parameter in amdgpu_gart_bindYifan Zhang3-8/+5
Pagelist is no long used in amdgpu_gart_bind. Remove it. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amd/pm: Disable SMU messages in navi10 sriovYifan Zha1-4/+4
[Why] sriov vf send unsupported SMU message lead to fail. [How] disable related messages in sriov. Signed-off-by: Yifan Zha <[email protected]> Acked-by: Jingwen Chen <[email protected]> Reviewed-by: Jack Zhang <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amdgpu: message smu to update hbm bad page numberStanley.Yang4-0/+28
Use SMU to update the bad pages rather than directly accessing the EEPROM from the driver. Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amdgpu: PWRBRK sequence changes for AldebaranAshish Pawar1-5/+0
Modify power brake enablement sequence on Aldebaran Signed-off-by: Ashish Pawar <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amdgpu: fix bad address translation for sienna_cichlidStanley.Yang2-1/+6
Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18amdgpu/pm: replaced snprintf usage in amdgpu_pm.c with sysfs_emitDarren Powell1-13/+14
replaced snprintf usage in amdgpu_pm.c with sysfs_emit fixed warning on comparing int with uint32_t in amdgpu_get_pp_num_states() == Test == AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 10` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" > scnprintf.test.log FILES="pp_num_states pp_od_clk_voltage pp_features pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_vclk pp_dpm_dclk pp_dpm_dcefclk pp_power_profile_mode " for f in $FILES do echo === $f === >> scnprintf.test.log cat $HWMON_DIR/device/$f >> scnprintf.test.log done Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amdkfd: Set iolink non-coherent in topologyEric Huang1-0/+23
Fix non-coherent bit of iolink properties flag which always is 0. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amd/display: Add Freesync video documentationRodrigo Siqueira2-2/+47
Recently, we added support for an experimental feature named Freesync video; for more details on that, refer to: commit 6f59f229f8ed ("drm/amd/display: Skip modeset for front porch change") commit d10cd527f5e5 ("drm/amd/display: Add freesync video modes based on preferred modes") commit 0eb1af2e8205 ("drm/amd/display: Add module parameter for freesync video mode") Nevertheless, we did not document it in detail in our driver. This commit introduces a kernel-doc and expands the module parameter description. Cc: Aurabindo Pillai <[email protected]> Cc: Sean Paul <[email protected]> Cc: Harry Wentland <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amdgpu/vcn3: drop extraneous Beige Goby hunkAlex Deucher1-5/+0
Probably a rebase leftover. This doesn't apply to SR-IOV, and the non-SR-IOV code below it already handles this properly. Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amd/display: Increase stutter watermark for dcn302 and dcn303Aurabindo Pillai2-4/+4
[Why] Current watermarks end up programming lowers watermarks which results in screen flickering and underflow for certain modes like 1440p. [How] Add 11us to stutter exit & stutter enter plus exit watermark. Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amdgpu: add vega20 to ras quirk listStanley.Yang1-1/+3
Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-18drm/amdgpu: Set TTM_PAGE_FLAG_SG earlier for userprt BOsxinhui pan1-3/+3
Because TTM do page counting on userptr BOs which is actually not needed. To avoid that, lets set TTM_PAGE_FLAG_SG after tt_create and before tt_populate. Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-16drm/amdgpu/gfx10: enlarge CP_MEC_DOORBELL_RANGE_UPPER to cover full doorbell.Yifan Zhang1-1/+5
If GC has entered CGPG, ringing doorbell > first page doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround this issue. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-06-16drm/amdgpu/gfx9: fix the doorbell missing when in CGPG issue.Yifan Zhang1-1/+5
If GC has entered CGPG, ringing doorbell > first page doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround this issue. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-06-15drm: display: Fix duplicate field initialization in dcn31Wan Jiabing1-1/+0
Fix the following coccicheck warning: drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c:917:56-57: pstate_enabled: first occurrence line 935, second occurrence line 937 Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wan Jiabing <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amdkfd: Fix circular lock in nocpsch pathAmber Lin1-5/+13
Calling free_mqd inside of destroy_queue_nocpsch_locked can cause a circular lock. destroy_queue_nocpsch_locked is called under a DQM lock, which is taken in MMU notifiers, potentially in FS reclaim context. Taking another lock, which is BO reservation lock from free_mqd, while causing an FS reclaim inside the DQM lock creates a problematic circular lock dependency. Therefore move free_mqd out of destroy_queue_nocpsch_locked and call it after unlocking DQM. Signed-off-by: Amber Lin <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amdgpu: Use spinlock_irqsave for pasid_lockFelix Kuehling1-4/+5
This should fix a kernel LOCKDEP warning on Vega10: [ 149.416604] ================================ [ 149.420877] WARNING: inconsistent lock state [ 149.425152] 5.11.0-kfd-fkuehlin #517 Not tainted [ 149.429770] -------------------------------- [ 149.434053] inconsistent {HARDIRQ-ON-W} -> {IN-HARDIRQ-W} usage. [ 149.440059] swapper/3/0 [HC1[1]:SC0[0]:HE0:SE1] takes: [ 149.445198] ffff9ac80e005d68 (&adev->vm_manager.pasid_lock){?.+.}-{2:2}, at: amdgpu_vm_get_task_info+0x25/0x90 [amdgpu] [ 149.456252] {HARDIRQ-ON-W} state was registered at: [ 149.461136] lock_acquire+0x242/0x390 [ 149.464895] _raw_spin_lock+0x2c/0x40 [ 149.468647] amdgpu_vm_handle_fault+0x44/0x380 [amdgpu] [ 149.474187] gmc_v9_0_process_interrupt+0xa8/0x410 [amdgpu] ... Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Oak Zeng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amdgpu/gfx10: enlarge CP_MEC_DOORBELL_RANGE_UPPER to cover full doorbell.Yifan Zhang1-1/+5
If GC has entered CGPG, ringing doorbell > first page doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround this issue. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amdgpu/gfx9: fix the doorbell missing when in CGPG issue.Yifan Zhang1-1/+5
If GC has entered CGPG, ringing doorbell > first page doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround this issue. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amdgpu: move shadow_list to amdgpu_bo_vmNirmoy Das4-13/+14
Move shadow_list to struct amdgpu_bo_vm as shadow BOs are part of PT/PD BOs. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amdgpu: parameterize ttm BO destroy callbackNirmoy Das2-12/+32
Make provision to pass different ttm BO destroy callback while creating a amdgpu_bo. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amdgpu: remove amdgpu_vm_ptNirmoy Das12-126/+105
Page table entries are now in embedded in VM BO, so we do not need struct amdgpu_vm_pt. This patch replaces struct amdgpu_vm_pt with struct amdgpu_vm_bo_base. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amdgpu: correct psp ucode arrary start addressHawking Zhang1-9/+14
For ASICs that need to load sys_drv_aux and sos_aux, the sys_start_addr is not the start address of psp ucode array because the sys_drv_aux and sos_aux actaully located at the end of the ucode array, instead, the psp ucode arrary start address should be sos_hdr + sos_hdr_offset. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amdkfd: Disable SVM per GPU, not per processFelix Kuehling7-38/+45
When some GPUs don't support SVM, don't disabe it for the entire process. That would be inconsistent with the information the process got from the topology, which indicates SVM support per GPU. Instead disable SVM support only for the unsupported GPUs. This is done by checking any per-device attributes against the bitmap of supported GPUs. Also use the supported GPU bitmap to initialize access bitmaps for new SVM address ranges. Don't handle recoverable page faults from unsupported GPUs. (I don't think there will be unsupported GPUs that can generate recoverable page faults. But better safe than sorry.) Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Philip Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Extend AUX timeout for DP initial readsWesley Chalmers1-4/+3
[WHY] DP LL Compliance tests require that the first DPCD transactions after a hotplug have a timeout interval of 3.2 ms. In cases where LTTPR is disabled, this means that the first reads from DP_SET_POWER and DP_DPCD_REV must have an extended timeout. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Cover edge-case when changing DISPCLK WDIVIDERWesley Chalmers3-6/+69
[WHY] When changing the DISPCLK_WDIVIDER value from 126 to 127, the change in clock rate is too great for the FIFOs to handle. This can cause visible corruption during clock change. HW has handed down this register sequence to fix the issue. [HOW] The sequence, from HW: a. 127 -> 126 Read DIG_FIFO_CAL_AVERAGE_LEVEL FIFO level N = DIG_FIFO_CAL_AVERAGE_LEVEL / 4 Set DCCG_FIFO_ERRDET_OVR_EN = 1 Write 1 to OTGx_DROP_PIXEL for (N-4) times Set DCCG_FIFO_ERRDET_OVR_EN = 0 Write DENTIST_DISPCLK_RDIVIDER = 126 Because of frequency stepping, sequence a can be executed to change the divider from 127 to any other divider value. b. 126 -> 127 Read DIG_FIFO_CAL_AVERAGE_LEVEL FIFO level N = DIG_FIFO_CAL_AVERAGE_LEVEL / 4 Set DCCG_FIFO_ERRDET_OVR_EN = 1 Write 1 to OTGx_ADD_PIXEL for (12-N) times Set DCCG_FIFO_ERRDET_OVR_EN = 0 Write DENTIST_DISPCLK_RDIVIDER = 127 Because of frequency stepping, divider must first be set from any other divider value to 126 before executing sequence b. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Add interface to get Calibrated Avg Level from FIFOWesley Chalmers8-0/+60
[WHY] Hardware has handed down a new sequence requiring the value of this register be read from clk_mgr. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Partition DPCD address space and break up transactionsWesley Chalmers1-2/+85
[WHY] SCR for DP 2.0 spec says that multiple LTTPRs must not be accessed in a single AUX transaction. There may be other places in future where breaking up AUX accesses is necessary. [HOW] Partition the entire DPCD address space into blocks. When an incoming AUX request spans multiple blocks, break up the request into multiple requests. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Do not count I2C DEFERs with AUX DEFERsWesley Chalmers1-1/+2
[WHY] DP 2.0 SCR specifies that "A DPTX shall distinguish I2C_DEFER|AUX_ACK from AUX_DEFER. AUX retries due to I2C_DEFER are not counted as part of minimum 7 retires (sic) upon AUX_DEFER’s" Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: 7 retries + 50 ms timeout on AUX DEFERWesley Chalmers1-3/+15
[WHY] DP 2.0 SCR specifies that TX devices must retry at least 7 times when receiving an AUX DEFER reply from RX. In addition, the specification states that the TX shall not retry indefinitely, and gives a suggestive timeout interval of 50ms. [HOW] Keep retrying until both 7 or more retries have been made, and the 50ms interval has passed. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Rename constantWesley Chalmers1-3/+3
[WHY] 7 is the minimum number of retries TX must attempt on an AUX DEFER, not the maximum. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Enforce DPCD Address rangesWesley Chalmers11-45/+162
[WHY] Some DPCD addresses, notably LTTPR Capability registers, are expected to be read all together in a single DPCD transaction. Rather than force callers to read registers they don't need, we want to quietly extend the addresses read, and only return back the values the caller asked for. This does not affect DPCD writes. [HOW] Create an additional layer above AUX to perform 'checked' DPCD transactions. Iterate through an array of DPCD address ranges that are marked as being contiguous. If a requested read falls within one of those ranges, extend the read to include the entire range. After DPCD has been queried, copy the requested bytes into the caller's data buffer, and deallocate all resources used. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Improve logic for is_lttpr_presentWesley Chalmers1-2/+1
[WHY] DP specifies that an LTTPR device is only present if PHY_REPEATER_CNT is 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, or 0x01. All other values should be considered no LTTPRs present. [HOW] Function dp_convert_to_count already does this check. Use it to determine if PHY_REPEATER_CNT is a valid LTTPR count. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Always write repeater mode regardless of LTTPRWesley Chalmers1-4/+3
[WHY] SCR for DP2.0 requires that LT be performed with PHY_REPEATER_MODE programmed to 0x55 (Transparent) whenever PHY_REPEATER_CNT is any value other than 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, or 0x01. [HOW] Write Non-Transparent (0xAA) to PHY_REPEATER_MODE when LTTPRs detected and Non-Transparent is requested. Write Transparent in all other cases. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Set LTTPR Transparent Mode after read link capWesley Chalmers1-2/+3
[WHY] SCR for DP 2.0 Spec states that a DPTX shall put LTTPRs into Transparent mode after reading LTTPR Capability registers on HPD. The wording of the SCR is somewhat ambiguous as to whether Transparent mode must be set explicity, or is implicitly set on LTTPR capability read. Explicitly setting Transparent mode after LTTPR capability read should cover all cases. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Read LTTPR caps first on bootupWesley Chalmers3-0/+8
[WHY] SCR for DP 2.0 requires that LTTPR caps be read first on hotplug. For the sake of consistency, this should also be the case on bootup. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Move LTTPR cap read into its own functionWesley Chalmers1-34/+41
[WHY] We want LTTPR capabilities to be readable from more places than just retrieve_link_cap Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Read LTTPR caps first on hotplugWesley Chalmers1-32/+33
[WHY] A new SCR for the DP2.0 spec requires that LTTPR caps be the first thing read from DPCD upon hotplug. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: move psr dm interface to separate filesRoman Li4-137/+205
[Why] Improve the maintain/read abilities of dm code. [How] Create amdgpu_dm_psr.c/h files. Move psr function from amdgpu_dm.c Signed-off-by: Roman Li <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: 3.2.140Aric Cyr1-1/+1
This version brings along following fixed: - LTTPR improvements - Backlight improvements - eDP hotplug detection Signed-off-by: Aric Cyr <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: [FW Promotion] Release 0.0.70Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Updated variable name.David Galiffi1-6/+6
[Why] Fixed spelling error. [How] Changed "currnet_setting" to "current_setting". Signed-off-by: David Galiffi <[email protected]> Reviewed-by: Wesley Chalmers <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Change swizzle visual confirm reference pipePo-Ting Chen1-5/+5
[Why] To change the swizzle visual confirm reference pipe from top pipe to bottom pipe due to bottom pipe information would be more important for multiple overlay case. Signed-off-by: Po-Ting Chen <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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