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2023-04-11drm/amd/display : Log DP link training downspread infoSrinivasan Shanmugam1-6/+8
Update the existing log with DP LT downspread info: [Downstream devices shall support down spreading of the link clock. The down-spread amplitude shall either be disabled (0.0%) or up to 0.5%, as written by the upstream device to the DOWNSPREAD_CTRL register (DPCD 00107h). The modulation frequency range shall be 30 to 33 kHz] Besides, fix checkpatch warning: CHECK: Alignment should match open parenthesis Cc: Mario Limonciello <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Leo Li <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: remove unused matching_stream_ptrs variableTom Rix1-4/+1
clang with W=1 reports drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_enc_cfg.c:625:6: error: variable 'matching_stream_ptrs' set but not used [-Werror,-Wunused-but-set-variable] int matching_stream_ptrs = 0; ^ This variable is not used so remove it. Reviewed-by: Nick Desaulniers <[email protected]> Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: set variables dml*_funcs storage-class-specifier to staticTom Rix1-12/+12
smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:44:24: warning: symbol 'dml20_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:51:24: warning: symbol 'dml20v2_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:58:24: warning: symbol 'dml21_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:65:24: warning: symbol 'dml30_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:72:24: warning: symbol 'dml31_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:79:24: warning: symbol 'dml314_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:86:24: warning: symbol 'dml32_funcs' was not declared. Should it be static? These variables are only used in one file so should be static. Cleanup whitespace, use tabs consistently for indents. Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: set variables aperture_default_system and ↵Tom Rix1-2/+2
context0_default_system storage-class-specifier to static smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hubp.c:758:10: warning: symbol 'aperture_default_system' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hubp.c:759:10: warning: symbol 'context0_default_system' was not declared. Should it be static? These variables are only used in one file so should be static. Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: set variable dcn3_14_soc storage-class-specifier to staticTom Rix1-1/+1
smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/dcn314_fpu.c:100:37: warning: symbol 'dcn3_14_soc' was not declared. Should it be static? This variable is only used in one file so should be static. Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: Fix warningsLijo Lazar1-1/+1
Fix below warning due to incompatible types in conditional operator ../pm/swsmu/smu13/smu_v13_0_6_ppt.c:315:17: sparse: sparse: incompatible types in conditional expression (different base types): Signed-off-by: Lijo Lazar <[email protected]> Reported-by: kernel test robot <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Link: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/pm: correct SMU13.0.7 max shader clock reportingHoratio Zhang1-1/+60
Correct the max shader clock reporting on SMU 13.0.7. Signed-off-by: Horatio Zhang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/pm: correct SMU13.0.7 pstate profiling clock settingsHoratio Zhang1-7/+15
Correct the pstate standard/peak profiling mode clock settings for SMU13.0.7. Signed-off-by: Horatio Zhang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: refine get gpu clock counter methodTong Liu011-2/+15
[why] regGOLDEN_TSC_COUNT_LOWER/regGOLDEN_TSC_COUNT_UPPER are protected and unaccessible under sriov. The clock counter high bit may update during reading process. [How] Replace regGOLDEN_TSC_COUNT_LOWER/regGOLDEN_TSC_COUNT_UPPER with regCP_MES_MTIME_LO/regCP_MES_MTIME_HI to get gpu clock under sriov. Refine get gpu clock counter method to make the result more precise. Signed-off-by: Tong Liu01 <[email protected]> Acked-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: optimize redundant code in umc_v6_7YiPeng Chai1-91/+70
Optimize redundant code in umc_v6_7. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: Fix sdma v4 sw fini errorlyndonli1-1/+1
Fix sdma v4 sw fini error for sdma 4.2.2 to solve the following general protection fault [ +0.108196] general protection fault, probably for non-canonical address 0xd5e5a4ae79d24a32: 0000 [#1] PREEMPT SMP PTI [ +0.000018] RIP: 0010:free_fw_priv+0xd/0x70 [ +0.000022] Call Trace: [ +0.000012] <TASK> [ +0.000011] release_firmware+0x55/0x80 [ +0.000021] amdgpu_ucode_release+0x11/0x20 [amdgpu] [ +0.000415] amdgpu_sdma_destroy_inst_ctx+0x4f/0x90 [amdgpu] [ +0.000360] sdma_v4_0_sw_fini+0xce/0x110 [amdgpu] Signed-off-by: lyndonli <[email protected]> Reviewed-by: Likun Gao <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: DROP redundant drm_prime_sg_to_dma_addr_arrayShane Xiao1-3/+0
For DMA-MAP userptr on other GPUs, the dma address array will be populated in amdgpu_ttm_backend_bind. Remove the redundant call from the driver. v2: update the comment Signed-off-by: Shane Xiao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: optimize redundant code in umc_v8_10YiPeng Chai3-120/+115
Optimize redundant code in umc_v8_10 Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11amd/amdgpu: Inherit coherence flags base on original BO flagsShane Xiao1-4/+8
For SG BO to DMA-map userptrs on other GPUs, the SG BO need inherit MTYPEs in PTEs from original BO. If we set the flags, the device can be coherent with the CPUs and other GPUs. v2: 1. Drop unnecessary flags check 2. Remove local variable align Signed-off-by: Shane Xiao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/pm: Fix incorrect comment about Vangogh power cap supportGuilherme G. Piccoli1-2/+2
The comment mentions that power1 cap attributes are not supported on Vangogh, but the opposite is indeed valid: for APUs, only Vangogh is supported. While at it, also fixed the Renoir comment below (thanks Melissa for noticing that!). Cc: Lijo Lazar <[email protected]> Cc: Melissa Wen <[email protected]> Signed-off-by: Guilherme G. Piccoli <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: Add userptr bo support for mGPUs when iommu is onShane Xiao1-4/+23
For userptr bo with iommu on, multiple GPUs use same system memory dma mapping address when both adev and bo_adev are in identity mode or in the same iommu group. If RAM direct map to one GPU, other GPUs can share the original BO in order to reduce dma address array usage when RAM can direct map to these GPUs. However, we should explicit check whether RAM can direct map to all these GPUs. This patch fixes a potential issue that where RAM is direct mapped on some but not all GPUs. v2: 1. Update comment 2. Add helper function reuse_dmamap Signed-off-by: Shane Xiao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/amdgpu: Drop the hang limit parameterSrinivasan Shanmugam3-10/+1
The driver doesn't resubmit jobs on hangs any more, hence drop the hang limit parameter - amdgpu_job_hang_limit, wherever it is used. Suggested-by: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Kent Russell <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: Fix potential null dereferenceIgor Artemiev1-1/+2
The adev->dm.dc pointer can be NULL and dereferenced in amdgpu_dm_fini() without checking. Add a NULL pointer check before calling dc_dmub_srv_destroy(). Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 9a71c7d31734 ("drm/amd/display: Register DMUB service with DC") Signed-off-by: Igor Artemiev <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: 3.2.230Aric Cyr1-1/+1
This DC version brings along: - FW Release 0.0.161.0 - Improvements on FPO/FAMS - Correction to DML calculation - Fix to multiple clock related issues Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd: Fix an out of bounds error in BIOS parserMario Limonciello1-5/+2
The array is hardcoded to 8 in atomfirmware.h, but firmware provides a bigger one sometimes. Deferencing the larger array causes an out of bounds error. commit 4fc1ba4aa589 ("drm/amd/display: fix array index out of bound error in bios parser") fixed some of this, but there are two other cases not covered by it. Fix those as well. Reported-by: [email protected] Link: https://bugzilla.kernel.org/show_bug.cgi?id=214853 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2473 Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: [FW Promotion] Release 0.0.161.0Anthony Koo1-2/+26
- Add command to idle opt. - Rename d3 entry event and add idle trigger param on notify event. - Add bit to fw boot status to notify status when hardware is powered up. Reviewed-by: Aric Cyr <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: Improve robustness of FIXED_VS link training at DP1 ratesMichael Strauss6-3/+396
[WHY] New sequence for transparent mode DP1.x link training was provided by LTTPR vendor [HOW] Implement new FIXED_VS sequence, increase LT retry count to minimize any potential intermittent lightup failures Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: Add MES KIQ clear to tell RLC that KIQ is dequeuedYifan Zha1-2/+12
[Why] As MES KIQ is dequeued, tell RLC that KIQ is inactive [How] Clear the RLC_CP_SCHEDULERS Active bit which RLC checks KIQ status In addition, driver can halt MES under SRIOV when unloading driver v2: Use scheduler0 mask to clear KIQ portion of RLC_CP_SCHEDULERS Signed-off-by: Yifan Zha <[email protected]> Reviewed-by: Horace Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: add dscclk instance offset checkCharlene Liu3-0/+30
[why] based on dscclk instance offset check conditiona program dscclk Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: On clock init, maintain DISPCLK freqAlvin Lee6-5/+45
[Description] - On init if a display is connected, we need to maintain the DISPCLK frequency - Even though DPG_EN=1, the display still requires the correct timing or it could cause audio corruption (if DISPCLK freq is reduced) - Read the current DISPCLK freq and request the same value to ensure the timing is valid and unchanged - However, add option to do a full pipe power down (including link) which will also avoid audio related issues - Disabled for the time being on dcn32 Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: Add FPO + VActive supportAlvin Lee8-3/+267
[Description] - When determining FPO support, include FPO + VActive support - Support FPO + VActive if one display meets regular requirements for FPO and the second display is able to switch in VACTIVE with a given amount of margin Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: Correct DML calculation to follow HW SPECPaul Hsieh4-4/+4
[Why] In 2560x1600@240p eDP panel, driver use lowest voltage level to play 1080p video cause underflow. According to HW SPEC, the senario should use high voltage level. [How] ChromaPre value is zero when bandwidth validation. Correct ChromaPre calculation. Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Paul Hsieh <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: prep work for root clock optimization enablement for DCN314Hamza Mahfooz2-1/+33
To enable root clock optimizations, we need a number of register writes and need to account for the difference in DPSTREAMCLK between DCN31 and DCN314. To prevent issues, add a number of register writes to DCCG_MASK_SH_LIST_DCN314_COMMON(), and define dccg314_init() which is mostly in alignment with dccg31_init() but accounts for the new DPSTREAMCLK sequence. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: add scaler control for dcn32Zhikai Zhai1-0/+1
[WHY] It will introduce the extra warnning log on some asic that doesn't register [HOW] Add the register on dcn32 Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Zhikai Zhai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: Clear FAMS flag if FAMS doesn't reduce vlevelAlvin Lee1-0/+4
[Description] - If we find that applying FAMS doesn't reduce the voltage level, we will not use it - Ensure to clear the stream flags indicating FAMS if we hit this case Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: Add MES KIQ dequeue in MES hw finiYifan Zha1-6/+11
[Why] Need dequeue MES KIQ under SRIOV when unloading driver [How] Modify mes_v11_0_kiq_dequeue_sched which was used to dequeue MES SCHED to support veriable pipe. Add MES KIQ dequeue in hw fini Signed-off-by: Yifan Zha <[email protected]> Reviewed-by: Horace Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: remove unused average_render_time_in_us and i variablesTom Rix1-14/+0
clang with W=1 reports drivers/gpu/drm/amd/amdgpu/../display/modules/freesync/freesync.c:1132:15: error: variable 'average_render_time_in_us' set but not used [-Werror,-Wunused-but-set-variable] unsigned int average_render_time_in_us = 0; ^ This variable is not used so remove it, which caused i to be unused so remove that as well. Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: add new parameters in v11_structArvind Yadav1-8/+8
Added some new parameters defined for the gfx usermode queues use cases in the v11_mqd_struct. Cc: Alex Deucher <[email protected]> Cc: Christian Koenig <[email protected]> Reviewed-by: Shashank Sharma <[email protected]> Signed-off-by: Arvind Yadav <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/amdgpu: introduce gc_*_mes_2.bin v2Jack Xiao2-9/+27
To avoid new mes fw running with old driver, rename mes schq fw to gc_*_mes_2.bin. v2: add MODULE_FIRMWARE declaration v3: squash in fixup patch Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: allow more APUs to do mode2 reset when go to S4Tim Huang1-1/+6
Skip mode2 reset only for IMU enabled APUs when do S4. This patch is to fix the regression issue https://gitlab.freedesktop.org/drm/amd/-/issues/2483 It is generated by commit b589626674de ("drm/amdgpu: skip ASIC reset for APUs when go to S4"). Fixes: b589626674de ("drm/amdgpu: skip ASIC reset for APUs when go to S4") Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2483 Tested-by: Yuan Perry <[email protected]> Signed-off-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11ACPI: video: Remove register_backlight_delay module option and codeHans de Goede1-4/+0
Since commit 5aa9d943e9b6 ("ACPI: video: Don't enable fallback path for creating ACPI backlight by default"), the delayed registering of acpi_video# backlight devices has been disabled by default. The few bugreports where this option was used as a workaround were all cases where the GPU driver did not call acpi_video_register_backlight() and the workaround was to pass video.register_backlight_delay=1. With the recent "ACPI: video: Make acpi_backlight=video work independent from GPU driver" changes acpi_backlight=video can be used to achieve the same result. So there is no need for the register_backlight_delay option + code anymore. Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Hans de Goede <[email protected]> Signed-off-by: Rafael J. Wysocki <[email protected]>
2023-04-11powerpc/64: Always build with 128-bit long doubleMichael Ellerman1-1/+1
The amdgpu driver builds some of its code with hard-float enabled, whereas the rest of the kernel is built with soft-float. When building with 64-bit long double, if soft-float and hard-float objects are linked together, the build fails due to incompatible ABI tags. In the past there have been build errors in the amdgpu driver caused by this, some of those were due to bad intermingling of soft & hard-float code, but those issues have now all been fixed since commit 58ddbecb14c7 ("drm/amd/display: move remaining FPU code to dml folder"). However it's still possible for soft & hard-float objects to end up linked together, if the amdgpu driver is built-in to the kernel along with the test_emulate_step.c code, which uses soft-float. That happens in an allyesconfig build. Currently those build errors are avoided because the amdgpu driver is gated on 128-bit long double being enabled. But that's not a detail the amdgpu driver should need to be aware of, and if another driver starts using hard-float the same problem would occur. All versions of the 64-bit ABI specify that long-double is 128-bits. However some compilers, notably the kernel.org ones, are built to use 64-bit long double by default. Apart from this issue of soft vs hard-float, the kernel doesn't care what size long double is. In particular the kernel using 128-bit long double doesn't impact userspace's ability to use 64-bit long double, as musl does. So always build the 64-bit kernel with 128-bit long double. That should avoid any build errors due to the incompatible ABI tags. Excluding the code that uses soft/hard-float, the vmlinux is identical with/without the flag. It does mean any code which is incorrectly intermingling soft & hard-float code will build without error, so those bugs will need to be caught by testing rather than at build time. For more background see: - commit d11219ad53dc ("amdgpu: disable powerpc support for the newer display engine") - commit c653c591789b ("drm/amdgpu: Re-enable DCN for 64-bit powerpc") - https://lore.kernel.org/r/[email protected] Signed-off-by: Michael Ellerman <[email protected]> Reviewed-by: Segher Boessenkool <[email protected]> Link: https://msgid.link/[email protected]
2023-04-03Merge tag 'amd-drm-next-6.4-2023-03-31' of ↵Daniel Vetter118-456/+118752
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.4-2023-03-31: amdgpu: - Misc code cleanups - S4 fixes - MES fixes - SR-IOV fixes - Link DC backlight to connector device rather than PCI device - W=1 fixes - ASPM quirk - RAS fixes - DC dynamic split fixes and enablement for remaining chips - Navi1x SMU fix - Initial NBIO 7.9 support - Initial GC 9.4.3 support - Initial GFXHUB 1.2 support - Initial MMHUB 1.8 support - DCN 3.1.5 fixes - Initial DC FAMs infrastructure - Add support for 6.75Gbps link rates - Add sysfs nodes for secondary VCN clocks amdkfd: - Initial support for GC 9.4.3 radeon: - Convert to client-based fbdev emulation Signed-off-by: Daniel Vetter <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-04-03Merge 6.3-rc5 into driver-core-nextGreg Kroah-Hartman43-156/+549
We need the fixes in here for testing, as well as the driver core changes for documentation updates to build on. Signed-off-by: Greg Kroah-Hartman <[email protected]>
2023-03-31drm/amd/pm: enable sysfs node vclk1 and dclk1 for NV3XTong Liu011-2/+6
Enable node pp_dpm_vclk1 and pp_dpm_dclk1 for gc11.0.2 and gc11.0.3 Signed-off-by: Tong Liu01 <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-31drm/amd/pm: enable sysfs node vclk1 and dclk1 for NV2XTong Liu011-0/+8
Enable vclk1 and dclk1 node for gc10.3.0 and gc10.3.1 Signed-off-by: Tong Liu01 <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-31drm/amd/pm: add sysfs node vclk1 and dclk1Tong Liu013-0/+42
User can check pp_dpm_vclk1 and pp_dpm_dclk1 for DPM frequency of vcn and dcn Signed-off-by: Tong Liu01 <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-31drm/amd/display: Mark function 'optc3_wait_drr_doublebuffer_pending_clear' ↵Caio Novais1-1/+1
as static Compiling AMD GPU drivers displays a warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.c:294:6: warning: no previous prototype for ‘optc3_wait_drr_doublebuffer_pending_clear’ [-Wmissing-prototypes] Get rid of it by marking the function as static Signed-off-by: Caio Novais <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-31drm/amdkfd: Set TG_CHUNK_SIZE for GC 9.4.3Amber Lin1-0/+15
On GC 9.4.3, DW 41 in MQD is repurposed as compute_tg_chunk_size for cooperative dispatch. When it's a AQL queue, set compute_tg_chunk_size as 1 to spread work groups evenly among XCCs. If it's PM4 queue, unset compute_tg_chunk_size to disable cooperative mode. v3: set compute_tg_chunk_size as 1 instead of #CUs per XCC v2: set compute_tg_chunk_size as #CUs per XCC instead of total wave slots per XCC Signed-off-by: Amber Lin <[email protected]> Reviewed-by: Sean Keely <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-31drm/amdkfd: Trap handler changes for GC 9.4.3 v2Jay Cornwall3-19/+526
v1: Check new exception bits in TRAPSTS register Remove single step exception workaround, now part of exception bits v2: GC 9.4.3 uses ttmp11 to store {1’b0, dispatch index [24:0], wave_id_in_workgroup[5:0]}, so use ttmp13 instead of ttmp11 to preserve ib_sts. (Laurent) Signed-off-by: Jay Cornwall <[email protected]> Signed-off-by: Laurent Morichetti <[email protected]> Reviewed-by: Laurent Morichetti <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-31drm/amd/display: Remove unused variable 'scl_enable'Caio Novais1-2/+0
Compiling AMD GPU drivers displays a warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c: In function ‘dml_rq_dlg_get_dlg_params’: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:991:14: warning: variable ‘scl_enable’ set but not used [-Wunused-but-set-variable] Get rid of it by removing the variable 'scl_enable'. Signed-off-by: Caio Novais <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-31drm/amdkfd: Set noretry/xnack for GC 9.4.3Amber Lin2-1/+3
For GC 9.4.3, disable retry as default and XNACK can be different modes per process. Signed-off-by: Amber Lin <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-31drm/amd/display: Whitespace cleanupUwe Kleine-König1-13/+13
Commit 075e2099c32c ("drm/amd/display: Fix race condition in DPIA AUX transfer") was backported to stable, which I noticed because of git saying linux-6.1/.git/rebase-apply/patch:37154: space before tab in indent. while applying patch-6.1.21. While fixing the code location that issued that warning, improve in few more places. Signed-off-by: Uwe Kleine-König <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-31drm/amdkfd: Add GC 9.4.3 KFD supportHawking Zhang3-1/+8
Add initial KFD support Convert a few structures to IP version checking (Hawking) Signed-off-by: Elena Sakhnovitch <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Amber Lin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-31drm/amd/display: Promote DAL to 3.2.229Aric Cyr1-1/+1
This DC version brings along: - Enable FPO optimization - Support for 6.75 GBps link rate - Fixes to underflow, black screen and more Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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