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2022-05-04drm/amdgpu: do not use passthrough mode in Xen dom0Marek Marczykowski-Górecki1-1/+3
While technically Xen dom0 is a virtual machine too, it does have access to most of the hardware so it doesn't need to be considered a "passthrough". Commit b818a5d37454 ("drm/amdgpu/gmc: use PCI BARs for APUs in passthrough") changed how FB is accessed based on passthrough mode. This breaks amdgpu in Xen dom0 with message like this: [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 While the reason for this failure is unclear, the passthrough mode is not really necessary in Xen dom0 anyway. So, to unbreak booting affected kernels, disable passthrough mode in this case. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1985 Fixes: b818a5d37454 ("drm/amdgpu/gmc: use PCI BARs for APUs in passthrough") Signed-off-by: Marek Marczykowski-Górecki <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2022-05-04drm/amdgpu/discovery: add VCN 4.0 SupportJames Zhu1-0/+6
Enable VCN 4.0 on asics where it is present. Signed-off-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: add vcn_4_0_0 video codec queryJames Zhu1-0/+44
Add vcn_4_0_0 video codec query. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu/vcn: enable vcn4 dpg modeJames Zhu1-0/+1
Enable vcn4 dpg mode. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu/jpeg: enable JPEG PG and CG for VCN4_0_0James Zhu1-1/+3
Enable JPEG PG and CG for VCN4_0_0. Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Sonny Jiang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: enable VCN4 PG and CG for VCN4_0_0Leo Liu1-2/+4
Most of the tiles can be power/clock gated. Reviewed-by: Sonny Jiang <[email protected]> Signed-off-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu/jpeg: add jpeg support for VCN4_0_0James Zhu3-1/+640
Add jpeg support for VCN4_0_0. Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Sonny Jiang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: add VCN4 ip block supportLeo Liu5-2/+1940
Add VCN 4.0 initialization and decoder/encoder ring functions. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: James Zhu <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: add irq sources for vcn v4_0James Zhu1-0/+41
Add the interrupt source packet definitions for VCN4. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: move out asic specific definition from common headerJames Zhu4-2/+9
Move out asic specific definition from common header. Acked-by: Alex Deucher <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Sonny Jiang <[email protected]> Signed-off-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: make software ring functions reuseable for newer VCNLeo Liu2-12/+23
Software ring will be supported only from VCN4 Signed-off-by: Leo Liu <[email protected]> Reviewed-by: James Zhu <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: add vcn 4_0_0 header files v7Leo Liu2-0/+9665
Add VCN 4.0.0 registers Signed-off-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: James Zhu <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu/discovery: add SDMA v6_0 ip blockStanley Yang1-0/+4
Add SDMA v6 ip block for asics which support it. Signed-off-by: Stanley Yang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: add initial support for sdma v6.0Stanley Yang3-1/+1719
Add functions for SDMA version 6. Signed-off-by: Stanley Yang <[email protected]> Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: add sdma v6_0_0 pkt header v3Hawking Zhang1-0/+5664
v1: add sdma v6_0_0 pkt definitions (Hawking) v2: add gcr control field definition (Likun) v3: correct some definitions (Likun) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amd/display: 3.2.184Aric Cyr1-1/+1
This version brings along following fixes: - Have optc3 function accessible to newer DCN - Add CM boot option for USB4 tunneling - Fix system hang issue when game resolution is changed - Remove outdated register for dcn3+ - Add new DSC interface to disconnect from pipe - Clean up pixel format types in enum surface_pixel_format Acked-by: Wayne Lin <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amd/display: [FW Promotion] Release 0.0.115.0Anthony Koo1-1/+34
- Add new cmd for querying HPD state Reviewed-by: Aric Cyr <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amd/display: Clean up pixel format typesAric Cyr1-1/+2
[Why & How] Equate the first non-subsampled video surface format to the enum SURFACE_PIXEL_FORMAT_SUBSAMPLE_END since it's not a real format. Acked-by: Wayne Lin <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amd/display: Add new DSC interface to disconnect from pipeEric Bernstein2-0/+12
[Why & How] Add new DSC interface to disconnect from pipe. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Eric Bernstein <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amd/display: Remove outdated register for dcn3+Tse, Kaitlyn1-5/+0
[Why & How] Remove MPCC_OGAM_LUT_RAM_CONTROL register which is outdated. Reviewed-by: Nevenko Stupar <[email protected]> Reviewed-by: Martin Leung <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Tse Kaitlyn <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04Revert "drm/amd/display: Reset cached PSR parameters after hibernate"Evgenii Krasnikov1-6/+1
This reverts commit d2069326d26c7de78e77a060fb6e6d0d21c35dbd. Commit d2069326d26c ("drm/amd/display: Reset cached PSR parameters after hibernate") causes a system hang when game resolution is changed. Revert it. Reviewed-by: Jayendran Ramani <[email protected]> Reviewed-by: Harry Vanzylldejong <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Evgenii Krasnikov <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amd/display: Add Connection Manager boot option.Jimmy Kizito3-1/+4
[Why] Boot up behaviour may differ depending on the Connection Manager handling USB4 tunneling. [How] Send boot option to firmware to indicate Connection Manager. Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Jimmy Kizito <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amd/display: Make OPTC3 function accessible to other DCNLee, Alvin1-1/+1
[Why] Newer DCN should use optc3 [How] Declare optc3 vmin/vmax function in header. Reviewed-by: Harry Vanzylldejong <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu/discovery: add MES11 supportAlex Deucher1-6/+15
Enable MES 11 on asics which support it. Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu/discovery: add GFX 11.0 SupportLikun Gao1-0/+4
Enable GFX 11.0 on asics where it is present. Signed-off-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu/gfx11: enable kiq to map mes ringJack Xiao2-66/+57
Enable KIQ to map MES ring: 1). add MES queue mapping support in MAP_QUEUES packet. 2). use correct MQD settings for MES queue. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu/gfx10: enable kiq to map mes ringJack Xiao2-67/+55
Enable KIQ to map MES ring: 1). add MES queue mapping support in MAP_QUEUES packet. 2). use correct MQD settings for MES queue. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: enable GENERIC0_INT for gfx/compute pipesHawking Zhang1-0/+8
To generate an interrupt to RLC for accessing indirect registers that CP can not access directly Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: enable fgcg for soc21Evan Quan1-1/+2
Enable Fine Grained Clock Gating on soc21 asics. Signed-off-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: enable GFX CGCG/CGLS for GC11.0.0Evan Quan1-1/+2
Enable GFX CGCG (coarse grained clockgating) and CGLS (coarse grained light sleep) for GC11.0.0. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdkfd: Add KFD support for soc21 v3Mukul Joshi20-64/+2024
Add initial support for soc21 in KFD compute driver (Mukul) - Add new definition for soc21 device. - Add new file for amdgpu-kfd interface for GFX11 family. - Add new file for queue management, interrupt handling, mqd management for GFX11 family in KFD driver. - Related changes/updates for soc21 device in KFD driver. - Repurpose last 2 entries of SDMA MQD for driver use. v2: Add an optional argument into update queue operation (Mukul) v3: Switch to ip version check, replace kgd_dev with amdgpu_device (Hawking) Signed-off-by: Mukul Joshi <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Oak Zeng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdkfd: add helper to generate cache info from gfx configAlex Deucher1-0/+72
Rather than using hardcoded tables, we can use the gfx and gmc config pulled from the IP discovery table to generate the cache configuration. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: add init support for GFX11 (v2)Hawking Zhang4-1/+6364
Add initial support for GC version 11. GC is the graphics and compute block on the GPU. v1: add initial gfx11 support (Wenhui) v2: switch to new amdgpu_gfx_is_high_priority_compute_queue interface (Hawking) v3: fix num_mec (Alex) Signed-off-by: Wenhui Sheng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu/mes11: initiate mes v11 supportJack Xiao4-1/+1814
Initiate mes v11 code base from mes v10, rename function and register names. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: support imu for gfx11Likun Gao6-1/+386
Add support to initialize imu for gfx v11. IMU is a new power management block for gfx which manages gfx power. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: add mes unmap legacy queue routineJack Xiao7-151/+526
For mes kiq has been taken over by mes sched, drv can't directly use mes kiq to unmap queues. drv has to use mes sched api to unmap legacy queue. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: support RS64 CP fw front door loadLikun Gao1-0/+57
Support to load RS64 CP firmware front door load. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: renovate sdma fw structLikun Gao2-0/+25
Add sdma firmware struct version 2 to support new SDMA v6 and forward firmware version. v2: squash in fix Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu/discovery: handle AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO in SMUAlex Deucher1-2/+3
Handle SMU load ordering when firmware load type is AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO. This works similarly to AMDGPU_FW_LOAD_DIRECT where the SMU load order is different from the standard ordering when front door loading is enabled. Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: fix the fw size for sdmaLikun Gao1-2/+2
For SDMA, if use the total size of SDMA TH0 and TH1 to allocate fw BO may result to the ucode data overflow when copy ucode to BO as the PAGE alignment. IMU have the same issue. Fix the above issue by alignment the fw size per fw ID. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amd/amdgpu: add more fw load type to fit new ASICsChengming Gui1-1/+1
Align exported fw load types with internal used. Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: correct cp doorbell rangeJack Xiao3-3/+16
1. move MES doorbell inside the mec doorbell range, for mes belongs to mec block 2. setting the correct gfx/mec doorbell range, so that fw can correctly detect gfx/compute work load to enter/exit power saving state. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Tested-and-acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amd/amdgpu: adjust the fw load type listChengming Gui1-1/+1
Use 0 for legacy backdoor and 1 for frontdoor. Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu/gfx: refine fw hdr check fuctionLikun Gao1-2/+2
The return value of function amdgpu_ucode_hdr_version doesn't make sense, so change it to return true when fw header version is match with passed in parameters. Signed-off-by: Wenhui Sheng <[email protected]> Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: extend the show ucode name functionLikun Gao1-0/+16
Extend amdgpu_ucode_name function to show SDMA TH0, TH1, IMU, RLCP, RLCV and MES related ucode name via ucode id. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: init SDMA v6 microcode with PSP load typeLikun Gao1-0/+2
Update to use new SDMA UCODE ID when init sdma microcode for sdma6 with psp front door load type. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: add convert for new gfx typeLikun Gao2-0/+44
Add convert for CP RS64 related gfx ip type. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: support IMU front door loadLikun Gao3-0/+21
Support for front door to load IMU firmware. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: add new CP_MES ucode idsJack Xiao1-0/+2
Needed for MES KIQ firmware loading. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-05-04drm/amdgpu: support for new SDMA front door loadLikun Gao2-0/+18
Support for SDMA v6_0 ucode front door load. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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